Report Evaluation Form: EE 365 Advanced Digital Design, Fall 2014

Total Grade _______/50

Project Title: 7 Segment Display: TTL & SPI via GPIO Project Grade _______/25

Report Writers: Joseph Crandall, Zachary Rauen Report Grade _______/25

I. Report Content (20 points): For each area below, 0 points are given if it is completely missing.

A. Summary (Executive summary or abstract) ____/2 Should summarize the design problem, the overall approach, and the results in terms of how well the specifications

were met. ____Excellent _____Good _____Average _____Fair _____None

B. Design Problem Statement (Interpretation of the Specification) ____/2Should explain what was to be designed, what assumptions were made, what constraints were placed on your design.____Excellent _____Good _____Average _____Fair _____None

C. Problem Decomposition ____/4Should describe the overall design in terms of functional blocks needed to meet the specifications. Should describe what each functional block is intended to do. There should be a block diagram that includes inputs and outputs of each functional block.____Excellent _____Good _____Average _____Fair _____None

D. Detailed Design ____/6Should describe how the design works in sufficient detail that a knowledgeable person is able to understand and verify that the design is technically sound. There should be documentation sufficient to allow a knowledgeable person to duplicate your design. You should have schematics for all hardware and source code for all programmable logic, VHDL, etc. ____Excellent _____Good _____Average _____Fair _____None

E. Module and Specifications Testing ____/4Should also describe how the design was tested at the module level and corrections made. Should also describe how the completed design was tested to verify, it meets specifications or to determine deviations from the specs.

____Excellent _____Good _____Average _____Fair _____None

F. Results and Analysis ____/2Should describe how well your design met the specifications and discuss any deviations from those specifications. Give an analysis of any deviations from the specification and explain what should be done to correct these.

____Excellent _____Good _____Average _____Fair _____None

II. Report form. (5 points) The report should be produced in a professional manner. Basis of Evaluation: 1 - no deficiencies, 1/2- no more than 2 minor deficiencies, 0-1 major or multiple minor deficiencies

The report is well organized, with explanatory text for each section. ____/1 The written language is clear and grammatically correct. ____/1 All figures and tables are referenced in the text and appear shortly after the reference, or are located in an appendix

with appropriate text to refer the reader there. All figures and tables have a caption____/1

All diagrams and schematics are drawn using CAD type software with no hand drawing or lettering ____/1 The report includes a list of references used in completing the design and documenting your results ____/1

A. Summary For this design project, the goal was to design an asynchronous system for the Nexys4 FPGA

board that will output a sequence of Hexadecimal values on the 7-segment displays on the board. The system also needs to display the sequence on the external Sparkfun 7-segment display using Serial TTL communication and SPI communication methods. The system operates an “effective clock “ of 1 Hz and outputs a repeating sequence of 9 values. Our overall approach was to use a Sequence Controller in conjunction with a ROM to control the output of the sequence using Reset, Reverse, and Enable buttons as inputs. The output of this ROM is then sent to the three different display entities that will output the signal to the board's 7-segment displays as well as the external one. By designing this system using a hierarchical approach, the sequence could be changed by replacing the ROM without making any changes to the rest of the circuit (Minor changes could be made to the Sequence Controller to increase the amount of values in the sequence).This design worked extremely well and performed exactly to the specifications that were given in the design problem.

B. Design Problem Statement Our design is a 7-segment controller that takes three button inputs and a clock as input from the

FPGA and outputs the HEX sequence:0000, 0A0A, 5050, FE45, AABB, CCDD, FEED, DEAD, BEEF

on the 7-segment display. This sequence should repeat when it is operational, and should be displayed on the 4 7 segment displays on the right side of the board. The design is implemented using Xilinx's PlanAhead CAD tool. This sequence is stored in Xilinx's single port ROM/RAM IP-core for this design. This design uses a specific sequence of values but was designed generically in a way that would make it easy to display a different signal. The board is unable to display on multiple 7-segment displays at once. In order to work around this restriction, we use two separate counters attached to separate clock enablers. One clock will run at an “effective clock” of 1 KHz and will control each individual 7-segment display and what it outputs. This will allow it appear as if all of the displays are working simultaneously while they are really just working one at a time. The second clock enabler will run at an “effective clock” of 1 Hz and will control which value will be sent to the output. This will allow each number in the sequence to be displayed for one second.

The design also calls for a reset button that will allow the system to restart at the beginning of the sequence one second after the button is depressed; BTNC on the Nexys 4 should perform this function. A reverse button that will toggle the system to output in the reverse order if pressed; BTNL should perform this function. An enabler button that will stop the sequence from changing if it is pressed and will allow it to continue from where it left off if pressed again; BTNR should perform this function. These buttons needed to be debounced before their signals were sent to the controller, and the signal was to be displayed on the 4 7-segment displays on the right side of the board.

In addition to the 7-segment displays on the board, this design specification also calls for the system to display a 16 bit HEX number on the Nexys3's on-board 4 seven segment displays. This is to be designed using a TTL Serial Communication controller and an SPI Serial Peripheral controller to display the signal on an external serial 7-segment display. These two design methods are to be separate entities and are self-contained designs.

The "Serial_TTL_display" entity consists of a clock and the 16-bit data as inputs and a single wire RX output that sends the final data to the external board.

The "SPI_display" entity consists of a clock and the 16-bit data as inputs and 3 wires, MOSI, CSN, and SCK as outputs that send the final data to the external board.

Finally, we were to use a Testbench file to test the overall designs functionality using Xilinx’s ISim simulator and a Chipscope logic Analyzer was to be used to debug the code.

C. Problem Decomposition

Top-Level Block Diagram

RTL Block Diagram

The design of this 7 segment display circuit requires 4 blocks in order to work as intended. The first three blocks in the circuit are used to debounce the button input signals and make sure that the user input it interpreted correctly. When a button on the Nexys 4 is pressed, there is an unintended bouncing from a mechanical button that could cause an input to be interpreted incorrectly. The debouncer makes sure that only the user's intended signal is sent to the controller.

There is one block called Enabler_debounce which takes the enabler signal and the clk signal as inputs and doubounces the button press on BTNR and toggles an active high enable signal as an output for the top level.

Another block called Reset_debounce takes the reset signal and the clk signal as inputs and debounces the button press on BTNC and toggles an active high reset signal as an output for the top level.

The final debouncing block is called Reverse_debounce. This takes the reverse signal and the clk signal as inputs and debounces the button press on BTNL and toggles an active high reverse signal as an output for the top level.

The next functional block is called the Sequence Controller. This is a complicated part of the design as it takes the clk, enabler, reset, and reverse signals as inputs. The purpose of this block is to intereperet the inputs of the 3 buttons and constantly output the correct memory address forward to the ROM. When no buttons are being pressed and the enabler is toggled on, the Sequence controller should send out a new memory address every second which will allow the displays to show the next value in the sequence. Pressing the reset button should have the sequence controller send out the first memory address for 0000 until it is depressed. Pressing the reset button should have the sequence controller begin sending out the memory addresses in the reverse order until it is toggled again.

The next functional block the ROM. This ROM will be generated using Xilinx Planahead and will hold the desired sequence 0000, 0A0A, 5050, FE45, AABB, CCDD, FEED, DEAD, BEEF each at a specific memory address. The ROM takes the integer memory address output from the Sequence Controller as an input and will output a 16 bit binary representation of the 4 character Hex value to the Board Display, TTL Display, and SPI Display entities.

The final three entities are the Board Display, TTL Display, and SPI Display entities. These three blocks each take the Data output of the ROM as their input as well as the top-level clock. The Board Display will interpret the input and will send out a 7-Seg Cathode and a 7-Seg Anode output that will control the displays on the Nexys 4 board's 7-segment displays. The TTL Display will interpret the Data and will output the Hexadecimal value to the output wire RX that can be used with the external Sparkfun display using the Serial TTL Display method. Finally, the SPI Display will interpret the input and will send out an SCK, SS, and MOSI wire as outputs that will control the external Sparkfun display using the SPI display method. Both the TTL Display and Board Display will be standalone outputs and can be used separately.

In this design, the debouncer blocks that will be used all begin with the toggle outputs as HIGH. This will cause the system to start counting down in reverse. Since we want the system to being counting the sequence in the forward direction, an inverter should be placed at the end of the Reverse_debounce output to make the system function normally.

D. Detailed Design The two different main components that are part of our top level design are the button

debouncers, a sequence controller that sends data to the ROM. The ROM sends data to 3 different entities that control the output 7-segment displays. One of them called BoardDisplay outputs data to the Nexys' 7-segment displays while the other two send data to an external display unit using TTL Serial communication and SPI communication methods (called Serial_TTL_display and SPI_display respectively. These two outputs work separately and one or the other can be used.

Top level code shown below:------------------------------------------------------------------------------------Code by: Joe Crandall, Zachary Rauen--Date: 10/6/14--Last Modified: 11/2/14----

----Version: 1.2----------------------------------------------------------------------------------

library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;use IEEE.std_logic_unsigned.all; -- add to do arithmetic operationsuse IEEE.std_logic_arith.all; -- add to do arithmetic operations

entity top_level is Generic (constant SequenceDisplaySpeed : integer := 1; -- 1 Hz constant RefreshSpeed : integer := 1000; -- 1 KHz constant sequenceCount : integer := 8; constant BoardClock : integer := 100000000; constant buttonMax: std_logic_vector(15 downto 0) := X"FFFF"; constant baud : integer := 9600; constant SPIspeed : integer :=250000);-- Generic (constant MaxClkEnable : integer := 5;-- constant MaxDispEnable : integer := 41;-- constant sequenceCount : integer := 8;-- constant buttonMax: std_logic_vector(15 downto 0) := X"0002";-- constant baud : integer := 9600;-- constant SPIspeed : integer :=250000);-- The above lines are used for simulation and chipscope. Port ( clk : in std_logic; reset : in std_logic; reverse : in std_logic; enabler : in std_logic; DispVector : out std_logic_vector(7 downto 0); SegVector : out std_logic_vector(7 downto 0); oRx : out std_logic; oSCK : out std_logic; oSS : out std_logic; oMOSI : out std_logic);

end top_level;

architecture Behavioral of top_level is

component BoardDisplay is Generic (RefreshRate : integer := 1000; ClockSpeed : integer := 100000000); Port ( ClockState : in std_logic; Data : in std_logic_vector(15 downto 0); DisplayVector : out std_logic_vector(7 downto 0); SegmentVector : out std_logic_vector(7 downto 0));end component BoardDisplay;

component SequenceController is Generic (NumOfSequences : integer := 8; DesiredDisplaySpeed : integer := 100000; InputClockSpeed : integer := 100000000); Port ( ClockState : in std_logic; Enabler : in std_logic; Reset : in std_logic; Reverse : in std_logic; MemAddress : out integer := 0);end component SequenceController;

component Serial_TTL_display is Generic (BaudSpeed : integer :=9600; Boardspeed : integer :=100000000); Port ( Clock : in STD_LOGIC; Data : in STD_LOGIC_VECTOR (15 downto 0); RX : out STD_LOGIC);end component Serial_TTL_display;

component btn_debounce_toggle isGENERIC (

CONSTANT CNTR_MAX : std_logic_vector(15 downto 0) := X"FFFF"); Port ( BTN_I : in STD_LOGIC; CLK : in STD_LOGIC; BTN_O : out STD_LOGIC; TOGGLE_O : out STD_LOGIC);end component btn_debounce_toggle;

COMPONENT Sequence_Select PORT ( clka : IN STD_LOGIC; addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) );END COMPONENT;

component SPI_display isGeneric (constant BoardClockSpeed : integer := 100000000; constant SCKSpeed : integer := 250000); Port ( BoardClock : in STD_LOGIC; Data : in STD_LOGIC_VECTOR (15 downto 0); SCK : out STD_LOGIC; SS : out STD_LOGIC; MOSI : out STD_LOGIC );end component SPI_display;

signal resetDebounce, enablerToggle, reverseToggle : std_logic;signal DataFromRom : std_logic_vector(15 downto 0);signal DataAddress : integer;

begin

Reset_debounce: btn_debounce_toggle generic map (CNTR_MAX => buttonMax) port map (BTN_I=>reset,CLK=>clk,BTN_O=>resetDebounce,TOGGLE_O=>OPEN);

Enabler_debounce: btn_debounce_toggle generic map (CNTR_MAX => buttonMax) port map (BTN_I=>enabler,CLK=>clk,BTN_O=>OPEN,TOGGLE_O=>enablerToggle);

Reverse_debounce: btn_debounce_toggle generic map (CNTR_MAX => buttonMax) port map (BTN_I=>reverse,CLK=>clk,BTN_O=>OPEN,TOGGLE_O=>reverseToggle);

SequenceControl: SequenceController Generic map (NumOfSequences=>sequenceCount, DesiredDisplaySpeed=>SequenceDisplaySpeed, InputClockSpeed=>BoardClock) Port map (ClockState=>clk, Enabler=>enablerToggle, Reset=>resetDebounce, Reverse=> NOT reverseToggle, MemAddress=>DataAddress);

BoardController: BoardDisplay generic map (RefreshRate=>RefreshSpeed, ClockSpeed=>BoardClock) port map ( ClockState=>clk, Data=>DataFromRom, DisplayVector=>DispVector, SegmentVector=>SegVector);

TTL: Serial_TTL_displaygeneric map (BaudSpeed=>baud, Boardspeed=>BoardClock)Port map ( Clock=>clk,

Data=>DataFromRom, RX=>oRx);

Main_Rom: Sequence_Select PORT MAP ( clka => clk, addra => std_logic_vector(to_unsigned(DataAddress,4)), douta => DataFromRom );

SPI: SPI_displaygeneric map (BoardClockSpeed=>BoardClock, SCKSpeed=>SPIspeed)Port map ( BoardClock=>clk, Data=>DataFromRom, SCK=>oSCK, SS=>oSS, MOSI=>oMOSI );

end Behavioral;

Debouncer Design:There is one debouncing circuit attached to each of the input buttons from the top-level of the design.

The code we used for our version of the btn_debouncer_toggle is as follows:------------------------------------------------------------------------------ btn_debounce.vhd -- Button Debouncer------------------------------------------------------------------------------ Author: Sam Bobrowicz-- Copyright 2011 Digilent, Inc.-- Modified: Added toggle output------------------------------------------------------------------------------------------------------------------------------------------------------------ This component is used to debounce signals generated by external push-- buttons. It is designed to independently debounce a Push button signal.-- Debouncing is done by only registering a change in a button state if -- it remains constant for 2^16 clock cycles. -- -- Port Descriptions:---- BTN_I - The input button signals-- CLK - Behavior is optimized for a 100 MHz clock-- BTN_O - The debounced button signals-- TOGGLE_O - Debounced toggle output

------------------------------------------------------------------------------------------------------------------------------------------------------------ Revision History:-- 08/08/2011(SamB): Created using Xilinx Tools 13.2-- 10/06/2013 (CU): Converted to one button and added toggle output----------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.std_logic_unsigned.all;

entity btn_debounce_toggle isGENERIC (

CONSTANT CNTR_MAX : std_logic_vector(15 downto 0) := X"FFFF"); Port ( BTN_I : in STD_LOGIC; CLK : in STD_LOGIC; BTN_O : out STD_LOGIC; TOGGLE_O : out STD_LOGIC);end btn_debounce_toggle;

architecture Behavioral of btn_debounce_toggle is

--constant CNTR_MAX : std_logic_vector(15 downto 0) := X"FFFF";signal btn_cntr : std_logic_vector(15 downto 0) := (others => '0');signal btn_reg : std_logic := '0';signal btn_toggle : std_logic := '1';signal btn_sync : std_logic_vector(1 downto 0) := (others => '0');signal btn_pulse : std_logic := '0';

begin

btn_debounce_process : process (CLK)begin

if (rising_edge(CLK)) thenif (btn_cntr = CNTR_MAX) then

btn_reg <= not(btn_reg);end if;

end if;end process;

btn_counter_process : process (CLK)begin

if (rising_edge(CLK)) thenif ((btn_reg = '1') xor (BTN_I = '1')) then

if (btn_cntr = CNTR_MAX) thenbtn_cntr <= (others => '0');

elsebtn_cntr <= btn_cntr + 1;

end if;else

btn_cntr <= (others => '0');end if;

end if;end process;

btn_toggle_process : process(CLK)begin

if (rising_edge(CLK)) thenbtn_sync(0) <= btn_reg;btn_sync(1) <= btn_sync(0);btn_pulse <= not btn_sync(1) and btn_sync(0);

if btn_pulse = '1' thenbtn_toggle <= not btn_toggle;

end if;end if;

end process;

BTN_O <= btn_reg;TOGGLE_O <= btn_toggle;

end Behavioral;

Each circuit takes the button input signal as its input along with the top level clock signal. The basic principal of this design is to count to a high number and continuously check if the button is at the same level, HIGH or LOW. When checking, if the button is no longer at the same level it resets the count. When the count reaches its maximum state if the button has been at that same level it will output the same level as the button. The toggle uses the same counting process but changes the output state on every press of the button rather than just debouncing it.

Sequence Controller Design:The SequenceController designed for this project is made up of multiple parts that will each be

covered in their own sections. The purpose of this design was to design it generically so it could be altered easily and still be able to perform its intended functions. The SequenceController takes the clock (labeled ClockedState in our VHDL code below and from now on), and the output BTN_O from the

enabler, reset, and reverse button debouncers (labeled Enabler, Reset, and Reverse respectively in our VHDL code below and from now on) as inputs and outputs an integer called MemAddress.

The SequenceController is designed to take the user's input from the buttons and send the correct signal to the ROM based on the commands given. The design utilizes a clock enabler (implemented in the process DisplaySpeed) and a counter called displayCnt to accomplish this goal. The counter, called displayCnt is used to determine the memory address of the value that should be output on the 7-segment displays.

The entire code for the BoardDisplay.vhd is shown here:------------------------------------------------------------------------------------Code by: Zachary Rauen, Joseph Crandall--Date: 10/6/14--Last Modified: 11/2/14----Description: This is a sequence controller that uses three buttons as-- reset, reverse and a system enable. Using the clock this sytem will -- generate an address for a ROM. However, this can be easily-- modified in order to create what is needed----Version: 2.1----------------------------------------------------------------------------------

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity SequenceController is Generic (NumOfSequences : integer := 8; DesiredDisplaySpeed : integer := 100000; InputClockSpeed : integer := 100000000); Port ( ClockState : in std_logic; Enabler : in std_logic; Reset : in std_logic; Reverse : in std_logic; MemAddress : out integer := 0);end SequenceController;

architecture Behavioral of SequenceController is

signal clkMax : integer := InputClockSpeed/DesiredDisplaySpeed;signal clkCnt : integer range 0 to clkMax;signal displayCnt : integer := 0;signal StateEnable : std_logic;

begin

DisplaySpeed: process(ClockState)beginif rising_edge(ClockState) then if Reset <= '0' then if clkCnt = clkMax then StateEnable <= '1'; clkCnt <= 0; else clkCnt<=clkCnt+1; StateEnable <= '0'; end if; else clkCnt<=0; end if;end if;

end process DisplaySpeed;

count: process(ClockState,StateEnable,Enabler,Reverse,Reset)

begin if Reset='1' then displayCnt <= 0; else if Enabler = '1' then if rising_edge(ClockState) AND StateEnable = '1' then if Reverse = '0' then if displayCnt = NumOfSequences then displayCnt <= 0; else displayCnt <= displayCnt + 1; end if; else if displayCnt = 0 then displayCnt <= NumOfSequences; else displayCnt <= displayCnt - 1; end if; end if; end if; end if; end if;MemAddress<=displayCnt;

end process count;

end Behavioral;

ROM:Using Xilinx Planahead, a ROM template can be created that will take the memory address from

the sequence controller as an input and will output the correct HEX value in the sequence out to the display entities. A detailed explanation on how to create the ROM is included in the tutorial linked in the references section at the end of the document.

BoardDisplay:This entity takes the 16bit Hexadecimal value output from the ROM and a clock (named

Clockstate in the code) as inputs and outputs an 8 bit std_logic_vector called DisplayVector and SegmentVector as outputs.

The board is not able to display an output on multiple 7-Segment displays at one time. If we cycle through each display quicker than a human can notice however, the board will appear to be show the entire sequence at one time. This design uses a counter called segCnt to simultaneously choose which display should be used and which part of the data should be sent to the display.

The counter segCnt is designed to count from 0 to 3 since we only are interested in using the last 4 displays on the board. This could easily be changed if the customer wanted to use more or less displays. Each number corresponds to a different display. If segCnt is out of the 0-3 range, it will tell the board that all of the displays should be off. Using a clock enabler, the segCnt is designed to only increment at a speed of 1 KHz. At this speed it appears that all of the displays are working simultaneously.

At each state of segCnt, SegmentVector sends out the value of the display that is to be used with the corresponding number and the data for that value is sent to a signal called vectorSection. The value of vectorSection is sent to a lookup table which sends the final DisplayVector to the board. The main purpose of this component is to take the binary number for the Hexadecimal digit and output the signal for the 7-Segment display to light up the correct segments for each number. All 16 different outputs are programmed into it so it can be used for any programmed sequence of values.

The entire code for the BoardDisplay.vhd is shown here:------------------------------------------------------------------------------------Code by: Zachary Rauen, Joseph Crandall--Date: 10/6/14--Last Modified: 10/16/14----Description: This is a 7 segment display that takes in-- a 16 bit number and displays it across 4 7 segment displays----Version: 2.3----------------------------------------------------------------------------------

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity BoardDisplay is Generic (RefreshRate : integer := 1000; ClockSpeed : integer := 100000000); Port ( ClockState : in std_logic; Data : in std_logic_vector(15 downto 0); DisplayVector : out std_logic_vector(7 downto 0); SegmentVector : out std_logic_vector(7 downto 0));end BoardDisplay;

architecture Behavioral of BoardDisplay is

signal vectorSection : std_logic_vector(3 downto 0);signal segCnt : integer := 0;signal segCntMax : integer := 3;signal dispCarry : std_logic_vector(7 downto 0);signal SegmentEnable : std_logic;signal clkEnableMax : integer := ClockSpeed/RefreshRate;signal clkEnCnt : integer range 0 to clkEnableMax;

begin

Refresh: process(ClockState)beginif rising_edge(ClockState) then if clkEnCnt = clkEnableMax then SegmentEnable <= '1'; clkEnCnt <= 0; else clkEnCnt<=clkEnCnt+1; SegmentEnable <= '0'; end if;end if;if rising_edge(ClockState) AND SegmentEnable = '1' then if segCnt = segCntMax then segCnt <= 0; else segCnt <= segCnt + 1; end if;end if;end process Refresh;

Display: process(Data)begin

case segCnt is when 0 => SegmentVector <="11111110"; vectorSection <=Data(3 downto 0); when 1 => SegmentVector <="11111101"; vectorSection <=Data(7 downto 4); when 2 => SegmentVector <="11111011";

vectorSection <=Data(11 downto 8); when 3 => SegmentVector <="11110111"; vectorSection <=Data(15 downto 12); when others => SegmentVector <="11111111"; vectorSection <="1111";end case;

end process Display;with vectorSection select dispCarry <= "11111100" when "0000", "01100000" when "0001", "11011010" when "0010", "11110010" when "0011", "01100110" when "0100", "10110110" when "0101", "10111110" when "0110", "11100000" when "0111", "11111110" when "1000", "11110110" when "1001", "11101110" when "1010", "00111110" when "1011", "10011100" when "1100", "01111010" when "1101", "10011110" when "1110", "10001110" when "1111";

DisplayVector<= NOT dispCarry;

end Behavioral;

Serial_TTL_displayIn order to send the sequence to the external 7-segment display unit, the Serial_TTL_display

entity was designed. This entity takes the top level clock as an input and the 16-bit output values from the ROM (called DataFromRom in this design) as the other input. The output of this entity is a single wire called RX that will be used to send out each bit of the value out to the display unit. The clock enabler (called BitEnabler in this design) is designed to run the circuit at 9600 Baud.

RX is controlled using a state machine and counter simultaneously called currentState and Bytechoice respectively. CurrentState first outputs the start bit 0 to RX and then sends out each bit one at a time starting with the most significant bit and ending by outputting the stop bit 1. Bytechoice is only incremented when currentState hits the final state at bit9. At each count of Bytechoice 4 bits of the Hexadecimal number corresponding to one of the displays is sent. The Sparkfun external 7-segment display can take instructions such as a reset that will change the behavior of the device. A full list of these is provided in the manual in the references section at the end of this document. At minimum, a reset signal should be sent to the display before any data is read in. Multiple reset signals are sent at the beginning of the operation of the device as the first few counts of Bytechoice. After this, Bytechoice will start at the states that send Hexadecimal values instead of the first state. The Data input in this entity is the same as the one in the BoardDisplay so the output will be identical to the output on the board's displays. The Sparkfun display has a lookup table built in the will convert the numbers from 16bit binary into a 4 bit Hexadecimal value. This can be seen in the Serial_TTL_display.vhd file included in this document.

The entire code for the Serial_TTL_display.vhd file is included below:----------------------------------------------------------------------------------

--Code by: Zachary Rauen, Joseph Crandall--Date: 10/28/14--Last Modified: 11/2/14----Description: This takes in 16 bit data and displays them on an external display-- using GPIO and serial ttl communication.----Version: 1.3----------------------------------------------------------------------------------

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;

entity Serial_TTL_display is Generic (BaudSpeed : integer :=9600; Boardspeed : integer :=100000000); Port ( Clock : in STD_LOGIC; Data : in STD_LOGIC_VECTOR (15 downto 0); RX : out STD_LOGIC);end Serial_TTL_display;

architecture Behavioral of Serial_TTL_display is

signal DataSection : std_logic_vector(7 downto 0);type state_type is (bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit7,bit8,bit9);signal nextState : state_type;signal currentState : state_type := bit0;signal bitEnableCnt,ByteChoice : integer:=0;signal ByteMax : integer :=8;signal BitEnable : std_logic :='0';signal BaudClockEnableMax : integer := Boardspeed/BaudSpeed-1;

begin

BitEnabler: process(Clock)beginif rising_edge(Clock) then if bitEnableCnt = BaudClockEnableMax then BitEnable <= '1'; bitEnableCnt <= 0; else bitEnableCnt<=bitEnableCnt+1; BitEnable <= '0'; end if;end if;end process BitEnabler;

StateChange: process (Clock,BitEnable)beginif (rising_edge(Clock) and BitEnable='1') then if currentState = bit9 then if ByteChoice = ByteMax then ByteChoice <= Bytechoice-3; else ByteChoice<=ByteChoice+1; end if; end if;

currentState <= nextState;end if;

end process StateChange;

States: process(currentState)begincase currentState is when bit0=> RX<='0'; nextState<=bit1; when bit1=> RX<=DataSection(0); nextState<=bit2; when bit2=> RX<=DataSection(1); nextState<=bit3; when bit3=> RX<=DataSection(2); nextState<=bit4; when bit4=> RX<=DataSection(3); nextState<=bit5; when bit5=> RX<=DataSection(4); nextState<=bit6; when bit6=> RX<=DataSection(5); nextState<=bit7; when bit7=> RX<=DataSection(6); nextState<=bit8; when bit8=> RX<=DataSection(7); nextState<=bit9; when bit9=> RX<='1'; nextState<=bit0;end case;

case ByteChoice is when 0 => DataSection<=x"76"; when 1 => DataSection<=x"76"; when 2 => DataSection<=x"76"; when 3 => DataSection<=x"76"; when 4 => DataSection<=x"76";-- when 5 => DataSection<=x"7A";-- when 6 => DataSection<=std_logic_vector(to_unsigned(0, 8));-- when 6 => DataSection<=x"79";-- when 7 => DataSection<=std_logic_vector(to_unsigned(0, 8)); when 5 => DataSection <=x"0" & Data(15 downto 12); when 6 => DataSection <=x"0" & Data(11 downto 8); when 7 => DataSection <=x"0" & Data(7 downto 4); when 8 => DataSection <=x"0" & Data(3 downto 0); when others => DataSection <="11111111";end case;

end process States;

end Behavioral;

SPI_displayThe other method of sending data to the external display is through SPI communication. This

entity takes the top level clock as an input and the 16-bit output values from the ROM (called Data in this design) as the other input. The outputs of this entity are the SCK, SS, and MOSI wires that will be used to send out each bit of the value out to the display unit. The SCK is what controls how the data is read by the system, in this case the slave reads in the data. When the SCK falls the data then reads in to the slave, when the SCK is ‘0’ there is no data being read. This is designed to run at 250Khz or less with a 50% duty cycle. The SS output sends out at LOW value to the external display when data is to be displayed and HIGH when it is at the beginning or ending of the sequence. The MOSI output sends the value to the display to be shown. The clock enabler (called BitEnabler in this design) is designed to run the circuit at 500Khz meaning the SCK runs at 250Khz.

MOSI is controlled using a counter and state machine simultaneously (similarly to the TTL Serial Method) called Bytechoice and currentState. CurrentState first initializes the system, MOSI then sends out each bit one at a time for two states in a row starting with high impedance (no-repeat) then the most significant bit and ending by outputting the high impedance again. SCK starts out low at the first state (state0 in this code) and begins to alternate between HIGH and LOW starting at state 2. At the final state of currentState (state 18 in this code) the SCK stays at LOW. The SS signal is designed to output a HIGH value at the first and last state (state0 and state18 respectively in the code). Bytechoice is only incremented when currentState hits the final state at state18. At each count of Bytechoice 4 bits of the Hexadecimal number corresponding to one of the displays is sent just like in the Serial TTL communication method. As with the previous method, several reset signals should be sent before any data is sent. After this, Bytechoice will start at the states that send Hexadecimal values instead of the first count (counts 5-8 in the code). The Data input in this entity is the same as the one in the BoardDisplay so the output will be identical to the output on the board's displays. The Sparkfun display has a lookup table built in the will convert the numbers from 16bit binary into a 4 bit Hexadecimal value.

The entire code for the SPI_display.vhd file is included below:------------------------------------------------------------------------------------Code by: Joseph Crandall, Zachary Rauen--Date: 10/30/14--Last Modified: 11/2/14----Description: This takes in 16 bit data and displays them on an external display-- using GPIO and SPI communication.----Version: 1.1----------------------------------------------------------------------------------

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity SPI_display isGeneric (constant BoardClockSpeed : integer := 100000000; constant SCKSpeed : integer := 250000);

Port ( BoardClock : in STD_LOGIC; Data : in STD_LOGIC_VECTOR (15 downto 0); SCK : out STD_LOGIC; SS : out STD_LOGIC; MOSI : out STD_LOGIC );end SPI_display;

architecture Behavioral of SPI_display is

signal clkMax : integer := (BoardClockSpeed/SCKSpeed)-1;signal clkCnt : integer range 0 to clkMax;signal StateClock : std_logic :='0';type state_type is (state0,state1,state2,state3,state4,state5,state6,state7,state8,state9,state10,state11,state12,state13,state14,state15,state16,state17,state18);signal currentState : state_type :=state0;signal nextState : state_type;signal dataSection : std_logic_vector(7 downto 0);signal byteChoice: integer :=0;signal byteMax: integer :=8;begin

ClkEnable : process(BoardClock)beginif rising_edge(BoardClock) then if clkCnt = clkMax then StateClock <= '1'; clkCnt <= 0; else clkCnt<=clkCnt+1; StateClock <= '0'; end if;end if;end process ClkEnable;

StateChange: process (BoardClock,StateClock)beginif (rising_edge(BoardClock) and StateClock='1') then if currentState = state18 then if byteChoice = byteMax then byteChoice <= byteChoice-3; else byteChoice<=byteChoice+1; end if;end if; currentState <= nextState;end if;

end process StateChange;

States: process(currentState)begincase currentState is when state0=> SCK<='0'; SS<='1'; MOSI<='Z'; nextState<=state1; when state1=> SCK<='0'; SS<='0'; MOSI<=dataSection(7);

nextState<=state2; when state2=> SCK<='1'; SS<='0'; MOSI<=dataSection(7); nextState<=state3; when state3=> SCK<='0'; SS<='0'; MOSI<=dataSection(6); nextState<=state4; when state4=> SCK<='1'; SS<='0'; MOSI<=dataSection(6); nextState<=state5; when state5=> SCK<='0'; SS<='0'; MOSI<=dataSection(5); nextState<=state6; when state6=> SCK<='1'; SS<='0'; MOSI<=dataSection(5); nextState<=state7; when state7=> SCK<='0'; SS<='0'; MOSI<=dataSection(4); nextState<=state8; when state8=> SCK<='1'; SS<='0'; MOSI<=dataSection(4); nextState<=state9; when state9=> SCK<='0'; SS<='0'; MOSI<=dataSection(3); nextState<=state10; when state10=> SCK<='1'; SS<='0'; MOSI<=dataSection(3); nextState<=state11; when state11=> SCK<='0'; SS<='0'; MOSI<=dataSection(2); nextState<=state12; when state12=> SCK<='1'; SS<='0'; MOSI<=dataSection(2); nextState<=state13; when state13=> SCK<='0'; SS<='0'; MOSI<=dataSection(1); nextState<=state14; when state14=>

SCK<='1'; SS<='0'; MOSI<=dataSection(1); nextState<=state15; when state15=> SCK<='0'; SS<='0'; MOSI<=dataSection(0); nextState<=state16; when state16=> SCK<='1'; SS<='0'; MOSI<=dataSection(0); nextState<=state17; when state17=> SCK<='0'; SS<='0'; MOSI<=datasection(0); nextState<=state18; when state18=> SCK<='0'; SS<='1'; MOSI<='Z'; nextState<=state1;end case;

end process States;

ByteSelection: process(byteChoice)begincase byteChoice is when 0 => dataSection<=x"76"; when 1 => dataSection<=x"76"; when 2 => dataSection<=x"76"; when 3 => dataSection<=x"76"; when 4 => dataSection<=x"76"; when 5 => dataSection <=x"0" & Data(15 downto 12); when 6 => dataSection <=x"0" & Data(11 downto 8); when 7 => dataSection <=x"0" & Data(7 downto 4); when 8 => dataSection <=x"0" & Data(3 downto 0); when others => dataSection <="11111111";end case;end process ByteSelection;

end Behavioral;

Button Inputs: The final part of our design is the input buttons that allow the user to control the system. Three buttons need to be implemented into our design. BTNC needs to be programmed as a Reset button. This button needs to asynchronously start the sequence back at the first value (0000 for this project) once the button is released after a 1 second delay. BTNL needs to be programmed to toggle as a Reverse button that changes the direction of the sequence once it is pressed and then back to the original direction if it is pressed again. BTNR needs to be programmed to toggle as an Enabler button that will make the system stop counting when pressed once, and then resume counting if it is toggled back on.

Reset: We can alter the behavior of the displayCnt clock enabler to easily implement the function of the reset button into our design. The enabler can be designed to only count up when Reset is 0. If Reset is ever equal to 1 then the clkDisplayCnt will reset. This allows the sequence to restart only after a whole clock cycle has passed by when the button is released. An example of this implementation is given below:

DisplaySpeed: process(ClockState)beginif rising_edge(ClockState) thenif Reset <= '0' then

if clkCnt = dispEnableMax then StateEnable <= '1'; clkCnt <= 0; else clkCnt<=clkCnt+1; StateEnable <= '0'; end if;

elseclkCnt<=0;end if;end if;end process DisplaySpeed;

Also, if Reset is HIGH displayCnt should also be set back to 0 so the sequence will restart from the beginning once the system starts counting again.

Reverse: This button is fairly straightforward to program into our design. If the Reverse signal is low (system is counting forward) then you set the displayCnt to increment up by 1 or reset to 0 if it is at the final number in the sequence (NumofSequences in our design). If the Reverse signal is high (system is counting backwards) then you set the displayCnt to increment down by 1 or reset to the maximum NumofSequences if displayCnt is valued at 0. An example of this design is provided below:count: process(ClockState,StateEnable,Enabler,Reverse,Reset)begin if Reset='1' then displayCnt <= 0; else if Enabler = '1' then if rising_edge(ClockState) AND StateEnable = '1' then if Reverse = '0' then if displayCnt = NumOfSequences then displayCnt <= 0; else displayCnt <= displayCnt + 1; end if; else if displayCnt = 0 then displayCnt <= NumOfSequences; else displayCnt <= displayCnt - 1; end if; end if; end if; end if; end if;MemAddress<=displayCnt;

end process count;

Enabler: We can easily implement a system enabler by only allowing our displayCnt to increment when the Enabler signal is equal to 1. This will cause the output of the system to remain constant and will not

change the value being displayed until the button is pressed again. This can be done by putting the code in the above example in an if statement that will only run if the Enabler signal output is HIGH.

Constraints: The constraints file is based off the master constraints file for the Nexys 4 board. This file is straightforward; the only sections have to be inputs and outputs of the top level entity. The only deviation from the standard setup of the constraints file is that the cathode output was setup in reverse. This was done to make the designing of the cathodes in the code easier to make.

E. Module and Specifications Testing 1. Modular testing

The modular testing of the system was done by using visual confirmation on the board. This is much simpler than rewriting a test bench for each individual piece. The first task was to be sure the clock enable for the sequence was running at 1Hz. This was done by connecting the enable directly to an LED on the board, not one of the seven segments. The same philosophy was applied to the counters of the design. Each bit was assigned to the LEDs to see if the correct binary number would show, which it did. After having that work, the controller was designed fully without any sort of button inputs just to see if the sequences would display. Upon having all the sequences display properly the buttons were added directly to test their abilities. The last step, after having working direct buttons, was to add the debounce/toggle modules to all three buttons.

The serial TTL communications block and the SPI communications block are each designed and tested separately. This occurs before they are added to the overall system in order to avoid any unintentional errors. For the TTL communications block, the design was simulated in order to check the functionality of the state machine and the RX terminal. This was confirmed in ChipScope to be sure there were no errors going from simulation to implementation. The SPI was tested in a similar manner except the simulation and ChipScope were aimed at seeing the correct values for the three ports. This is because the functionality of the state machines was already established via the TTL block. The proper functionality can be confirmed by observing the changes in RX for TTL, MOSI, SS, SCK for SPI, in accordance with the data and the byte choice.

2. Overall TestingThe overall testing of the design is done, not only using visual confirmation upon programming

the design onto the board, but also using simulation and the ChipScope Logic Analyzer. There are a few key things that must be checked when testing the design. For this specific design, the seven segment displays must show the sequence at a rate of 1Hz while the three button inputs must affect the outputs the way they were specified to; one must reset, another will enable or disable the sequence while the other changes which direction it goes through the sequence.

When using these different forms of testing the design it is not feasible to use the standard timing of the design. This is due to the nature of the testing. In simulation it takes a long time to simulate enough of the system to be able to view its function and therefore the system is sped up in

order to view its function. The same concept occurs for ChipScope however the reason is different. The analyzer can only accept so many samples before it stops so by the time the sampling has finished the system will not have changed.

a) SimulationThe simulation requires a testbench which is shown in the appendix. This testbench shows all

the different ways in which the overall system needs to be tested including having the three different buttons used. The results of the testing are shown below. For the simulation, the following are shown, in order, on the waveform: The onboard clock, the clock enable pulse for the refresh rate, the clock enable pulse for the sequence selection, the reset button, the button that determines which way the sequence goes, the enable button, the current count for the anode selection, the current count for the sequence selection, the display on the cathode, the full anode selection.

Figure 1: This waveform shows the toggle pulses for the reverse button.This figure has two pieces. In the first it can be seen that the sequence choice, labelled as

Sequence on the waveform is initially counting up until the reverse button is pressed as shown on the waveform. After this button is pressed, due to its toggling nature affects the system upon the next pulse of the enabler for the sequence count shown at the cursor. At the time of the cursor the sequence count goes from 10 to 1 which means it did successfully reverse the direction of the count. The second piece of the figure demonstrates that the button can reverse the direction again back to its original direction. This occurs on the next enable for the sequence after the reverse button again shown by the cursor.

Figure 2: This shows the reset occurs while held then waits before restarting the count.Shown in this diagram, the sequence is reset to 0 while it’s held (after debouncing) then waits a

full cycle, which in real time would be 1 second, before starting to count again. This is exactly to specification.

Figure 3: Two enable pulses to show disable and re-enable.This three piece figure shows the enable button’s functionality. In the first piece it is shown that

the first pulse occurs. The second piece confirms that this pulse disabled the counting ability of the system because the Sequence select stays at 1. Upon the detection of another pulse the system re-enables and starts counting again as shown in the final section of the figure.

Figure 4: This figure shows the combination of the reset and enable buttons.When the enable button is pressed early on in the first piece of the figure the system stops

counting like it should. After this the reset is then pressed to be sure it initializes the system to the first value of the system and wait there until it should count again. When the system is enabled this would be a wait of one second. However, as shown here, the system is disabled and therefore shows the first value indefinitely.

Figure 5: Simulation of TTL and SPI

It can be shown in the first section of the simulation that the TTL communications work as designed. Looking along the RX signal at the time stamp, the start bit of ‘0’ is seen. After that, the logic vector for “0e” is output in reverse order making “01110000.” Around 7.55us it is seen that the RX goes back to its resting ‘1’ as the stop bit indicating that the data is done being sent.The second section of the figure shows the SPI outputs of SCK, SS and MOSI. The MOSI works similar to RX except it sends in forward order with high impedance as start and stop bits. Checking at the timestamp on the figure, it should start sending “05” in forward order, including the high impedance this should be “Z00000101Z.” All the logic values should be repeated to make a total of 2 times. For the stop impedance, the bit directly preceding it is unused and therefore its value does not to be checked.

b) ChipScopeIn the following figures for the ChipScope waveforms the waveforms are as follows: The enable

button, the reset button, the reverse direction button, the clock enable for the refresh rate, the clock enable for the sequence counting, the current sequence, the current 7 segment choice, the cathode, the anode.

Figure 6: The demonstration of the reset capabilities in ChipScope.As shown in this image, the reset makes the current choice for the sequence initialize to first

value pointed at by the value 0. The system is also showing here that it will wait a full count shown by DispEnable before starting to count again.

Figure 7: This figure shows both capabilities of the reverse button.In the first section of the figure, the sequence is shown to be counting up with a maximum value

of 8 as it rolls over to 0 then counts up to 1. This is when the reverse button is hit. This causes the system to start showing the sequence in reverse which is shown in the end of the first section and beginning of the second. In the first section the 1 quickly becomes a 0 and then rolls back over to an 8. In the second section this goes from 8 to 7 then to 6 when the button is hit again, demonstrating that it can successfully switch directions both ways by having it start showing it in the forward direction once more. This is represented by counting up to 7 then 8 at the end of the second section.

Figure 8: The final figure in the testing set showing the enabler button on ChipScope.Contained within the figure is the proof of the functionality of the enable button. In the first

section of the figure the system is clearly enabled because it is currently counting through the sequence, but when the enable button is pressed the system disabled and no longer counts through the sequence which is what is desired. The second section shows the enable button being pressed while the system is disabled as shown by the lack of counting before the trigger. This then begins to count through the sequence as shown at the end of the second section traversing from 2 to 3 and onto 4.

Figure 9: Chipscope of the serial TTL communications.

In the figure above, the middle signal represents the current data being sent out by the sequence controller. The last signal is the byte choice which dictates which byte is currently being sent out. The minimum value is 1 but choices 1 through 4 were the initial bytes sent out to the external display in order to setup and clear the device. The maximum value of the signal is 8 which represents the least significant hex of the data and 5 represents the most significant hex of the data. The first signal is the RX terminal consistent with serial TTL communication. To confirm, at timestamp 215 which is marked on the figure it can be observed that the start bit is used quickly followed by the corresponding data for sending an ‘E.’ This byte would be “00001110” but sent from the LSB to the MSB. As seen after the timestamp, the RX stays at a ‘0’ then goes to a ‘1’ for three clock cycles then reverts to ‘0’ for the last four bits until it hits a ‘1’ signifying the stop bit. This confirms proper workings of the TTL communications.

Figure 10: ChipScope analysis of SPI communications

In the above figure the signals are as follows: MOSI, SCK, SS, Data, Byte Choice. Here the byte choice represents the same things as in TTL and have the same configuration where 8 is the LSH and 5 is the MSH of the sequence. In order to confirm the proper function of the SPI it can be observed at the timestamp marked on the figure, around 370. At this time the SS is ‘1’ which signifies the start/stop of data being sent. From this point on to the next time that the SS goes to ‘1’ the SCK oscillates like a clock from ‘0’ to ‘1’ and back with a fifty percent duty cycle. The MOSI is very similar to RX from TTL but it actually send from MSB to LSB of the hex unlike RX. According to the data and byte choice, the MOSI should send out a D which in byte form is represented as “00001101.” This is confirmed when observing the MOSI as it stays at ‘0’ for the first 8 state changes then goes to a ‘1’ for two then quickly back to ‘0.’ Due to the way it was designed, the MOSI stays at a ‘1’ longer than just one state for the last bit but this does not matter because the SS is ‘1’ and the SCK is ‘0.’ This shows proper functionality in the SPI block.

F. Results and Analysis This design meets all the given specifications to the best of our knowledge and ability. The

system has an effective clock for the sequence running at 1 Hz. Specified in the outline, the design outputs the desired sequence in hex on the first four seven segment displays on the board and repeats when the last value is reached. The center button asynchronously resets the system to its initial value. Then after a one second delay it will begin counting as long as the system is enabled. The left button toggle the direction that the system displays the sequence. The system also starts in the forward mode. The other button used in the design enables and disables, as a toggle, the sequencer. All the buttons are debounced or toggled and the design uses one Xilinx IP for the ROM. The design can make successful communication through the GPIO port to the external seven-segment via both SPI and TTL communications. The testbench was written successfully and used in the ISim simulator for both modular and top level design. The overall design has enough generic statements to make the code easier to use later on. Lastly, the ChipScope logic analyzer was used to test the functionality of the system. Overall this design is easy to use and reuse while still meeting all the design specifications.

References1. Sam Bobrowicz. Digilent 2011. Button Debouncer.2. Abul Khondker. Lecture Presentations 10/2014. TTL & SPI Communications.

3. SparkFun Electronics. SparkFun Electronics 2010. Serial 7 Segment Display Manual.4. Digilent. Digilent 2013. Nexys4 FPGA Board Reference Manual.