Your Partner Throughout the Product Life Cycle - IEEEsites.ieee.org/ocs-cpmt/files/2013/06/Solder-Bump-vs.-Copper...Your Partner Throughout the Product Life Cycle ... o FMEA / FTA

© 2004 - 2007© 2004 - 20109000 Virginia Manor Rd Ste 290, Beltsville MD 20705 | 301-474-0607 | www.dfrsolutions.com© 2004 – 2010

Your Partner Throughout the Product Life Cycle

© 2004 - 2007© 2004 - 20109000 Virginia Manor Rd Ste 290, Beltsville MD 20705 | 301-474-0607 | www.dfrsolutions.com

Who is DfR Solutions?

The Industry Leader in Quality-Reliability-

Durability of Electronics

50 Fastest Growing Companies in the Electronics Industry

- Inc Magazine

2012 Global Technology Award Winner

Best Design Verification Tool- Printed Circuit Design


10 Years of Providing Solutions to the Electronics Marketplace

o DfR / DfM / DfT / DfS….. DfX

o Finite Element / Fluid Dynamics

o Physics of Failure Modeling

o FMEA / FTA

o 3rd Party Design Review

o Failure Analysis

o Root Cause Investigations

o Forensic Engineering

o Circuit Analysis

o Connector/Wiring Selection

o Analog/Power Design

o Material Characterization

o PCB / PCBA Onsite Audits

o Pottings and Coatings

o Software Risk Mitigation

End-to-End Quality and

Reliability Expertise


o Identified current state of technology and potential risks

o Difficulty in manufacturing

o Limited supply of reliability data

o Recommended four condition testing scheme for qualification

Technology Risk Evaluation: GaN FETs


o Performed comprehensive benchmarking of customer solution and market competitors

o Captured case temperature rise and efficiency under multiple voltages, power loads, and ambient temperatures

o This level of assessment was not previously performed; provided key insight into deratingrecommendations and margining

Market Benchmarking: SOC Power Conversion Devices


o Component manufacturer pushing the

limits to increase market share

o Driving RF CMOS transistors beyond

foundry’s specification

o New packaging technologies (copper

pillar, copper wirebond, low Tg underfill)

o Comprehensive assessment

o Initial transistor life prediction

o Finite modeling for prediction of 1st

and 2nd level lifetime

o Guidance on qualification plan

Design Review (Physics of Failure): Power Amplifier


Produces a

Failure Rate

EM

HCI

NBTI

TDDB

EM

HCI

NBTI

TDDB

EM

HCI

NBTI

TDDB

Acceleration Factors

Analysis of

Functional

Groups

Functional Group A Functional Group B Functional Group i

Simulated Device

Deconstruction

Device

Properties

Manufacturer

Testing

Functional Group A Functional Group B Functional Group i

Device

Accelerated

Failure Rate

IC Lifetime Prediction Methodology

o Models the simultaneous

degradation behaviors of

multiple failure mechanisms on

integrated circuit devices

o Devised from published research

literature, technological

publications, and accepted

degradation models from:

o NASA\JPL

o University of Maryland

o Semiconductor Reliability

Community


o Turnkey solution for application note development

o Design recommendations (stencil, bond pad, solder mask)

o Process optimization (reflow, wave, rework)

o Created defect identification guide

o Cause of misalignment/voiding

o Images of starved, bulbous solder joints

o Troubleshooting guide

o Qualified to JEDEC and AEC

o Range of environmental test conditions

Customer Management: Application Notes


Testing: Board Level Reliability (BLR)

Test Environments

o Temperature

o Temperature Cycling

o Temperature/Humidity

o Vibration

o Mechanical Shock

o Drop

o Bending

o Pull/Shear

o Combined Environment (Vibration + Temperature)

Test Methods

o JESD22 (A and B)

o AEC Q100

o IPC 97XX

Failure Analysis

o Decapsulation (gold and copper wire)

o Cross-Sectioning

o Optical and Electron Microscopy


Simulation: Modeling Warpage and BLR

o asdfasdf


Results: Over 1000 Satisfied Customers

© 2004 - 2007© 2004 - 20109000 Virginia Manor Rd Ste 290, Beltsville MD 20705 | 301-474-0607 | www.dfrsolutions.com© 2004 – 2010

Flip Chip Reliability Issues

Solder Bump vs. Copper Pillar


Flip Chip: Growing, but Not Dominant

Interesting Fact: Did you know there is,

practically, only one manufacturer of

wire bond equipment?


…but is Evolving

Note: Yole forecasts can be inaccurate


Underfill

Soldermask

Copper Pad

Substrate

Solder

Silicon

ELK Active layer

USG protective Layer

Al Pad Pad Passivation

PI/PBO Passivation

UBM

Flip Chip SnAg Bump


Underfill

Soldermask

Solder

Silicon

ELK Active layer

USG protective Layer

Al Pad Pad Passivation

PI/PBO Passivation

UBM

Flip Chip Copper Pillar

Copper Pad

Substrate


o Copper pillar was first patented by IBM in 2001

o Metal post solder chip connection (MPS-C2)

o In 2005, copper pillar interconnects placed in RF

power amplifiers and front-end modules

o Improved electrical stability and thermal performance

o Elimination of through-GaAs vias, wafer thinning, and

backside metallization

o Intel uses a combination copper pillar/SnPb joint for its

65nm Yonah and Pressler processors (2006)

Copper Pillar History


o The benefits listed by Intel

o Improved electromigrationresistance

o Improved thermal conductivity

o Simplified underbumpmetallization

o Higher I/O density

o Many believe the migration to copper pillar allowed Intel to avoid the low-Tg underfill fiasco

o These devices maintained high Tg underfill

o Note, no mention of improved thermal cycling performance

Copper Pillar History (cont.)

105 micron diameter pillar


o One Word:

Smaller Pitch

o Solder bumps are

problematic below

125 micron pitch

o Challenging to manufacture

and assemble

o Drivers for smaller pitch

o Needed for latest process nodes (28nm and below)

o Allows for smaller devices (demand of mobile OEMs)

o Reduces # of substrate layers (lower cost)

Why Copper Pillar?

Renesas, Solid State Technology, May 2012

SPIL, Cu Pillar webpage, May 2014


o Flip Chip interconnections require a fine balancing act

between die, interconnect, underfill,

substrate/leadframe, and lid to avoid the ‘SEVEN’

Flip Chip: A Balancing Act

o Low-K Dielectric Cracking

o During chip attach – White Bump

o During underfill

o Flip chip bump reliability

o Solder fatigue of C4 SnAg bump

o Temp cycling

o Solder joint reliability

o Solder fatigue of 2nd level connection

o Temp cycling

o Warpageo Coplanarity of the package

o Measured at (-55)°C and 260°C

o Die backside stresso During chip attach

o Die cracking

o Bond line thicknesso TIM thickness at various temps

o Affects θjc (thermal resistance: Junction to case)

o Electromigration


o Is Copper Pillar more/less reliable than Solder Bump?

o Answer: Depends!

o Why?: Multiple flavors of flip chip devices and 1st level

interconnections

Solder Bump vs. Copper Pillar


PCB

BGA ballPads

Substrate

Die Underfill

Flavors of Flip Chip: Bare Die with Underfill


PCB

BGA ballPads

Substrate

Lid Adhesive Lid Lid FootTIMDie UnderfillStreet

Flavors of Flip Chip: Lidded


PCB

BGA ballPads

Substrate

MoldDie UnderfillStreet

Flavors of Flip Chip: Exposed Die + Molded + UF


PCB

BGA ballPads

Substrate

MoldDieStreet

Flavors of Flip Chip: Exposed Die + Molded


PCB

BGA ballPads

Substrate

MoldDieStreet

Flavors of Flip Chip: Overmolded


o sdf

Which Copper Pillar?


o Intel (above), Amkor (top

right), and ASE (bottom right)

Which Copper Pillar (cont.)

105 micron diameter pillar


o Clear differences in regards to

o Pillar dimensions (height and diameter)

o Pillar shape (square vs. oval vs. round)

o Pillar wall (tapered vs. straight)

o Ratio of pillar height to solder thickness

o Ratio of pillar diameter to UBM diameter

o Ratio of pillar diameter to bond pad diameter

o Presence/absence of compliance layer (polyimide)

o These differences complicate an attempt to compare solder bump to copper pillar (or even copper pillars to each other)

Which Copper Pillar (cont.)


o Standard reflow process (solder paste)

o Modified reflow process (flux dip)

o Thermo-compression bondingo Increasingly the dominant assembly process

Which Assembly Process?


o If the pitch gets fine enough, process moves to thermocompression bonding with non-conductive paste

o Typically below 60 micron pitch

o Actual thermocompression takes only 2 to 3 seconds (similar to wirebonding!)

o However, this results in a change in material properties of the underfill

o The non-conductive paste (NCP) becomes the underfill

o Typically, different material properties than standard underfill(lower Tg, lower modulus)

o Underfill properties will tend to dominate thermo-mechanical fatigue performance

Thermocompression Bonding


o At similar dimensions, copper pillar outperforms solder bump in regards to electromigration (as much as 3X increase in lifetime1)

o Higher electrical and thermal conductivities reduce current density and temperature (primary drivers of electromigration)o Current crowding in solder bumps is highest at the entrance of the

metal trace to the bump2)

Electromigration (EM) Reliability

1 SPIL, Cu Pillar and BOT Flip Chip, 2014

2 Y Wang, Reliability of Cu Pillar Bumps for Flip Chip Packages


Amkor EM Test Results (A. Syed, EPTC 2010)


o However, the switch from solder bumps to copper pillar

will not result in similar dimensions

o Solder bump: 80 to 100 micron diameter

o Copper pillar: 25 to 60 micron diameter

o The ratio of interconnect (bump or pillar) diameter to

UBM diameter will likely decrease to reduce stress on

low-K dielectric

o Use of bump on trace (BOT) could also introduce areas

of elevated current density

Electromigration (EM) Reliability (cont.)


o There is surprisingly little good test data on the relative

performance of solder bump vs. copper pillar

o Comparisons have primarily been through simulation

o Regardless of the interconnect technology (bump vs.

pillar), underfill properties will dominate thermal

cycling performance

o If the underfill needs to change, to NCP / NCF /

molded underfill, this will tend to have a far greater

effect than interconnect parameters

Thermal Cycling Reliability


o As a general statement, thermal cycling performance

would be expected to be better

o Copper pillars can offer a larger standoff for a given

pitch (more compliance in the interconnect)

o Larger ratio of copper to solder increases amount of

intermetallic within the solder volume

o Improves creep resistance (this why SAC405 is better than

SAC305 which is better than SAC205, etc.)

Thermal Cycling Reliability (cont.)


Intermetallics in Copper Pillar Interconnections

L. Kwang and T.K. Hwee, Flip Chip on Leadframe Assembly Using copper pillar bump technology

J. Vardaman, Emerging Trends in Flip chip


o Different papers have indicated different trends

o Some claim lower stress (improved performance)

o Some claim higher inelastic strain energy density (worse

performance)

Thermal Cycling Reliability (Simulations)

Y Wang, Reliability of Cu Pillar Bumps for Flip Chip Packages

M. Hseih, IEEE IMPACT, 2012


Change in Underfill (Decrease in Tg)

o Near the Tg, CTE changes more rapidly than modulus

o Large increase in the expansion with negligible change in the modulus can result in significant solder tensile stresses

0.01

0.10

1.00

10.00

35 45 55 65 75 85 95 105

Temperature (oC)

Sto

rag

e M

od

ulu

s (

MP

a)

0

20

40

60

80

100

120

140

CT

E (p

pm

/ oC)

Storage Modulus

CTE


Rise in Tensile Stress

2211

12

11

EAEA

TF

High stresses generated in

the solder due to

CTE increase before

modulus decrease


o As mean tensile stress increases, fatigue lifetime drops due

to diminished recovery of accumulated damage

o Example: stress-controlled fatigue at 42 MPa amplitude

o smean = 0 MPa: lifetimes of 15K to 35K cycles

o smean = 7 MPa: lifetimes of 100 to 1K cycles

o For mean compressive stress or strain, recovery processes

dominate; fatigue life is effectively infinite

o At comparable stress amplitudes, lifetime in tension is up to

100X less than that in shear

Effect of Mean Tensile Stress


End Result

Temperature transitions through the critical temperature range decreases the

life by an order of magnitude

100

100,000

10,000

1,000

1,000,000

Cycles to

Failure

Peak Temperature (oC)Tg

25C / Peak Temp (1x)

25C / Peak Temp (1x)

Tg 3C (10x)


o Consistency of solder between the copper pillar and

bond pad also becomes critical

o Wetting along the sides of the copper pillar can result

in very small bondline

o Insufficient coplanarity of the copper pillar can also

result in joints with non-optimum geometry

o Copper plating process can result in pillar heights varying by

as much as 25% (40 to 50 microns)



o Discussions on reliability can be complicated by shift in

failure site

o Some studies have identified cracking in low-k

dielectric after temperature cycling / thermal shock

o The singular environmental

may not detect these

type of failure modes


R. Katkar et. al., Reliability of Cu Pillar on Substrate, 2011


o ELK cracking is often viewed as the biggest risk in

regards to transition to copper pillar

o Primarily occurs during flip chip bonding process

o Some observation of cracking during underfill cure (during

cool down)

o Key issues are to identify mitigation techniques

ELK Cracking


o Tall copper pillars help decouple the interaction between the copper pillar and the low-K/ultra-low K/extreme low-K (ELK) dielectric

o However, tall copper pillar is a tradeoff. Requires more plating time, decreasing through-put

o Larger ELK thickness

o Larger diameter

o Small attach at top or bottom

o Use of polyimide

ELK Cracking Mitigation

M.C. Hsieh, IEEE IMPACT, 2012


o Comparison of 80um (small) vs. 100um (large)

diameter copper pillar

o Copper pillar height of 50um and solder height of 20um

ELK Crack Migitation (Large Diameter)

ILD: Interlayer Dielectric

M: Metal layer

IMD:

Y Wang, Reliability of Cu Pillar Bumps for Flip Chip Packages


o Can increase compliance of the

overall structure

o Used for bump on trace (BOT)

geometry

o SPIL recommends die bond pad ratio

to trace width ratio not exceed 2X

ELK Crack Migitation (Small Attach)


o The PI layer is softer:

o Reduces stress

o Pad-Bump interface diameter is reduced to the PI passivation opening

o The copper pillar height remains the same

o The distance between the copper pillar corner to the pad passivation is increased

o Adding the PI layer:

o Either at the die vendor or before bumping

PI Passivation

Pad-Bump Interface Pad Passivation

Al Pad

Active Layers


o Copper pillar is increasing in popularity

o As each OSAT (and potentially foundry) has different

technology and process, variations to improve

reliability can be challenging

o Especially considering die constraints

o Do not always rely on test!

o Test conditions may not accurately convey to field

environments

Conclusion


Documents

Your Partner Throughout the Product Life Cycle - IEEEsites.ieee.org/ocs-cpmt/files/2013/06/Solder-Bump-vs.-Copper...Your Partner Throughout the Product Life Cycle ... o FMEA / FTA