Upload
others
View
4
Download
0
Embed Size (px)
Citation preview
© 2000 Altera Corporation
Download from http://www.pld.com.cn
Designing with Quartus
You can download more files fromhttp://www.pld.com.cn or www.fpga.com.cn
© 2000 Altera Corporation
Download from http://www.pld.com.cn
Quartus Development System Feature Overview
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Quartus Development System
Quartus Development System features:– Fully integrated design entry, processing, and verification tools:
• Multiple design entry methods• Logic synthesis• Place & route• Simulation• Timing analysis• Device programming
– NativeLink– Revision Control Interface– Intellectual Property (IP) Support– SignalTap– Extensive On-Line Help
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
More Features
Incremental RecompilationInternet-enabled technical supportSupports multiple platforms1
– Quartus runs on Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 workstations
Extensive on-line helpNetwork licensing supported on both Windows-based PCs and Unix-based workstations
Note 1: Please refer to Quartus’ ReadMe file to determinewhich version of the Operating System is supported for each platform
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Quartus Operating Environment
Project Navigator Window
Messages Window
Status Window
© 2000 Altera Corporation
Download from http://www.pld.com.cn
QuartusDesign Methodology
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Design Specification
Design Compilation
Functional Verification
Timing Verification
Device Programming
In-System Verification
Design Modification
Design Entry
Command-LineMode:
Scripting
System Production
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Design Methodologies
Quartus supports three common design methodologies:– Top-down
• Create a top-level of the design first, and then break down the design into lower-level design blocks.
– Bottom-up• Begin by creating the lower-level design blocks first and then
stitch together the design at the top-level.– Middle-out
• Start in-between Top-down and Bottom-up design methodologies
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Design Entry
Multiple design entry methods– Quartus
• Block/Schematic Editor• Text Editor
– AHDL, VHDL, Verilog• Memory Editor
– Hex, Mif– Third party EDA tools
• EDIF• HDL• VQM
– Add flexibility and optimization to the design entry process by:• Mixing and matching design files• Using LPM and Megafunctions to accelerate design entry
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Design Entry Files
QuartusMemory Editor
QuartusText Editor
QuartusBlock Editor
Top-Level File
.bdf
.gdf
Top-level design files can be .bdf, .tdf, .vhd, .vhdl, .v, .vlg, .edif or .edf
.bsf .vhd
BlockFile
SymbolFile
TextFile
TextFile
.v
TextFile
Exemplar,Synopsys,Synplicity,etc...
VHDL
Schematic
Schematic.tdf
TextFile
AHDL
Verilog
.edf.edif
TextFile
.v, .vlg,.vhd, .vhdl,
vqm
MegaWizardManager
Generated within Quartus Imported from third-party EDA tools
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Resource Libraries
The following libraries are added to the project by default– LPM
• Library of Parameterized Modules ( LPMs )• Industry standard logic functions
– LPM_ADD_SUB, LPM_COUNTER, etc.– Others
• 7400 series logic functions (to provide support for older designs)
• Other legacy functions like 161mux, 8fadd, etc.– Primitives
• Basic logic building blocks
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Add User LibrariesMenu Bar: Project > General Setting...
Step 1: Select User LibrariesStep 2: Select Library pathStep 3: Click AddStep 4: Click OK
Adding User Libraries can also be done using Project Wizard. Refer to the section on Project Wizard for more information
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Text Design Entry
Available Features– Line numbering in the HDL text files– Preview of HDL templates– Syntax Coloring– When editing a text file, an asterisk (*) appears next to the
filename • After saving the file, the asterisk disappears
Enter text description– AHDL (.tdf)– VHDL (.vhd)– Verilog (.v)
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
HDL Templates
Menu Bar: Insert > Template… or click on the shortcut button
Select HDL language. Select Template section. Preview window display section
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Edit OptionsUpper Left-hand Corner of the Screen
Find Matching Delimiter
Increase Indent
Decrease Indent
Upper Left-hand Corner of the Screen
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Text Editor: Options
Menu Bar: Tools > Options...
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
AHDL
Altera Hardware Description LanguageHigh-level hardware behavior description languageUses Boolean equations, arithmetic operators, truth tables, conditional statements, etc.Can create AHDL Design File (.tdf) with the Quartus text editor or any standard text editor and compile it directly with QuartusText editor has AHDL templates and syntax coloring
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Verilog
1993 Verilog IEEE 1364 standard Hardware Description LanguageCan create Verilog design files with the Quartus text editor or any standard text editor and compile it directly with Quartus Text editor has Verilog templates and syntax coloringFeatures– Tasks– 2-D Arrays– Empty placeholder– State machine recognition– Verilog TestBench support
Learn more about Verilog in Altera VerilogCustomer Training Classes
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
VHDL
VHSIC Hardware Description Language1987 and 1993 IEEE 1074 standards supportedCan create VHDL design files (.vhd) with the Quartus text editor or any standard text editor and compile it directly with QuartusText editor has VHDL Templates and syntax coloringVHDL TestBench support
Learn more about VHDL in Altera VHDLCustomer Training Classes
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Block Diagram/Schematic File Editor
This is both a block diagram editor and a schematic file editor
Block diagram entry is mainly for top-down design methodologySchematic file entry is the traditional schematic design entryUser can enter blocks, primitives, LPMs, and megafunctions from Quartus-provided or user librariesProvides “smart” block connection and mapping
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Block Editor - Entry Process
Create new block design file– Draw block diagram or enter design components (symbols)– Enter port and parameter information– Connect components with connectors (wires, buses & conduits)– Add mapping properties to conduits, if needed
Save the design– The file extension is .bdf
Generate HDL/graphic file for the lower-level blocksCreate symbol or include file of the top-level block design
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Block Editor - Create New File
Open new file
Select Block/Schematic Document
Create a block/schematic fileMenu Bar: File > New > Block/Schematic document
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Block Editor - Enter Symbols
Click on the toolbar option “Insert Symbol”
OR
Double-click in block editor to insert symbols
Enter symbols from libraries - LPMs, primitives, others
Symbol libraries
Preview the Symbol
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Block Editor - Draw Block
Create block using the toolbar and enter ports
Right-click on the block. Select Properties from the pop-up menu. Enter port information.
Click on the toolbar option “Block” to draw a block diagram
Block A
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Block Editor - Make Connections
Wire
Bus
Wire (Single bit line)Bus (Multiple bits)
Conduit– Connects blocks to any other objects
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Block Editor - Check Conduit ConnectionsRight Mouse Click on the connector > Conduit Properties
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Block Editor - “Smart” Connections
Quartus has “smart” block connecting and mapping– Unnecessary to label conduits if the I/O names between different
blocks are the same– One conduit will connect all the common I/Os between the blocks
Mapper Connector
Block A Block B
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Block Editor - Conduit Properties
Map the block I/Os when the I/O names are different between the blocks1 First, label the connector
• Select connector right-click choose Properties enter Name
Block BConnectorAB
ConnectorAB
Enter Signal
Block A
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Mapper Properties
Double-click on the mapper
ConnectorAB Block B
2 Select the mapper and double-click on it to open the Mapper Properties dialog box
3 In the General tab, set the Mapper Type -Input, Output, Bidir
4 In the Mappings tab, set the I/O on block and connector signal
5 Click Add and hit OK
Block A
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Block Editor - Make Connections6 Enter mapper properties on both the blocks
7 Now, the I/Os are connected
Block A ConnectorAB Block B
IIIII
Mapper Annotation Box
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Block Editor - Save DesignSave the design file with .bdf extension
Design File Name
Block AConnectorAB Block B
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Block Editor - Generate Design FileCreate HDL or graphic design file for individual blocks
Select Create Design File from the menu
Block AConnectorAB
Block B
Right-click on the symbol to open the pop-up menu
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Block Editor - Generate Design FileChoose from the File Type and enter File Name
Select from AHDL, VHDL,Verilog or Graphic option
Block AConnectorAB
Block B
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Create Design File
module myblk(
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!in1, in2, out1, out2// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!input in1;input in2;output out1;output out2;// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
endmodule
These lines arenecessary for Quartus to update the source code
Quartus creates a design file that contains the port names that are specified in your block.
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Update Design File...Before After If you change the name
or number of I/Os in your block, Quartus can update the design file for you
Right mouse clickUpdate Design File...
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Updated Design File
Quartus updatedthe source filewith the additional pin, out3
module myblk(
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
in1, in2, out1, out2, out3// {{ALTERA_ARGS_END}} DO NOT REMOVE
THIS LINE!);// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input in1;input in2;output out1;output out2;output out3;// {{ALTERA_IO_END}} DO NOT REMOVE THIS
LINE!endmodule
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Block Editor - Designing Hierarchically?Menu Bar: Tools > Create Symbol for Current FileMenu Bar: Tools > Create Include File for Current File
Creates .bsf file
Creates .inc file
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Block Editor - OptionsMenu Bar: Tools > Options
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Memory Editor
Create or edit memory files in hex format (.hex) or memory initialization format (.mif)For Design Entry – If you have a memory block in your design (ex. RAM, ROM, or
Dual-port RAM), you can use the memory editor to create a memory initialization file to initialize your memory block
For Simulation– You can create an initialization file to initialize your memory
during simulation
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Memory Editor - Create New File
Create memory file Menu Bar: File > New > Other Files tab
Hex DocumentMif Document
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Memory Editor - Create New File
Create memory file– Enter Number of Words and Word Size
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Memory Editor - Create New File
Opens memory editor window with the required number of words and word size
WordsORCells
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Memory Editor - OptionsChanging some options of memory editor– View Select from available options
Cell Per Row
Show ASCII Equivalents
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Memory Editor - Options
Changing radix settings of memory editor– View Address/Memory Radix
Memory Radix
Address Radix
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Memory Editor - Edit Contents
Select the word and type in a value
OR
Select the word and right click to select an option from the pop-up menu
Create memory file– Edit contents of the memory file
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Memory Editor - Save File
Create memory file– Save the memory file as .hex or .mif file
.
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Memory Editor - Memory Size WizardNeed to Edit Memory Size Contents?
Quartus Provides the Memory Size Wizard– Edit Word Size– Edit Number of Words– Specify How to Handle Word Size Change
• Increasing Word Size – Pad Words– Combine Words
• Decreasing Word Size– Truncate Words From Left– Truncate Words From Right
.
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Memory Editor - Memory Size Wizard
1. Open Memory File
2. Select theMemory Size Wizard
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Memory Editor - Memory Size WizardDecreasing Memory Size
3a. How should Quartus handle excess bits?
- Truncate MSBs- Truncate LSBs- Split Words/Increase Memory Depth
16 bits
8 bits
To
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Memory Editor - Memory Size WizardIncreasing Memory Size
16 bits
32 bits
3b. How should Quartus pad words?
- Combine Words- Sign Extend (Signed)- Pad MSBs With Zeros (Unsigned)
To
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Memory Editor - Memory Size Wizard
4. Select New Memory Depth
4. Click on Finish
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
EDA Interfaces Introduction
Quartus can interface with industry-standard EDA tools that generate an EDIF 200 netlist file, a VHDL 1987 netlist file, VHDL 1993 netlist file, or a Verilog HDL netlist fileNativeLink interface provides truly seamless integration with third-party EDA software tools– Quartus and EDA tools pass information/commands in
background– Designers can complete entire designs without “leaving” their
tools
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Introduction to Quartus Design Flows
Quartus allows for three possible design flows :– Quartus Driven Flow:
• User launches other EDA tools from Quartus• No need to learn 3rd party EDA tool
– Vendor Driven Flow:• User runs Quartus in the background from the 3rd party EDA
tools– File Based Flow:
• Very little integration between Quartus and 3rd party EDA tools
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Quartus Driven Flow
– EDA tools launched from within Quartus
– Code level integration • Cross probing and error
location– Quartus automatically
generates the netlists or reads in the netlists based on the tool
– User doesn’t have to learn the setup and the flow
Synthesis Tool
TclCOM (C++,VBScript)
API
Cross Probe Error Locate
Quartus drives the third party EDA software
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Vendor Driven Flow
Third party EDA software drives Quartus
Synthesis Tool
TclCOM (C++,VBScript)
Cross Probe Error Locate
API
– Offers the tightest code-level integration between tools
– Quartus appears ‘Native’ in third party EDA software
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
NativeLink FeaturesMinimizes designer interaction with different EDA tools– Allows designers to complete their designs using as little as one tool
Cross-referencing– Nodes from place-and-route result can be traced back to HDL code
across from Quartus to a synthesis toolImproved Quality of Results (QoR)– Nativelink lets synthesis tools map directly into the fundamental
building block of an architecture Iterative Compile– Improves QoR from synthesis tools– Allows Quartus to pass routing delay information after place-and-
route back to the synthesis tools– Synthesis tools can then re-synthesize the design based on the
feedback
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
NativeLink
Quartus NativeLink interface is comprised of two components:– External Files: WYSIWYG (What You See Is What You Get)
ATOM netlist files (EDIF, Verilog, VHDL) cross reference files (ex. xrf), timing files (ex. sdo) etc.
– Application Programming Interface (API) Functions - a pre-defined interface
EDA PartnersEDA Partners
API
ExternalFiles
Quartus
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
WYSIWYG ATOM Primitives
A set of design primitives that support WYSIWYG compilationProvides direct control of how a design is technology mapped to a specific target deviceHelps synthesis vendors provide an optimal realization of a design for a device architectureWYSIWYG elements in the design are translated as directly as possible for fitting and routing purposes
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
WYSIWYG Compilation Flow
EDA Synthesis
Partner
EDA EDA Synthesis Synthesis
PartnerPartner
EDIFVerilogVHDL
NetlistExtraction
Database Builder
SynthesisPlace
& Route
QUARTUSDesign Input Files with
WYSIWYG Primitives
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Iterative Compilation Flow
SDFFile
Device Database &
Delay Annotator
PartialPlacement
FinalPlacement
Routing
COMPILER
Good Timing Estimation
Better Timing Estimation
Best Timing Estimation
QUARTUS
Area &Timing
ConstraintsSYNTHESIS
TOOLATOMNetlist
EDIFVHDLVerilog
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Synthesis Tools•Design Compiler•FPGA Express1
•FPGA Compiler•FPGA Compiler II•Altera Edition•General Version
•Leonardo Spectrum•Synplify
Simulation Tools•ModelSim•Verilog-XL
Timing Analyzers:•Motive•Primetime
Tools Supported by NativeLink
1
1
1
Note 1: These synthesis tools generate WYSIWYG ATOM netlists and support iterative compile capability
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Non-NativeLink Supported EDA Tools
Synthesis Tools– Design Architect– ViewDraw
Simulation Tools– VCS/VCSI– VSS– Speed Wave
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Quartus Driven FlowProject > EDA Tool Settings...
ATOM netlist is automatically generated whenyou choose a NativeLink EDA ToolThe correct data format is automatically chosen
Quartus DrivenFlow
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
EDA Driven Flow
Run Quartus in the background: Background Compile
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
File Based Flow: Non-NativeLink
If a non-NativeLink EDA Tool generates a VHDL, Verilog, EDIF file, then specify a .lmf for that file format
Can be EDIF, VHDL, or Verilog
Select a library mapping file (lmf)
Project > EDA Tool Settings... Select Custom
Select Settings...
© 2000 Altera Corporation
Download from http://www.pld.com.cn
Quartus Projects
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Project Definitions
Quartus Project:– A collection of related design files and libraries– Must have at least one designated top level entity– Targets a single device or can be partitioned into multiple devices– Stores project settings in Project Settings File (.PSF)
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Agenda
New Project Wizard– Quick way to create a new project– Easy way to import an existing MAX+PLUS II project
Project Menu– Edit existing project settings– Non-Wizard settings
Project Settings File (.PSF)Project Navigator
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Creating a New Project1. Invoke New Project Wizard
2. Select Working directory
3. Name of Project. Recommendation: Use top-level design entity
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Creating a New Project
4. Add design files
Notes:• All files in the project directory do not need to be added• Add top level file if file name and entity name are not the same
5. Add user library pathnames and files
- Graphic (.BDF, .GDF)
- AHDL
- VHDL
- Verilog
- EDIF
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Creating a New Project
• User Libraries (ex. MegaWizard functions)
• MegaCores/AMPP libraries
• Pre-compiled VHDL packages
5(cont.) Add user library pathnames and files
Browse to file and click on Add.
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Creating a New Project
6. Review results and click on Finish
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
New Project (Completed)
Project Name &Directory
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
MAX+PLUS II to Quartus
Converting MAX+PLUS II designs to Quartus:– Browse to project directory– Set top level file/entity– No need to add other files in directory– Add:
• Any files not located in same directory • Any user directories as libraries
Notes
- Any Graphic Design File (.GDF) from MAX+PLUS II that is edited within Quartus can only be saved as a Block Diagram File (.BDF) by Quartus
- Symbols with .GDF files may have to be updated
- The Assignment & Configuration File (.ACF) from MAX+PLUS II is not recognized by Quartus
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Project Menu
Edit the settings for an existing project– Adding/removing files or libraries
Non-Wizard project settings– HDL interface– Third Party EDA Flow– Timing Settings (not discussed)– Revision Control (not discussed)
Note:All Project settings except project name and top level entity default to the settings of the previously opened project
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Editing Project Settings
Existing project must first be opened to edit the settings
Open the Existing Project
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Editing Project Settings
To add/remove project files
Adding- Browse to file- Click Add
Removing- Select file from list- Click Remove
Access via the General Settings dialog box
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Editing Project Settings
To add/remove project libraries
Adding- Browse to directory- Click Add
Removing- Select library from list- Click Remove
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
VHDL Input Files
Select VHDL version
Enter Library names when directly compiling VHDL files with Quartus that contain user-created packages
If gate level VHDL netlist file is used, specify mapping file (discussed later)
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Verilog Input Files
If gate level Verilog netlistfile is used, specify mapping file (discussed later)
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Project Settings File (PSF)
Stores all project setting informationAutomatically generated by QuartusQuartus default file name is <project_name.psf>Can be manually edited inside Quartus
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Sample Project Settings File (PSF)DEFAULT_LOGIC_OPTIONS{
DUPLICATE_LOGIC_EXTRACTION = ON;AUTO_TURBO_BIT = ON;AUTO_OPEN_DRAIN_PINS = ON;AUTO_PARALLEL_EXPANDERS = ON;AUTO_OUTPUT_REGISTERS = OFF;AUTO_INPUT_REGISTERS = OFF;AUTO_DELAY_CHAINS = ON;AUTO_CASCADE_CHAINS = ON;AUTO_CARRY_CHAINS = ON;PARALLEL_EXPANDER_CHAIN_LENGTH = 16;CASCADE_CHAIN_LENGTH = 2;CARRY_CHAIN_LENGTH = 32;NOT_GATE_PUSH_BACK = ON;SLOW_SLEW_RATE = OFF;STATE_MACHINE_PROCESSING = AUTO;
}DEFAULT_TIMING_REQUIREMENTS{
IGNORE_REQUIREMENTS_FOR_FITTER = ON;CUT_OFF_IO_PIN_FEEDBACK = ON;CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;CUT_OFF_READ_DURING_WRITE_PATH = ON;
}PROJECT_INFO(test){}THIRD_PARTY_EDA_TOOLS(test){}
Default Logic Options (partial listing)
Timing Analysis Information
EDA Tool Information
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Project Navigator
Graphical display used to study project relationshipsActive in both Compilation and Simulation modesThree views– Hierarchies view– Files view– Design Units view
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Views of the Project Navigator
Hierarchy View– Displays Project Hierarchy after
project is analyzed– Can be used to make
assignments
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Views of the Project Navigator
Files View– Shows all files in the
project– All source files appear
under Design Files– Simulation files, include
files, etc., appear under Other Files
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Views of the Project Navigator
Design Unit view– Displays each design unit
• a design entity that can be used together with gates, registers, and megafunctions in a design file
– Displays type, e.g. AHDL entity– Details the File in which it is
instantiated
Design Unit
Associated Design File
© 2000 Altera Corporation
Download from: http://www.fpga.com.cn
Project Summary
Use Project Wizard to create new projectsUse Project Menu dialog boxes to– Edit existing project settings– Set up Third Party interface
Use Project Navigator to study file and entity relationships within the project