Yole 3DIC & TSV Interconnects July 2012 Sample[1]

© 2012

Copyrights © Yole Developpement SA. All rights reserved.

3DIC & TSV Interconnects

2012 Business Update

Infineon

Xilinx/Yole

Micron

Synopsys

Memory

Logic

© 2012 • 2

Copyrights © Yole Développement SA. All rights reserved.

Table of Contents

• Scope of the Report & Definitions ……..……. 5 – Objectives of the report

– What has changed?

– Scope of the report

• Executive Summary ………………..………… 11

• Recent key press headlines ………………… 25

• 3DIC & TSV Market Forecasts ……………… 35 – 2011 Capacities and Market Status

– 2010-2017 Market Forecasts

o 3DIC platform

o 2.5D platform

o 3D-WLCSP platform

• Infrastructure & Supply Chain for 3DI …….. 85 – Active Players & Geographic locations

– Respective market shares of main contract 3D TSV players

– Supply chain perspective

– Middle-end infrastructure evolution

• 3DIC Market Focus …………………..…... 100 – Wireless market

– Automotive market

– Medical market

• 3DIC Application Focus …….……….…… 115 – CMOS image sensors

– MEMS & sensor applications

– Power, Analog & RF applications

– Stacked memories (DRAM, Flash)

– HB-LED module

– Logic + memory SiP applications

– Logic 3D-SOC/SiP applications

• 3DIC technological challenges ……….. 145

• TSV IP Analysis ………………………….. 168

• Conclusion & Perspectives …….………… 180

• Appendix ………...…………….……….…… 188 – Yole Developpement company

presentation & services

© 2012 • 3


What’s new since “3DIC 2009” Report ?

• Even if “3DIC & TSV” is still an emerging and booming market, we now

have a clear picture of what is happening. 3 technological platforms are

involved in 3D chip integration and have been studied through this report

– 3DIC

– 3D-WLCSP

– 2.5D Interposer

• This is the first Yole’s report using our brand new top down approach

screening more than 80 electronic ICs (GPU, Accelerometer, FPGA,

Interposer IC, Baw Filter etc.) used in more than 90 end products, in 9

different markets

• This report also provides

– The full analysis of 3D market through 2010 – 2017 forecast given in wafers, units and $

– The bottom up approach with 2011 installed capacities, cross checked with top down

approach

– Supply chain analysis with key players

© 2012 • 4


FOWLP ‘Fan-in’ WLCSP 2.5D

Interposer 3D WLCSP

Flip Chip

• This report is focused on the 3 Mid-End technological platforms in which TSV is used as a

vertical interconnect: 3D-WLCSP, 2.5D Interposer and 3DIC

Technology scope of the report

ST Elpida

Xilinx

3D

FOWLP

Scope of the report

3DIC

© 2012 • 5


Scope of the report

Mid-end Process steps

RDL

Bumping Balling

Wafer Bonding

TSV

WL-Optics

WL-Capping

3D WLCSP

2.5D Interposer

Bumping

3DIC

Balling

WLCSP FO

WLP Embedded

IC Flip Chip

MEMS IC

Capping

IC

Sensor

Memory

Logic

Partially covered in the report

Main topic of this

brand new report !

© 2012 • 6

Copyrights © Yole Développement SA. All rights reserved. APTC Workshop – SEMICON China – 2011

3D integration, halfway between SoC and SiP

“All in One chip system

integration Euphoria”

3DIC / 3D-SOC will provide

at least two more decades

of semiconductor evolution

through higher Added Value

Systems and continued Cost

reduction

© 2012• 7


• Several slides show the most important news related

to 3DIC & TSV technology released betweend 2009

and today

• « key annoucement slides » have been integrated all

along this report to provide an up to date picture of

the market with embedded links to i-micronews

website !

What’s new since 2009 ? 2010 – 2012 key announcements about 3DIC & TSV

JEDEC Wide

IO Standard

IBM First 3DIC Chip sampled

Mar 2011

3D Product Announcement

by Renesas

Jan 2012

Dec 2011

Micron Hyper Memory Cube

Feb 2011

Xilinx FPGA

Oct 2010

TSMC reveals Si Interposer

plans

Jun 2010

© 2012 • 8


Yole’s Top Down Approach Methodology

• The top-down analysis derives the wafer forecasts from an analysis of the 3D products,

application by application, taking into account the penetration rate of the technology for

each product type, as well as their yields and die sizes

• This « 2012 3DIC & TSV Interconnects report » is the first one using Yole’s brand new top

down matrix in which more than 90 electronic end products are screened

• Inputs of this matrix are end product market data, outputs are packaging market forecasts in

wafers, units and dollars

2008 2009 2010 2011 2012 2013 2014 2015

TOT Thin-film IPD revenues 614 580 631 725 827 1 012 1 276 1 750

0

200

400

600

800

1 000

1 200

1 400

1 600

1 800

Sale

s (M

$)

Thin film IPD Market Forecast per Application Field (in M$)

Yole Developpement © June 2009

IPD market

In Munit

Techno

penetration %

Die sizes

(mm²)

Std. Product

Unit forecasts 3DIC ASP

$$$

Sources: iSuppli, IC Insights …

Wafer

Forecasts & 2011

processed wafers

3DIC

market

In $M

3DIC market

In B units

Manufacturing

Yield

by product

90 end-products screened in 9

different markets

80 electronic IC studied

© 2012 • 9


Packaging platforms studied through top down approach

• Each of studied device packaging possibilities are considered and modelled with a penetration rate

• Knowing IC forecast (in unit and wafer), advanced packaging forecast are extracted

• For this 3D report, 3 advanced packaging platforms have been considered: 3DIC, 3D-WLCSP and 2.5D

Interposer

Device type Mid-end Process Steps

AP Platforms Active Passive Wafer

Bonding TSV RDL Bumping Balling

3D IC X Optional X Optional Optional

3D WLCSP X X X X X

2.5D Interposers X X X Double Side

WLCSP X X X X

Embedded Die X X X X

FOWLP X X X X

Flip-Chip X Optional X

WLOptics X X

WLCapping X X X

MEMS IC

Capping

IC

Sensor

Memory

Logic

3DIC

3D-WLCSP

WLCSP

FO-WLP

WLOptics

2.5D Interposer

Embedded IC

Flip Chip BGA

WLCapping

© 2012 • 10


Global 3D TSV Semiconductor Market Value Comparison with total semiconductor value (M$)

• 3D Semiconductor market (including 3DIC, 2.5D Interposer & 3DWLCSP) will

represent 9% of the total semiconductor value in 2017

Yole Developpement © July 2012

© 2012 • 11


Global TSV Chip Wafer Forecast Breakdown by industry (12’’eq. Wafers)

• Logic 3D SoC/SiP (including interposer chips, APE, CPU, FPGA, wide IO memory

etc.) will be the biggest industry using 3D platforms in the next few years

-

2 000 000

4 000 000

6 000 000

8 000 000

10 000 000

2 010 2 011 2 012 2 013 2 014 2 015 2 016 2 017

3D Stacked NAND Flash - - - - - 8 877 20 130 318 072

3D Wide IO Memory - - - - 110 215 252 005 896 565 1 429 417

Logic 3D SiP / SoC - - 9 734 169 677 544 957 1 137 164 2 000 097 3 190 499

3D Stacked DRAM - 7 977 50 563 146 200 324 563 593 361 878 729 1 596 526

MEMS / Sensors 92 29 396 76 298 116 305 208 910 323 314 461 323 616 799

LED 4 395 8 759 18 890 45 188 91 101 159 569 232 887 237 715

RF, Power, Analog & Mixed signal 26 255 35 892 47 018 80 883 127 106 189 921 275 402 386 344

Imaging & Optoelectronics 387 126 503 821 635 468 787 345 996 423 1 240 691 1 492 479 1 801 534

Waf

er c

ou

nt

(12

’’eq

waf

ers)

Global TSV Chip Wafer Forecast (All 3D Platforms)

Breakdown by Industry (12''eq wafers)

Yole Developpement © July 2012

TOTAL 417 868 585 845 837 971 1 345 597 2 403 275 3 904 902 6 257 613 9 576 906

© 2012 • 12


Global TSV Chip Production by 2017 Breakdown by End Product (12’’eq. Wafers)

Mobile Phone 3 950 514

43%

Tablet 1 221 841

13%

Laptop 440 866

5%

Server 561 210

6%

Smart TV 467 332

5%

Game stations 386 693

4%

Game Station Controller 309 128

3%

Set-Top Box and Hybrid Set-Top Box 343 667

4% HPC

403 357 4%

Automotive: Total 204 373

2%

DSC Camera 154 508

2%

Network (Switch, Router, Appliance) 162 310

2%

Desktop PC

134 717 1%

General Lighting (LED Packages) 128 308

1%

Data Center 70 302

1% SLR Camera

57 363 1%

Surveillance & IP Camera 75 603

1% Base stations

43 411 0%

TSV Chip Production Forecast by 2017 (All 3D Platforms) Breakdown by key end product (12''eq. wafers)

Yole Developpement © May 2012

© 2012 • 13


Samsung’s TSV / WLP

in mobile phone CIS

TSV / WLP reality in low-end, FSI CMOS image sensors

BYD’s CSP camera module

Galaxycore’s 3D WLCSP of

CMOS image sensors

SuperPix’s TSV package in

2MPixels CMOS image sensors Omnivision’s WLCamera with TSV / WLP Sharp’s WLCamera with TSV / WLP

STMicro’s WLCamera with TSV / WLP

Toshiba’s WLCamera with TSV / WLP

OnSemi / Cypress’s3D WLCSP

of medical CMOS image sensor

SK Hynix WLP / TSV

in CMOS image sensors

• Most low-end CIS (CIF, VGA to 2MPixels resolutions) are adopting 3D WLCSP packaging:

© 2012 • 14


Presentation of Yole’s activities

© 2011 • 15

Copyrights © Yole Développement SARL. All rights reserved.

• Yole Développement provides powerfull tools and services…

– Strategic analysis

– Technology evaluation

– Market Research & Marketing analysis

– Specific services for investors by Yole Finance

Yole Développement activity & services

• …In 6 high technology areas

MEMS

Photovoltaic

Advanced packaging

Microfluidics

Power electronics

Compound semiconductors

© 2011 • 16


Yole activities in Advanced Packaging

Media business News feed / Magazines / Webcasts

www.yole.fr

© 2009


HB-LED Packaging Technology & Market Trends

IR

Osram

Market Research

Reports Strategy

Consulting services

http://www.yole.fr/pagesAn/products/Report_sample/3DIC.pdf




© 2011 • 17


NEW service: IP analysis

Phase II depends on Phase I results. Phase III depends on phase II results.

© 2011 • 18


About Yole’s Advanced Packaging Analysts team (1/2)

Jerome Baron – Jerome is the business unit

manager of the semiconductor

packaging market research at

Yole Developpement. He has

been following the 3D packaging

market evolution since its early

beginnings at the device,

equipment and material levels.

He was granted a Master of

Science degree from INSA-Lyon

in France as well as a Master of

Research from INL – Lyon

Institute of Nanotechnology

Contact: [email protected]

Lionel Cadix – Lionel joined Yole after the

completion of several projects

linked to the

characterization and modeling of

high density TSV and 3DIC chip

stacking in collaboration

with CEA-Leti and

STMicroelectronics during his

PhD. He is author of several

publications and 8 patents in

the field of 3D Integration Contact: [email protected]

Phil Garrou – Phil recently joined Yole

Développement forces as senior

technical advisor in the fields of

advanced packaging. Phil as

more than 20 years extensive

experiences in the

semiconductor industry where he

mainly served as global

marketing manager for DOW

Chemical’s BCB polymer

business


Jean-Marc Yannou – Jean-Marc joined Yole

Développement as technology

and market expert in the fields of

advanced packaging and

Integrated Passive Devices. He

has 15-years of experience in the

semiconductor industry. He

worked for Texas Instruments &

NXP semiconductors where he

was Innovation Manager for

System-in-Package technologies


© 2011 • 19


Amandine Pizzagalli – Amandine recently joined Yole

Development Advanced

Packaging and MEMS

manufacturing teams after

graduating as an engineer in

Electronics, with a

specialization in

Semiconductors and Nano

Electronics Technologies. She

worked in the past for Air

Liquide with an emphasis on

CVD and ALD processes for

semiconductor applications


Eric Mounier – Dr. Eric Mounier co-founded Yole

Developpement in 1998. He is in

charge of technology analysis for

MEMS related manufacturing

technologies within the company.

In the 3D Packaging area, Eric has

developed a unique Cost modeling

tool “TSV+” able to simulate to the

cost of ownership of several

different Through-Silicon-Vias and

3D integration scenarios


About Yole’s Advanced Packaging Analysts team (2/2)

Documents

Yole 3DIC & TSV Interconnects July 2012 Sample[1]