Yan-Yu Huang, 2013 IEE5008 Autumn 2013 Memory Systems NAND
Flash Memory Controller Yan-Yu Huang Department of Electronic
Engineering National Chiao Tung University, Hsinchu, Taiwan, R.O.C.
[email protected]
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Outline
Introduction Overview of a Basic Controller Structure Flash
Translation Layer Multichip Parallelism in Flash memory A variety
of Different Architectures Controllers Conclusion Reference 2
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Introduction
Improve chip performance Bit-flipping errors Bad blocks Increase
battery life Reduces the CPU load on the device Do the operation
independently Increases the overall throughput Reduce the load on
the system 3
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Introduction
Integrated controller Smaller chip size Cheaper cost Inevitable
delay between a new Flash technology Dedicated or External
controller Sourced independently of other parts. More flexible
design Cost more money 4
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Overview of
a Basic Controller Structure Host may be a computer or a terminal.
FTL translates host request into flash request. Controller decide
what time and which chip should work. Flash chip do read, write
page or erase block. 5 Flash Controller FTL Host
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Flash
Translation Layer ( FTL ) Maintain a mapping between logic address
and physical address. Page level One logical sector maps one
physical block. More flexible Requires a large amount of memory for
mapping table. Block level One logical block maps one physical
block. It requires extra flash operations when only a few pages in
a logical block are modified. 6
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Flash
Translation Layer ( FTL ) A basic structure of FTL Garbage
Collection Bad Block Management Error Checking and Correcting Wear
Leveling Low Level Driver 7 Flash Controller FTL Host
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Garbage
Collection Collect the valid data from the scattered blocks 8
Slide 9
NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Low Level
Driver Provide basic operation. That executes the operation
directly on NAND Flash memory device. Read Write Erase 9
Slide 10
NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Error
Checking and Correcting ( ECC ) That can detect and correct the
most common kinds of internal data corruption. Maintains a memory
system immune to single-bit errors. 10 N: the number of bits of a
block E : the number of errors in a block P : the bit error
rate
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Wear
Leveling Maximizes the life span of NAND flash as each cell is used
evenly. Static Dynamic 11
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Wear
Leveling Implementing static wear leveling. All good blocks are
evenly distribute the wear. With an additional step Implementing
dynamic wear leveling. Select the one with the lowest erase count
for the next write Only the non-static part of array is
wear-leveling 12
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Bad Block
Management ( BBM ) Perform write verification and remapping to
spare sectors in case of write failure. 13
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Bad Block
Management ( BBM ) Skip Block Method With a bad block table when
the target address is address of bad block then chose the next.
Reverse Block Method re-directed to a 14 Reserved Block Area
Slide 15
NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Multichip
parallelism in Flash memory Flash memory management High data
accessing speed Chip-level Bus-level 15 Flash Controller FTL
Host
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Multichip
parallelism in Flash memory Chip-level Increase the effective
bandwidth of flash operations. Maximum bandwidth is limited by the
bus. 16
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Multichip
parallelism in Flash memory Bus-level Parallel flash operation can
across chips by different flash bus. Cost more area than
chip-level. 17
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 A variety of
Different Architectures Controllers Chip-level For FPGA application
Bus-level & Chip-level Scalable Multi-channel Parallel
Controller 18 Flash Controller FTL Host
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Controller
for FPGA Application Provides a main state-machine with an enhance
command. 19 System reset Enable signal Sub-state machine Interrupt
signal timing sequences Reverse Block Method
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Scalable
Multi-channel Parallel Controller Multi-channel parallelism 20
Addressed uniformly state
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Scalable
Multi-channel Parallel Controller Switching fabric to implement the
multi-channel parallel access mechanism. 21 Stored the request
Select signal Data path The number of the request Data command
address
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Scalable
Multi-channel Parallel Controller The single controller Main
Control Module ECC Module 22 request Implement the control of flash
operation control logic
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Scalable
Multi-channel Parallel Controller Main Control Module Core of the
single controller with a main state machine. 23 Stored the data
need to input or output request Main control logic Main state
machine Sub-state machine Generate different control signal
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Scalable
Multi-channel Parallel Controller ECC Module Generates a ECC code
of each page Detect the bit-flipping errors Modify one bit error 24
request Program page operation data ECC code Spare data area of the
target chip
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Scalable
Multi-channel Parallel Controller ECC Module Generates a ECC code
of each page Detect the bit-flipping errors Modify one bit error 25
request read page operation Old code Bit-flipping error ? New code
Address of error bit
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Conclusion
Controller for FPGA Application Advantage Without caring about the
timing sequences Replace the invalid block Disadvantage
Bit-flipping Reliability The scalable Multi-channel Parallel
Controller Advantage Exploit the multi-chip parallelism to improve
the bandwidth. New dynamic replacing strategy for the mapping
table. Disadvantage For increase the bandwidth more channel will be
needed. 26
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Conclusion
Improve chip performance Handle the bit errors Bad blocks
management Wear leveling High data accessing speed Flash memory
management A well designed controller gets the maximum bandwidth of
the NAND Flash device, whereas poorly designed one only reduces
system performance. 27
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Reference
[1] Jose, S.T., Pradeep, C., Design of a Multichannel NAND Flash
Memory Controller for Efficient Utilization of Bandwidth in SSDs,
2013 International Multi-Conference on Automation, Computing,
Communication, Control and Compressed Sensing (iMac4s), pp.
235-239, Mar 2013. [2] Micron Technology, Inc. All Rights Reserved,
(2013), Choosing the Right NAND, Retrieved 2013 Nov 30 form
URL:http://www.micron.com/products/nand-flash/choosing-the-right-nand
[3] Yang Ou, Nong Xiao, Mingche Lai, A Scalable Multi-channel
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[5] Jose, S.T., Pradeep, C., Design of a Multichannel NAND Flash
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NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Reference
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