XC16x architecture

AI MC MA TMApr 21, 2023

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XC16xarchitecture

Interrupt Response Time


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Agenda

Advanced Interrupt System

– Definition of Interrupt Response Time

– Interrupt Flow

– Interrupt Response Time

Interrupt

PEC Transfer

– Conditions for Minimum Response Time

– Examples

– Spreadsheet

– Interrupt handling using Tasking Toolchain


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Interrupt Response Time (Definition)

First Instruction isexecuted

Interrupt occurs


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Interrupt Flow

Fast externalInterrupts

(synch. / edge)

PeripheralInterrupts

InterruptController /Arbitration

Interrupt Requests

CPU Core

Memory TypeVector Table

Jump Table CacheGlobal / Local

Context Sw itch

Interrupt RequestsInjection

Peripheral / Fast External Interrupt

Interrupt Controller

CPU


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Peripherals / Fast External Intrrupts

Fast External Interruptsynch. / edge

InterruptC

ontroller

PeripheralNode

(e.g.ASC0)FlipF lop

Interrupt Request L ine


PeripheralNode

(e.g.SSC0)FlipF lop


In te rrup t L ine 1

In terrup t L ine n

In terrup t L ine 1

In terrup t L ine n

3 PD clock cycles

2 PD clock cycles

2 PD clock cycles


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Interrupt Controller / CPU

CPU

Interrupt Request Lines

ArbitrationStage 1(InterruptSources)

ArbitrationStage 2(OCDS)

InterruptController

ITRAPInjection

Prepared /Executed

Jump VectorTable

JumpInterruptRoutine

Vector Table

2/4/8/16 word,includes address

to interruptroutine, or

program code

Interr. Routine

Context Switch

First Instruction

5 PD clock cycles 3 PD clock cyclesPrepares toinject ITRAP

(1 fcpu clock cycle)Execution of ITRAP(4 fcpu clock cycle)

4 fcpu clock cycles 4 fcpu clock cycles

Jump Table Cach

FINTxCSPFINTxADDR

BNKSELx

Interrupt Handling


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Interrupt Request Lines

ArbitrationStage 1(InterruptSources)

ArbitrationStage 2(OCDS)

InterruptController

ITRAPInjectionPrepared

5 PD clock cycles 3 PD clock cyclesPrepares to

inject ITRAP (1 fcpu clock cycle)

InjectionMOV [ ],[ ],Execution

Injection (1 fcpu clock cycle)

Execution of PEC instruction

(4 fcpu clock clock cycle)

CPU

Interrupt Controller / CPU

PEC Transfer


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Overview about Interrupt Response Time

Interrupt

PEC

5 + 3 PD cycle

5 + 3 PD cycleNext Generation (2 PD cycle)

2 (3) PD cycle

2 (3) PD cycle 1 + 1 + 4 +(...) fcpu cycle

1 + 4 + (4) + (...) fcpucycle


(synch. / edge)



Interrupt Requests

CPU Core

Memory TypeVector Table

Jump Table CacheGlobal / Local

Context Sw itch


Can be influenced by the user


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The total Interrupt Response Time becomes shorter with:

– Interrupt Jump Table Cache

The complete 24 bit address is supplied from a pair of dedicated register (FINTxCSP/FINTxADDE, instead of being fetched from the Interrupt Vector Table.

– Starting an ISR from the Interrupt Vector Table

As the amount of words reserved for any Interrupt within the Vector Table can be set to 2,4,8,16 using VECSC. Therefor it is possible to place the most time-critical instructions from a ISR just there. The rest of the ISR can be placed in another program location.

– Using Local Register Bank


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Jump Table Cache

Interrupt entry point

enableinterrupt priority(12-15)

segment address


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Register Banks (local / global)

Register banks (local/global) can be selected for an interrupt level greater or equal 12, with group level 0..7


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Location of In terruptService Routine /

S tack

Location of In terruptVector Table

Type of Execution

Context Switch

PRAM / DPRAM

PRAM

Directly from VectorTable / Jum p Table

Cache

Local Bank

Int. F lash / DSRAM

Int. F lash

V ia Vector Table

G lobal Bank

External M em ory

External M em ory

In terrupt R esponse T im e

Short Long


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Interrupt Response Time (Optimum / Minimum Timing)

The optimal interrupt time ( 23 cpu clock cycle) based on following assumptions.

– Code / Interrupt Vector Table / stack are located in dual ported internal program memory

– PDBUS+ clock speed = CPU clock speed

– no previous interrupt request is still proceeded

– no stall / cancellation of the pipeline

– Target address from Interrupt Vector Table holds a JMPS instruction to the start point of an ISR

Jump Table cache reduce interrupt response time to 19 cpu clock cycle

– either local register bank or no context switch


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Example (Interrupt)


(synch. / edge)



Interrupt Requests

CPU Core

PRAM,Jump Table Cache,

Local ContextSwitch,

PD clock = CPUclock,

optimal pipline flow


2 (3) CPU Cycle 8 CPU Cycle 9 CPU Cycle++ =

19 (20) CPU Cycle,475ns (500ns) @ 40 MHz


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Example (PEC)


(synch. / edge)



Interrupt Requests

CPU Core

PRAM,PD clock = CPU

clock,optimal pipline flow


2 (3) CPU Cycle 8 CPU Cycle 6 CPU Cycle++ =

16 (17) CPU Cycle,400ns (425ns) @ 40 MHz


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Interrupt Response Time (additional delays)

The following additional delays based on the assumption that PDBUS+ clock speed = CPU clock speed.

– Interrupt controller busy (up to 9 cpu clock cycle)

– Pipeline stalled / canceled (up to 4 cpu clock cycle)

– Slower Memory (e.g. external, single ported memory)

– Context switching of the global register bank (19 cpu clock cycle)

– Switching to the local banks by changing directly the bit field BANK within the PSW register causes cancellation of the complete pipeline (6 cpu clock cycle + time to fetch next instruction).


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Calculation of Interrupt Response Time (Spreadsheet)

CPU PDBus+ IVT Mem. PM Stack MAX

Constant Delays Step 1 1 1 1 1 2

Fixed CPU operations 10 6

Stack operations Step 2 3

Using Interrupt Jump Table Cache, ISR from PM x 2

Starting ISR directly from the IVT 2

Vector from the IVT, starting ISR from the PM 2 2

Dynamic Delays ( due to exact program flow and "random" external events )

Step 3Another Interrupt Request just started Arbitration 3 6

Data-access just preceeding x 1

Data-dependancy (write then read the same) just preceeding 2

Updating major CSFRs just preceeding 4 2

"Software" Delays ( due to Bank/Context Switching by user software )

Step 4Global Bank Switching (SCXT Instruction) 19

Changing Register Banks by writing to BANK field in PSW 6 2

The Result 23 CPU Clock Cycles of Total Response Time 10 6 0 2 3 2

Guidelines :

Step 1 1 - N Enter the timing characteristics of your system, measured by the CPU Clock Time for Word-operations!

Step 2 x Select the way ISR is started - just one!

Step 3 x Select combinations of "random" events; check different to find minimum/maximum delays.

Step 4 x Select one, if your software uses it.

Conventions : IVT Interrupt Vector Table

IVT Mem. Memory which holds the IVT

PM Program Memory

MAX Maximum Access Time for R/W operations in the system

Clock Repetition/Access Times compared to the CPU Clock

System-dependent


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Interrupt Response Time (Measurement) Timer T7 overflow

CC20

P9.4 / CC20IO

P1L.6

Interrupt

ISR T7:……….

BSET P1L.6………..

RETI


Main:While(1)

{BCLR P1L.6

}

ISR T7:Interrupt Priority Level 12

Group Level 0


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Tasking C-Compiler options / switches

_stacksize (num) //specifies the userstack adjustment in byte

_localbank (num) //local register bank switching (0,1,2,-1,-2)

0 = Global register bank

-1 / -2 = local register bank1/2, BNKSEL0 should be used

1 / 2 = local register bank1/2, PSW is set in the ISR ( not recommended !)

_cached //bypasses the interrupt vector table

#pragma noframe //omit the whole interrupt frame, allows you to make your own interrupt frame


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Interrupt (None)

interrupt (CC2_T7INT) void CC2_viTmr7(void) { #pragma asm BSET P1L.6 #pragma endasm }


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Interrupt (None)

Fcpu = 40 MHz


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Interrupt (Interrupt Jump Table Cache)

interrupt (CC2_T7INT) _cached void CC2_viTmr7(void) { #pragma asm BSET P1L.6 #pragma endasm }

void CC2_vInit(void){….. FINT0CSP = 0x8000 | (((unsigned long)&(CC2_viTmr7))>>16); FINT0ADDR = (unsigned int)&(CC2_viTmr7);}


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Interrupt (Interrupt Jump Table Cache)

Fcpu = 40 MHz


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Interrupt (Fast Bank Switching)

interrupt (CC2_T7INT) _localbank(-1) _stacksize(50) void CC2_viTmr7(void) { #pragma asm BSET P1L.6 #pragma endasm }

void CC2_vInit(void){…..BNKSEL0 = 0x0002; // Set local register bank 1 for Interr.level 12 / group 0}


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Interrupt (Fast Bank Switching)

Fcpu = 40 MHz


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Interrupt (Fast Bank Switching / Interrupt Jump Table Cache)

interrupt (CC2_T7INT) _localbank(-1) _stacksize(50) _cached void CC2_viTmr7(void) { #pragma asm BSET P1L.6 #pragma endasm }

void CC2_vInit(void){….. FINT0CSP = 0x8000 | (((unsigned long)&(CC2_viTmr7))>>16); FINT0ADDR = (unsigned int)&(CC2_viTmr7); BNKSEL0 = 0x0002; // Set local register bank 1 for Interr.level 12 / group 0

}


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Fcpu = 40 MHz


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interrupt (CC2_T7INT) _localbank(-1) _stacksize(50) _cached void CC2_viTmr7(void)#pragma noframe // omit the whole interrupt frame { #pragma asm BSET P1L.6 #pragma endasm }

void CC2_vInit(void){….. FINT0CSP = 0x8000 | (((unsigned long)&(CC2_viTmr7))>>16); FINT0ADDR = (unsigned int)&(CC2_viTmr7); BNKSEL0 = 0x0002; // Set local register bank 1 for Interr.level 12 / group 0

}


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Fcpu = 40 MHz

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XC16x architecture