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Very Large Scale Integration II - VLSI II

Memory Structures

Hayri Uğur UYANIK

Devrim Yılmaz AKSIN

ITU VLSI Laboratories

Istanbul Technical University

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Outline History Lesson General Memory Structure Memory Cell Types

– Volatile SRAM DRAM

– Non-Volatile MPROM EPROM OTP & UV-EPROM E2PROM FeRAM Memristor

Sense Amplifiers– Voltage Sense Amplifiers– Current Sense Amplifiers

Address Decoder Memory Modelling In Verilog References

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History Lesson

Delay line memory– Piezoelectric pulses within mercury– One of the earliest electronic (?) memory– 1000 word storage

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General Memory Structure

Address Decoder

Memory Cell Array

DATA_IN[7:0]

Sense Amplifier

DATA_OUT[7:0]

ADR[3:0]

R/W

DATA[7:0]DATA_IN[7:0]

DATA_OUT[7:0]

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Memory Cell Types

Volatile

– SRAM– DRAM

Non-Volatile

– MPROM– EPROM

OTP UV-EPROM E2PROM

– FeRAM– Memristor

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SRAM

Static Random Access Memory

QQ

BB

SEL

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SRAM

Not area efficient No special semiconductor process Fast Low power consumption Easy to communicate

Used in– Embedded systems– CPU Cache– FPGA CPLD LUT

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DRAM

Dynamic Random Access Memory

SEL

B

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DRAM Area efficient Very area efficient Needs special semiconductor process Slow Hard to communicate with High power consumption Needs refreshing

Used in – Computer primary storage– Video card primary storage– Cell Phones, PDAs

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DRAM Types

Asynchronous DRAM Synchronous DRAM (SDRAM)

– Single Data Rate (SDR SDRAM)– Dual Data Rate (DDR SDRAM)

Both rising and falling edge Memory cells are slow compared to bandwidth demand Bandwidth is increased by increasing the I/O buffer data rate

(DDR2 and DDR3)

– Dual DDR Communicate with two different RAM slots at the same time

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DRAM Types

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Dual Ported RAM

SRAMs and DRAMs can be dual ported– can read from and write to two different addresses at

the same time– Mostly effective in

Video processing– One port filling the RAM, one port is reading for display

CPU registers FIFOs

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MPROM

Mask Programmable ROM

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MPROM Programmed at the fab

– Route metal interconnects– Increase VT

Change channel implant Change gate oxide thickness

One time programmable Only few masks are changed Cheap in large volume

Used in– Old video games– Sound data in electronic music instruments– Electronic dictionaries

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OTP & UV-EPROM

One Time Programmable ROM UV Erasable Programmable ROM

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OTP & UV-EPROM

1. High VG and VD creates hot electrons

2. They penetrate gate oxide

3. They become trapped in the floating polysilicon

4. Additional negative charge below the gate increases VT (For a 5V ROM, VT increases from 1V to 8V)

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OTP & UV-EPROM OTP and UV-EPROM are the same

– OTP has a opaque plastic package (cheaper) – UV-EPROM has a package with transparent quartz window

(expensive) Need special semiconductor process Slow write High power consumption when writing Fast read OTP data is permanent UV-EPROMs can be erased

– When exposed to UV light for 20 minutes

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E2PROM

Electrically Erasable Programmable ROM

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E2PROM

Erasing:– VD=0, VS=0, VG=High (e.g. 15V)

– Floating gate becomes positively charged Fowler-Nordheim Tunneling

– VT below floating gate (VTFG) drops

Making Open Circuit:– EPROM like operation– VD=0, VS=High (e.g. 12V) VG=VTCG

– Channel present under control gate– Hot electrons penetrate gate oxide– VTFG increases

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E2PROM

Fast read/write Need special semiconductor process Low power consumption when writing

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FeRAM

Ferroelectric RAM

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FeRAM

Fast read/write Need special semiconductor process Low power consumption Destructive reading

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Memristor

Missing circuit element for 37 years– Concept: Leon Chua - 1971– First Realization: HP Labs - 2008

Final addition to RLC team

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Memristor

Charge dependent resistance (memristance)

Applied voltage or current changes charge (thus the resistance)– Resistance is stored in a non-volatile manner– Can be used to store digital data– Must be read with an AC signal for non-destructive

reading (AC does not change stored charge)

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V t

M q tI t

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Memristor

Best of both worlds– Non-volatile– Fast (~fDRAM/10)

– Dense (~1Pb/cm3)

Has a potential to alter the

computer programming paradigm– No need for two sets of memories (fast & volatile for

computing, slow & non-volatile for data storage)

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Sense Amplifiers

Voltage Sense Amplifiers

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Sense Amplifiers

Current Sense Amplifiers

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Address Decodermodule ADD_3_8 (in, out);

input [2:0] in;output [7:0] out;

reg [7:0] out;

always @(in) begincase (in)

3'b000 : out = 8'b00000001;3'b001 : out = 8'b00000010;3'b010 : out = 8'b00000100;3'b011 : out = 8'b00001000;3'b100 : out = 8'b00010000;3'b101 : out = 8'b00100000;3'b110 : out = 8'b01000000;3'b111 : out = 8'b10000000;

endcaseendendmodule

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Memory Modelling In Verilog parameter RAM_WIDTH = <ram_width>; parameter RAM_ADDR_BITS = <ram_addr_bits>; reg [RAM_WIDTH-1:0] <ram_name> [(2**RAM_ADDR_BITS)-1:0]; reg [RAM_WIDTH-1:0] <output_data>;

<reg_or_wire> [RAM_ADDR_BITS-1:0] <address>; <reg_or_wire> [RAM_WIDTH-1:0] <input_data>;

initial$readmemh("<data_file_name>", <ram_name>, <begin_address>, <end_address>);

always @(posedge <clock>) beginif (<ram_enable>)

if (<write_enable>)<ram_name>[<address>] <= <input_data>;

else<output_data> <= <ram_name>[<address>];

end

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References http://www.ieee.org/portal/cms_docs_sscs/sscs/08Winter/sunami-

fig3.jpg http://en.wikipedia.org http://www.seas.upenn.edu/~ese570/1244.pdf http://www.xtremesystems.org/forums/showthread.php?208829-

Memory-101-SDR-vs-DDR1-vs-DDR2-vs-DDR3 http://smithsonianchips.si.edu/ice/cd/MEMORY97/SEC09.PDF http://smithsonianchips.si.edu/ice/cd/MEMORY97/SEC07.PDF http://spectrum.ieee.org/semiconductors/design/the-mysterious-

memristor http://www.eecg.toronto.edu/~kphang/papers/2001/igor_sense.pdf Xilinx Documentation