WWROF Webinar K9LA Nov 2015 Design Issues for a 50W VHF/UHF Solid State RF Power Amplifier Carl Luetzelschwab K9LA [email protected] thanks WWROF

WWROF Webinar K9LA Nov WWROF Webinar K9LA Nov 20152015

Design Issues for a 50W Design Issues for a 50W VHF/UHF Solid State RF VHF/UHF Solid State RF

Power AmplifierPower Amplifier

Carl Luetzelschwab Carl Luetzelschwab K9LAK9LA

[email protected]@arrl.net

http://k9la.ushttp://k9la.us

thanks WWROF (wwrof.org)thanks WWROF (wwrof.org)

11


Who Is K9LA?Who Is K9LA?• First licensed in October 1961 as WN9AVTFirst licensed in October 1961 as WN9AVT

– Selected K9LA in 1977Selected K9LA in 1977

• Enjoy propagation, DX, contests, antennas, vintage rigsEnjoy propagation, DX, contests, antennas, vintage rigs

• RF design engineer by profession (RF design engineer by profession (mostly RF power amplifiersmostly RF power amplifiers))– BSEE 1969 and MSEE 1972 from Purdue UniversityBSEE 1969 and MSEE 1972 from Purdue University– Motorola Land Mobile 1974 to 1988 (Motorola Land Mobile 1974 to 1988 (Schaumburg and Fort WorthSchaumburg and Fort Worth))

• FM Power Amplifiers from 30 MHz to 512 MHz at 30 W to 100 WFM Power Amplifiers from 30 MHz to 512 MHz at 30 W to 100 W• Patent Patent US4251784 Apparatus for Parallel Combining An Odd Number of Semiconductor DevicesUS4251784 Apparatus for Parallel Combining An Odd Number of Semiconductor Devices

– Raytheon (formerly Magnavox) 1988 to Oct 2013 (Raytheon (formerly Magnavox) 1988 to Oct 2013 (Fort WayneFort Wayne))• Power Amplifiers from 30 MHz to 2 GHz and from 10 W to 1 KWPower Amplifiers from 30 MHz to 2 GHz and from 10 W to 1 KW

• Constant envelope waveforms (for example, FM) and non-constant Constant envelope waveforms (for example, FM) and non-constant envelope waveforms (for example, OFDM)envelope waveforms (for example, OFDM)

• Patent Patent 20040100341 MEMS-Tuned High-Power High-Efficiency Wide-Bandwidth Power Amplifier20040100341 MEMS-Tuned High-Power High-Efficiency Wide-Bandwidth Power Amplifier

22


IntroductionIntroduction

• A linear RF power amplifier (PA) takes a little A linear RF power amplifier (PA) takes a little signal and makes it bigger without losing fidelitysignal and makes it bigger without losing fidelity

theoretically!theoretically!

• This presentation discusses several design This presentation discusses several design issues for a very broadband 50 Watt power issues for a very broadband 50 Watt power amplifieramplifier

• This presentation is not a construction projectThis presentation is not a construction project• This presentation does not discuss all the issues This presentation does not discuss all the issues

tied to RF power amplifier designtied to RF power amplifier design– There are books that do thisThere are books that do this

• Cripps, Kenington, Dye & Granberg, etcCripps, Kenington, Dye & Granberg, etc

33


My Work With TransistorsMy Work With Transistors• 1974-1988: BJTs (bipolar junction transistors)1974-1988: BJTs (bipolar junction transistors)

– My early days at Motorola – wow, 6 dB gain at 450 MHz!My early days at Motorola – wow, 6 dB gain at 450 MHz!• 1988-2000: Vertical MOS (metal oxide 1988-2000: Vertical MOS (metal oxide

semiconductors)semiconductors)• 2000-2010: Lateral MOS (LDMOS)2000-2010: Lateral MOS (LDMOS)

– More gain than Vertical MOS, better thermal interfaceMore gain than Vertical MOS, better thermal interface– About $1/watt when I retired in October 2013About $1/watt when I retired in October 2013

• 2010-2013: GaN (gallium nitride)2010-2013: GaN (gallium nitride)– Less dispersion of output parameters vs freqLess dispersion of output parameters vs freq

• Easier to match over wide range of frequenciesEasier to match over wide range of frequencies– Depletion mode – need negative gate voltageDepletion mode – need negative gate voltage

• Voltage sequencing requiredVoltage sequencing required– About $4/watt when I retired in October 2013About $4/watt when I retired in October 2013

• Summary for my designsSummary for my designs– LDMOS in PAs below 1 GHz and narrow band PAs up to 2 LDMOS in PAs below 1 GHz and narrow band PAs up to 2

GHzGHz– GaN for wideband PAs from 30 MHz to 2 GHzGaN for wideband PAs from 30 MHz to 2 GHz

44

Put up your grids and let’s settle this once and for all!


Broadband DesignBroadband Design• Let’s look at a 50 W PA from low VHF thru Let’s look at a 50 W PA from low VHF thru

high UHF for a multitude of waveformshigh UHF for a multitude of waveforms– 50 W means 50 W PEP (50 W means 50 W PEP (Peak Envelope PowerPeak Envelope Power) )

capabilitycapability• 50 W continuous (slow CW) if heat sink and power 50 W continuous (slow CW) if heat sink and power

supply are adequatesupply are adequate

• 50 W PEP for SSB50 W PEP for SSB

• 12.5 W carrier for AM (12.5 W carrier for AM (AM peak-to-carrier ratio = 6 dBAM peak-to-carrier ratio = 6 dB))

• Use a BLF645 push-pull LDMOS transistorUse a BLF645 push-pull LDMOS transistor– From NXP (formerly Philips)From NXP (formerly Philips)

• Suitable for 6m, 2m, 1.25m, 70cm and Suitable for 6m, 2m, 1.25m, 70cm and 33cm amateur bands (50 – 928 MHz)33cm amateur bands (50 – 928 MHz)

55


Design DecisionsDesign Decisions• IdqIdq

– Class AB for decent linearity (for non-constant Class AB for decent linearity (for non-constant envelope waveforms) with reasonable efficiencyenvelope waveforms) with reasonable efficiency

– How far into Class AB?How far into Class AB?• Other classes (A, B, C, D, E, F, FOther classes (A, B, C, D, E, F, F-1-1, S, etc) – not addressed, S, etc) – not addressed

• Drain-to-gate feedbackDrain-to-gate feedback– Reduce gain at low-frequencies for improved Reduce gain at low-frequencies for improved

stabilitystability

– Reduce dispersion of ZReduce dispersion of Zinin

– Flatten gain across operating bandwidthFlatten gain across operating bandwidth

• Desired load impedanceDesired load impedance– To meet output power, efficiency and linearity goalsTo meet output power, efficiency and linearity goals

66


Idq from ADSIdq from ADS• Use Agilent’s ADS Use Agilent’s ADS

(Advanced Design (Advanced Design System) to simulate System) to simulate Id vs VgId vs Vg

VARVAR2V_drain=28.0

EqnVar

ParamSweepSweep1

Step=0.01Stop=2.5Start=1.8SimInstanceName[6]=SimInstanceName[5]=SimInstanceName[4]=SimInstanceName[3]=SimInstanceName[2]=SimInstanceName[1]="DC1"SweepVar="V_gate"

PARAMETER SWEEP

NXP_BLF645_v0p10X1Zth_Enable=1

OptionsOptions1

MaxWarnings=10GiveAllWarnings=yesI_AbsTol=I_RelTol=V_AbsTol=V_RelTol=DC_ConvMode=0Tnom=25Temp=25

OPTIONS

VARVAR1V_gate=.00

EqnVar

DCDC1

Pt=Dec=Lin=Center=Step=1Stop=50Start=0SweepPlan=SweepVar=

DC

V_DCSRC1Vdc=V_drain V

I_ProbeI_gate

V_DCSRC2Vdc=V_gate V

I_ProbeI_drain

1.9 2.0 2.1 2.2 2.3 2.41.8 2.5

0.5

1.0

1.5

0.0

2.0

V_gate

I_dr

ain.

i

Readout

m1

m1indep(m1)=plot_vs(I_drain.i, V_gate)=0.507freq=0.0000000Hz

2.190

V_gate

1.8001.8101.8201.8301.8401.8501.8601.8701.8801.8901.9001.9101.9201.9301.9401.9501.9601.9701.9801.9902.0002.0102.0202.0302.0402.0502.0602.0702.0802.0902.1002.1102.1202.1302.1402.1502.1602.1702.1802.1902.2002.2102.2202.2302.2402.2502.2602.2702.2802.2902.3002.3102.3202.3302.3402.3502.3602.3702.3802.3902.4002.4102.4202.4302.4402.4502.4602.4702.4802.4902.500

I_drain.ifreq=0.000

21.34 mA24.14 mA27.23 mA30.61 mA34.30 mA38.30 mA42.62 mA47.27 mA52.28 mA57.65 mA63.40 mA69.57 mA76.17 mA83.24 mA90.80 mA98.87 mA107.5 mA116.7 mA126.5 mA136.9 mA148.0 mA159.8 mA172.2 mA185.4 mA199.4 mA214.0 mA229.5 mA245.7 mA262.8 mA280.7 mA299.4 mA319.0 mA339.4 mA360.7 mA382.8 mA405.9 mA429.8 mA454.5 mA480.2 mA506.7 mA534.0 mA562.3 mA591.4 mA621.3 mA652.1 mA683.7 mA716.1 mA749.4 mA783.4 mA818.3 mA853.9 mA890.2 mA927.4 mA965.2 mA1.004 A1.043 A1.083 A1.124 A1.165 A1.207 A1.250 A1.293 A1.337 A1.381 A1.426 A1.472 A1.518 A1.565 A1.612 A1.659 A1.708 A

each side of the push-pull transistor

77

light AB

heavy AB

medium AB


FeedbackFeedback

• I’ve always believed it’s a good idea to use I’ve always believed it’s a good idea to use some feedback to improve low frequency some feedback to improve low frequency stabilitystability

• I usually used drain-to-gate feedbackI usually used drain-to-gate feedback

• Sometimes need additional series R at gate or Sometimes need additional series R at gate or shunt R at gate for stabilityshunt R at gate for stability

DrainGate

LL1L=yy nH

CC1C=zz pF

RR1R=xx Ohm

88

L1 is usually parasitic inductance from layout and parts themselves


Input Impedance from ADS Input Impedance from ADS

RR5R=50 Ohm

RR7R=50 Ohm

RR8R=50 Ohm

RR6R=50 Ohm

RR4R=50 Ohm

RR3R=50 Ohm

RR2R=50 Ohm

RR1R=50 Ohm

TFTF1T=1.00

CC4C=0.75 pF

S1PSNP30File="C:\d\ads\C06BL851X-5UN-X0B - PORT EXTENSIONS.S1P"

1

Ref

DC_FeedDC_Feed5

DC_BlockDC_Block4

DC_FeedDC_Feed4

DC_BlockDC_Block2

TFTF2T=1.00

PortP2Num=2

DC_FeedDC_Feed3

DC_BlockDC_Block3

DC_FeedDC_Feed2

DC_BlockDC_Block1

PortP1Num=1

CC3C=0.75 pF

S1PSNP29File="C:\d\ads\C06BL851X-5UN-X0B - PORT EXTENSIONS.S1P"

1

Ref

PortP3Num=3

NXP_BLF645_v0p10X1Zth_Enable=1

PortP4Num=4

includes both sides of transistor and ideal 1:1 xfmrs

99

shunt C to ground is from resistor package

• Going to be lowGoing to be low

• Idq and feedback play Idq and feedback play important roleimportant role

• Would like small dispersion of Would like small dispersion of input impedance vs frequencyinput impedance vs frequency– tight impedance arctight impedance arc

• Look at combinations ofLook at combinations of– Feedback RFeedback R

• none (infinite none (infinite ), 800 ), 800 , 200 , 200

– Idq (each side)Idq (each side)• light AB (100 mA), medium light AB (100 mA), medium

AB (500 mA), heavy AB (1.5 AB (500 mA), heavy AB (1.5 A)A)


50 Ω

centered about 10 Ω

1010


Caveat on Input Caveat on Input ImpedancesImpedances

• They are s-parametersThey are s-parameters– Gates driven with small signal Gates driven with small signal

• BLF645 load impedance set to 50 BLF645 load impedance set to 50 each side each side– 100 100 drain-to-drain drain-to-drain– Actual desired load ~ VActual desired load ~ V22/(2 x Pout) = 13 /(2 x Pout) = 13 each side = 26 each side = 26

drain-to-drain (at low frequencies) drain-to-drain (at low frequencies)

• Output load impedance affects input impedanceOutput load impedance affects input impedance

• When bias BLF645 to ~ 3 A drain current When bias BLF645 to ~ 3 A drain current (emulating large signal) and terminate BLF645 with (emulating large signal) and terminate BLF645 with 26 26 drain-to-drain, ‘large signal’ input impedances drain-to-drain, ‘large signal’ input impedances are very similar to ‘small signal’ input impedancesare very similar to ‘small signal’ input impedances– Sometimes two “wrongs” make a “right” !Sometimes two “wrongs” make a “right” !

1111


Input Network DesignInput Network Design

• For 200 For 200 feedback and 500 mA Idq feedback and 500 mA Idq each sideeach side– ZZinin vs Frequency centered around 10 vs Frequency centered around 10

• 4:1 transformer is a good starting point4:1 transformer is a good starting point– Don’t put right at the body of the transistorDon’t put right at the body of the transistor

•Use a little bit of series L (in conjunction with Use a little bit of series L (in conjunction with shunt C) to step up the BLF645 input shunt C) to step up the BLF645 input impedance at the higher frequenciesimpedance at the higher frequencies

– BLF645 ZBLF645 Zinin decreases with increasing frequency decreases with increasing frequency

1212


Output Network DesignOutput Network Design

• What load impedance does the BLF645 What load impedance does the BLF645 want to see to meet output power, want to see to meet output power, efficiency and linearity goals?efficiency and linearity goals?

• Do load-pull in ADS with 200 Do load-pull in ADS with 200 feedback feedback and Idq = 500 mA (each side)and Idq = 500 mA (each side)

• DefinitionsDefinitions– Pdel is power delivered to load (in dBm)Pdel is power delivered to load (in dBm)– PAE is power added efficiency (in %)PAE is power added efficiency (in %)

• PAE = PAE = Pdel – PinPdel – Pin x 100 x 100 Vd x IdVd x Id

1313


ADS Load-PullADS Load-Pull

Vs_low

V_In

Vs_high

Refer to the PowerPoint (TM) presentation "LoadPullPres.ppt" within this example project directory for a detailed explanation of these load pull simulation setups.

Set these values:

Specify desired Fundamental Load Tuner coverage: s11_rho is the radius of the circle of reflection coefficients simulated. However, the radius of the circle will be reduced if it would otherwise go outside the Smith chart. If you want to override this and allow reflection coefficients outside the Smith chart, edit the SweepEquations VAR block, and set max_rho=mag(s11_rho)s11_center is the center of the circle of simulated reflection coefficientspts is total number of reflection coefficients simulatedZ0 is the system reference impedance

Set Load and Source impedances atharmonic frequencies

One Tone Load Pull Simulation; output power and PAE found at each fundamental load impedance

VARSTIMULUS

Vlow=2.19Vhigh=28.0RFfreq=50 MHzPavs=23.0_dBm

EqnVar

HarmonicBalanceHB1

Other=UseOptDamp=0 NormCheck=1Oversample[1]=FundOversample=16Order[1]=5Freq[1]=RFfreq

HARMONIC BALANCEVARVAR2

Z_s_5 =Z0 + j*0Z_s_4 = Z0 + j*0Z_s_3 = Z0 + j*0Z_s_2 = Z0 + j*0Z_s_fund = 7.8- j*2.2Z_l_5 = Z0 + j*0Z_l_4 = Z0 + j*0Z_l_3 = Z0 + j*0Z_l_2 =Z0 + j*0

EqnVar

ParamSweepSweep2

PARAMETER SWEEP

BLF645_preliminary_141w_ampX1

VARSweepEquations

Z0=10.0pts=100s11_center =-0.0 +j*0.1s11_rho =0.75

EqnVar

I_ProbeI_In

I_ProbeIs_low

V_DCSRC2Vdc=Vlow

P_1TonePORT1

Freq=RFfreqP=dbmtow(Pavs)Z=Z_sNum=1

S1P_EqnS1S[1,1]=LoadTunerZ[1]=Z0

P_ProbeP_Load

I

P

I_ProbeIs_high

V_DCSRC1Vdc=Vhigh

VARglobal ImpedanceEquations

EqnVar

LoadTuner varies impedances over desired range while recording Pdel and PAE

1414


PAE/Pdel DataPAE/Pdel Data• Frequency is 50 MHzFrequency is 50 MHz

• Pin = +23 dBmPin = +23 dBm

• ZZoo of Smith chart is 10 of Smith chart is 10

• Max Pdel is +48.09 dBmMax Pdel is +48.09 dBm

• Max PAE is 62.69%Max PAE is 62.69%

• Max Pdel and PAE usually Max Pdel and PAE usually don’t occur at the same don’t occur at the same load impedanceload impedance

• Decision – design for Decision – design for max Pdelmax Pdel– ZZdesired loaddesired load = 21.5 – j 6.8 = 21.5 – j 6.8

• PAE at max Pdel ~ 50%PAE at max Pdel ~ 50%

• Pdel at max PAE ~ 45 Pdel at max PAE ~ 45 dBmdBm

Eqn Pdel_step=0.50

Eqn PAE_step=2.0

Eqn NumPAE_lines=20

Eqn NumPdel_lines=30

Set Delivered Powercontour step size (dB)and PAE contour stepsize (%), and number ofcontour lines

m1indep(m1)=PAE_contours_p=0.727 / 1.912level=62.586459, number=1impedance = 62.477 + j6.417

1m2indep(m2)=Pdel_contours_p=0.415 / -18.275level=48.084778, number=1impedance = 21.540 - j6.765

2

indep(PAE_contours_p) (0.000 to 33.000)

PA

E_co

nto

urs

_p

10.645 / 18.949

m1

indep(Pdel_contours_p) (0.000 to 41.000)

Pdel_

conto

urs

_p

20.767 / 124.731

m2

m1indep(m1)=PAE_contours_p=0.727 / 1.912level=62.586459, number=1impedance = 62.477 + j6.417

1m2indep(m2)=Pdel_contours_p=0.415 / -18.275level=48.084778, number=1impedance = 21.540 - j6.765

2

10.000SystemReference Impedance

PAE (red) and Delivered Power (blue) Contours

48.09

Maximum PowerDelivered, dBm

62.69

Maximum Power-AddedEfficiency, %

max Pdel

max PAE

1515


Desired ZDesired Zloadload vs Frequency vs Frequency• Do load-pull at other frequenciesDo load-pull at other frequencies

– 50 MHz50 MHz 21.5 – j 6.8 21.5 – j 6.8 – 145 MHz145 MHz 19.2 – j 5.6 19.2 – j 5.6 – 220 MHz220 MHz 16.8 – j 4.4 16.8 – j 4.4 – 440 MHz440 MHz 16.5 + j 6.0 16.5 + j 6.0 – 750 MHz 11.8 + j 3.2 750 MHz 11.8 + j 3.2 – 902 MHz902 MHz 5.0 + j 8.0 5.0 + j 8.0

• All impedances are drain-to-drainAll impedances are drain-to-drain– Plotted on 12.5 Plotted on 12.5 Smith chart Smith chart

• Desired load mostly around 12.5 Desired load mostly around 12.5 – Suggests 4:1 xfmrSuggests 4:1 xfmr

• Using simple formula, we Using simple formula, we estimated 26 estimated 26 at low frequencies at low frequencies– That’s about where 50 MHz isThat’s about where 50 MHz is

50 MHz

12.5 Smith chart

1616

as frequency increases, desired load impedance decreases


ADS Model: PWB and ADS Model: PWB and SchematicSchematic

Vout

V4V3V2V1

Vf wd

Vrefl

S_Param

SP1

Step=50 MHz

Stop=950 MHz

Start=50. 0 MHz

S-PARAMETERS

Term

Term1

Z=50 O hm

Num=1

VAR

VAR1

opf req=1. 0

E q nV a r

HarmonicBalance

HB1

FundO versample=32

O rder[1]=3

Freq[1]=opf req

HARMONIC BALANCE

V_DC

SRC1

Vdc=28. 0 V

Attenuator

ATTEN1

VSWR=1

Loss=0 dB

S1P

SNP13

File="C: \ d\ ads\ C18BL103X-4UN-X0B-ENG - PO RT EXTENSI O NS. S1P"

1

R e f

CO AX

TL3

Er=2. 1

L=3000 mil

Do=34. 4 mil

Di=12. 4 milCO AX

TL1

Er=2. 1

L=900 mil

Do=41. 0 mil

Di=24. 0 mil

CO AX

TL2

Er=2. 1

L=900 mil

Do=41. 0 mil

Di=24. 0 mil

SRLC

SRLC1

C=8. 2 pF

L=0. 5 nH

R=0. 1 O hm

SRLC

SRLC2

C=12. 0 pF

L=0. 5 nH

R=0. 1 O hm

CouplerDual

CO UP1

ZRef=50. O hm

Direct1=100 dB

Loss1=0. dB

CVSWR1=1.

MVSWR1=1.

Coupling=20. 0 dB

1

3

2

4

S1P

SNP11

File="C: \ d\ ads\ 2861000202_UT85_1R6_output4to1_1core_BLF645EvalBd. S1P"

1 R e f

S1P

SNP10

File="C: \ d\ ads\ 2861000202_UT85_1R6_output4to1_1core_BLF645EvalBd. S1P"

1 R e f

S1P

SNP12

File="C: \ d\ ads\ 366192_804_CHO KI NG _I ND_output1to1_1core. S1P"

1 R e f

S1P

SNP9

File="C: \ d\ ads\ 366192_801_CHO KI NG _I ND_input4to1_1core. S1P"

1 R e f

S1P

SNP8

File="C: \ d\ ads\ 366192_801_CHO KI NG _I ND_input4to1_1core. S1P"

1 R e f

S1P

SNP7

File="C: \ d\ ads\ 366192_802_CHO KI NG _I ND_input1to1_2cores. S1P"

1 R e f

WI RE

Wire12

Rho=1. 0

L=150 mil

D=12. 4 mil

WI RE

Wire11

Rho=1. 0

L=150 mil

D=12. 4 milWI RE

Wire7

Rho=1. 0

L=150 mil

D=24. 0 mil

WI RE

Wire9

Rho=1. 0

L=175 mil

D=24. 0 mil

WI RE

Wire10

Rho=1. 0

L=175 mil

D=24. 0 mil

WI RE

Wire8

Rho=1. 0

L=50. 0 mil

D=1. 0 mil

R

R8

R=50 O hm

R

R7

R=50 O hm

WI RE

Wire5

Rho=1. 0

L=150 mil

D=12. 6 mil

WI RE

Wire6

Rho=1. 0

L=150 mil

D=12. 6 mil

WI RE

Wire2

Rho=1. 0

L=100 mil

D=12. 6 mil

WI RE

Wire3

Rho=1. 0

L=100 mil

D=12. 6 mil

WI RE

Wire1

Rho=1. 0

L=150 mil

D=11. 3 mil

WI RE

Wire4

Rho=1. 0

L=150 mil

D=11. 3 mil

CO AX

TL4

Er=2. 1

L=850 mil

Do=23. 0 mil

Di=12. 6 mil

CO AX

TL5

Er=2. 1

L=850 mil

Do=23. 0 mil

Di=12. 6 milCO AX

TL6

Er=2. 1

L=2000 mil

Do=37. 0 mil

Di=11. 3 mil

S1P

SNP3


1 R e f

S1P

SNP4


1 R e f

S1P

SNP6


1 R e f

Term

Term2

Z=50 O hm

Num=2

S1P

SNP5


1 R e f

C

C3

C=4. 0 uF

R

R1

R=0. 02 O hm

I _Probe

I _Probe1

S1P

SNP2

File="C: \ d\ ads\ C06BL851X-5UN-X0B - PO RT EXTENSI O NS. S1P"

1

R e f

S1P

SNP1

File="C: \ d\ ads\ C06BL851X-5UN-X0B - PO RT EXTENSI O NS. S1P"

1

R e f

R

R6

R=100 O hm

R

R5

R=100 O hm

R

R4

R=100 O hm

R

R3

R=100 O hm

V_DC

SRC2

Vdc=2. 19 V

C

C4

C=100 pFR

R2

R=100 O hm

C

C2

C=850 pF

C

C1

C=850 pF

L

L2

R=

L=160 nH

L

L1

R=

L=160 nH

BLF645a

BLF645a_1

ModelType=RF

NXP_BLF645_v0p10

X1

Zth_Enable=1

output 1:4

input 1:1balun input 4:1

output 1:1balun

BLF645

feedback

feedback

PWB artwork

1717

PWB + Schematic: InputPWB + Schematic: Input

excellent correlationexcellent correlation


m1freq=S(1,1)=0.114 / 135.564impedance = 41.946 + j6.807

50.00MHz

m2freq=S(1,1)=0.269 / -19.655impedance = 81.926 - j15.952

910.0MHz


50.00MHz


910.0MHz

freq (20.00MHz to 950.0MHz)

S(1

,1)

Readout

m1

Readout

m2S(2

,2)

Readout

m3

Readout

m4


50.00MHz


910.0MHz


50.00MHz


910.0MHz

simulated measured

Looking into input RF connector with 12.4Ω gate-to-gate chip resistor substituted for BLF645

1818

PWB + Schematic: OutputPWB + Schematic: Output

excellent correlationexcellent correlation



50.00MHz


910.0MHz


50.00MHz


910.0MHz

freq (20.00MHz to 950.0MHz)

S(1

,1)

Readout

m1

Readout

m2S(2

,2)

Readout

m3

Readout

m4


50.00MHz


910.0MHz


50.00MHz


910.0MHz

simulated measured

Looking into output RF connector with 12.4Ω drain-to-drain chip resistor substituted for BLF645

1919


Small-Signal ComparisonSmall-Signal ComparisonSimulated vs MeasuredSimulated vs Measured

S21 S11

good correlation overall

decent correlation between ‘PA CCA PWB’ and ‘Simulation’

2020

‘PA CCA PWB’ is measured breadboard‘Fig 3 App Note’ is data from NXP app note‘Simulation’ is from ADS model


Large-Signal ComparisonLarge-Signal ComparisonSimulated vs MeasuredSimulated vs Measured

at 28V

excellent correlation

decent correlation

2121

‘Measured’ is the breadboard‘Simulation’ is from ADS model


Large-Signal PerformanceLarge-Signal PerformanceMeasured DataMeasured Data

at 28V

2222

this is the breadboard


BLF645 Design BLF645 Design ImplementationImplementation

input 1:1balun

input 4:1 output 1:4output 1:1balun

BLF645drain-to-gate feedback (2 pl)

schematic and breadboard photo from NXP App Note AN10953

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Caveat On SimulationCaveat On Simulation• Simulation results are only as good as the models Simulation results are only as good as the models

usedused

• Chip capacitor example – 300 pF ATC 100B (Chip capacitor example – 300 pF ATC 100B (100 100

mil cubemil cube))• Very simple model – series CVery simple model – series C

• Better model – series RLCBetter model – series RLC

• Best model – from network analyzer measurement of Best model – from network analyzer measurement of capcap


multiple resonances

complicated but accurate to very high frequencies

R=0.1 Ω, L=0.5 nH

blue is measured

red is simulated

both images from Mark Walker KB9TAF presentation at an inter-company RF symposium

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Other Components, and IMDOther Components, and IMD• ResistorsResistors

– Series R-L is usually sufficientSeries R-L is usually sufficient– Generally not in the RF pathGenerally not in the RF path

• InductorsInductors– Might be some inter-winding capacitance at the higher frequenciesMight be some inter-winding capacitance at the higher frequencies

• RF transformersRF transformers– Used transmission-line transformers (TLT)Used transmission-line transformers (TLT)– Modeled with a length of coaxModeled with a length of coax– Impact of ferrite modeled as inductance of outer conductorImpact of ferrite modeled as inductance of outer conductor

• S-parameter measurement – we called it ‘magnetizing inductance’S-parameter measurement – we called it ‘magnetizing inductance’

• Simulating IMDSimulating IMD– Areas of concern: transistor model, impact of ferrite on xfmrsAreas of concern: transistor model, impact of ferrite on xfmrs– Use results cautiously - rule of thumb for medium Class AB – if PEP Use results cautiously - rule of thumb for medium Class AB – if PEP

of waveform is at P1dB, 2-tone IMD ~ -25 dBc or AM distortion ~ of waveform is at P1dB, 2-tone IMD ~ -25 dBc or AM distortion ~ 5%5%

WWROF Webinar K9LA Nov WWROF Webinar K9LA Nov 20152015 2525

0805 chip resistorXL about 6 ohms at 900 MHz

1:1 balun

More Simulation CommentsMore Simulation Comments• What if you don’t have simulation What if you don’t have simulation

capabilities?capabilities?– Design the old-fashioned wayDesign the old-fashioned way

• Start with data sheet impedancesStart with data sheet impedances

• Play around on the bench a lot – as Ed Paragi WB9RMA Play around on the bench a lot – as Ed Paragi WB9RMA and I did in our early PA design daysand I did in our early PA design days

• Simulation allows you to look at many “what Simulation allows you to look at many “what if” scenarios in a short amount of timeif” scenarios in a short amount of time

• The model can be used for trends, and if it’s The model can be used for trends, and if it’s good enough it can be used for absolute good enough it can be used for absolute results (usually the model of the transistor is results (usually the model of the transistor is the limiting factor)the limiting factor)

WWROF Webinar K9LA Nov WWROF Webinar K9LA Nov 20152015 2626

Simple Characterization of a Simple Characterization of a PAPA

• The November 2015 QST had a Product Review of a 6m amplifier – The November 2015 QST had a Product Review of a 6m amplifier – showed a plot of Pout vs Pinshowed a plot of Pout vs Pin

• Better way to characterize a PA – plot Gain vs PoutBetter way to characterize a PA – plot Gain vs Pout


• Gain vs Pout tells class of operation (flat gain is A or medium/high AB), tells gain Gain vs Pout tells class of operation (flat gain is A or medium/high AB), tells gain (from plot), shows compression, and indicates efficiency (A is least efficient)(from plot), shows compression, and indicates efficiency (A is least efficient)

• Gain vs Pout indicates linearity (flat gain best, gain expansion not good)Gain vs Pout indicates linearity (flat gain best, gain expansion not good)

full BLF645 design at 50 MHz

full BLF645 design at 50 MHz

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SummarySummary• Discussed design issues for a broadband VHF/UHF PADiscussed design issues for a broadband VHF/UHF PA

• More work needed for More work needed for completecomplete design design– PPinin from 0.2 – 1.0 W: could add gain compensation from 0.2 – 1.0 W: could add gain compensation

– Power supply: 28 V at 7 APower supply: 28 V at 7 A– Heat sink: max dissipation = 120 W Heat sink: max dissipation = 120 W need to get the heat out!need to get the heat out!– 5 harmonic filters: push-pull eases 2f rejection (see slide 22)5 harmonic filters: push-pull eases 2f rejection (see slide 22)– T/R Switch: relays easiest, could use PIN diodesT/R Switch: relays easiest, could use PIN diodes

– Directional coupler on output: PDirectional coupler on output: Pfwdfwd and P and Prefl refl , use P, use Pfwdfwd for ALC for ALC

• Harmonic filters, T/R Sw and dir cplr add lossHarmonic filters, T/R Sw and dir cplr add loss

• Simulation is a big help, but bench performance Simulation is a big help, but bench performance determines success or failuredetermines success or failure– Accurate models give accurate simulationsAccurate models give accurate simulations

• Thanks to WB9RMA and KB9TAF for comments to these Thanks to WB9RMA and KB9TAF for comments to these slidesslides

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Documents

WWROF Webinar K9LA Nov 2015 Design Issues for a 50W VHF/UHF Solid State RF Power Amplifier Carl Luetzelschwab K9LA [email protected] thanks WWROF