WS-03 | Wireless 100Gb/s and Beyond: Progress in Ultra

WS-03 | Wireless 100Gb/s and Beyond: Progress in Ultra-fast Wireless Communications

European Microwave Week 2017 EuMC

Development of Novel System and

Component Architectures for Future

Innovative 100 GBit/s Communication

Systems

Christian Carlowitz

[email protected]

Friedrich-Alexander Universität Erlangen-Nürnberg

research supported by German Research Foundation (DFG), SPP 1655

mailto:[email protected]


European Microwave Week 2017 EuMC Slide 2

Prof. Dr.-Ing. Martin Vossiek

Institute of Microwaves and Photonics (LHFT)


Prof. Dr.-Ing. Dr.-Ing. habil. Robert Weigel

Institute of Electronics Engineering (LTE)


Prof. Dr. sc. techn. habil. Frank Ellinger

Chair of Circuit Design and Network Theory (CCN)

Technische Universität Dresden

Prof. Dr.-Ing. Manfred Berroth

Institute of Electrical and Optical Communications

Engineering (INT)

Universität Stuttgart

Project Partners



1. Introduction

– Motivation

– SPARS Concept

– Transceiver Architecture

2. Project Topics

– LHFT: System Concept Investigation and Experimental Verification

– CCN: 180 GHz SPARS Receiver Frontend Design

– LTE: 180 GHz QAM Modulator and High Speed DAC Design

– INT: High Speed Receiver Analog Baseband Architectures and Design

3. Conclusion

Outline



High speed communication systems:

– Symbol rate up to 20% of carrier

– e.g. 2x18 GBaud at 180 GHz > 100 GBit/s wireless

Technological limitations:

– Operation close to process transit frequency

Low single-stage amplifier gain

– Scaling issues: Long amplifier chains, high area cost, high power

dissipation

Goal: Scalable, efficient and broadband quadrature transceivers

beyond homodyne architectures

Motivation



SPARS - „Simultaneous Phase and Amplitude Regenerative

Sampling“ - A disruptive technology

The ordinary approach SPARS / SRO approach

Gain: Gain (pos. feedback):

Example (with N=5; g = 2): Example: (with L=4; g = 2):

Power dissipation: Power dissipation:

g g g g s t tg s t

Ntg g

32tg

dP dP dP dP

5totald dP P

1

Ll

t

l

g g

totald dP P

g s t SWTtg t s t

30tg

+

sampling clk. (on/off switch)

Power consumption and complexity

dramatically reduced, especially

useful when working close to

transit frequency

2

g

dP swf



Novel Transceiver Architecture: „SPARS“, Simultaneous Phase and

Amplitude Regenerative Sampling

Major Benefits: Overcome scaling and power dissipation issues by:

– High gain boost with single stage amplifier (6 dB 30 dB)

– No PLL, no stabilized LO, no LNA or PA chains

– Employing self-mixing receiver approach

– Relaxing modulator power level requirements

System Concept



System Concept Investigation and

Experimental Verification



Super-regenerative oscillator vs. amplifier chain

Difference:

– amplifier chain adds noise

after each stage:

– SRO adds signal and noise

at each oscillation cycle:

Noise bandwidth?

– homodyne receiver: symbol rate is lower bound

(with sinc-shaped pulses, rect. filter)

– super-regenerative theory:

similar performance achievable

– at technological boundaries:

2-4 dB excess

overall: SRO and amplifier chain

comparable / slight SRO

advantage

Noise Figure, SNR/Sensitivity

1

1

1n

ac kk

F FF

G

sroF F

time time

oscillator open loop gain

optimal

+

- reality

+

-



SRO samples average input power during

sensitivity phase

countermeasures (if peak power limited):

– gain tuning faster rise, shorter sampling period

– slight compression widens peak maximum

– quench signal shaping hold unity gain on decay

Pulse Recovery



Minimum period: Oscillation rise

and decay + SNR margin

Dependencies:

– oscillator tank quality factor Q0

– active element gain M

Typically low open loop gain

(e.g. < 3 dB)

Rise time limitation (τ=2/f0 … 4/f0)

included in simulation

Results:

– 10x gain with 8-10% relative

symbol rate could be achieved

– Preliminary experimental

result with scaled demonstrator

• 270 MBaud measured @ 5.8 GHz

• 293 MBaud theoretical expectation

Achievable Data Rate

target

preliminary experimental results (scaled demonstrator)



Complete transmitter and receiver at 5.8 GHz, 150 MBaud (450 MBit/s)

– passive 8-PSK modulator (diode switched transmission lines, 11 dB loss)

– discrete SRO (electrically small, single port)

– filter/antenna from COTS components (~10 dB loss)

– Receiver: Isolator at input, self-mixing with cable delay line

Demonstrator Implementation

-9 dBm

-27 dBm

-7 dBm

-11 dBm

-45 dBm

-51 dBm -5 dBm

+46 dB

42 cm airgap



Complete Transmitter & Receiver:

– Modulation: 8-DPSK

• EVM < -18 dB (BER < 10-3)

• diff.: EVM < -21 dB

– Measured Deviations:

• TX EVM -30 dB (systematic)

• RX EVM -24 dB (stochastic)

– Sensitivity CW: -77 dBm, pulsed: -75 dBm

close to theoretical SNR=Ps/(k*T*B*F)

24 GHz 16-QAM Demonstrator (SRO only):

– 343 MBaud (1.37 GBit/s)

– 5 dB single stage gain

25 dB

– linear recovery of

amplitude and phase

Demonstrator Measurement Results



180 GHz SPARS Receiver Frontend Design



Most amplification is done in SRO

component

Many design compromises possible

e.g. gain, symbol rate, dynamic

range, etc.

Proper modelling of SRO circuit provides

guidelines for performance optimization

Large-signal behavior is of highest importance

Study relation between Vout and Vin in phase

and amplitude

Model implemented electrically using CAD tools

Cross-coupled topology chosen for monolithic

integratibility

Integrated mm-Wave Super-Regenerative Oscillators (mmW SROs)

Proposed Regenerative Receiver

Vsw

SROBuffer IF,I

Delay

Element Φ

IF,Q

LO

RF

LPF

LPF

A

κ

Vin Vout

nonlinear

gain

resonator

coupling

factor

Vsw



Ideal nonlinear model; no base

currents, numerical simulations

Amplitude and phase sampling

Influence of design variables on

performance can be studied

(e.g. loop gain, RC time constant, etc.)

Modeling of integrated mmW SROs

≡ Vin

Rs/2

Vout

Vsw

L/22*C

Vsw

SPDT

Q1 Q2

L/2L/2 C

Rs Vin

Vout

I0Vsw

κ

Amplitude Modulation Phase Modulation



Cross-Coupled mmW SRO in IHP 0.13-µm SiGe BiCMOS

Vb1

Q1 Q2

Vcc

Vb3 Vb3

Vcc Vcc

Q3 Q4

Q5 Q6

INJ+ INJ-

Vcc Vcc

Vb2Vb2

Q7 Q8

OUT+OUT-

SW

TL1 TL2

I1 I2/2I2/2

I3

Cf CfCc Cc

Rb1Rb1

Rb2 Rb2

Rb3

Rb4 Rb4

fosc (GHz) 148

PDC (mW) 48

fsw (GHz) 1

Pout (dBm) -6

Area (mm2) 0.66

Gain (dB) 36



Single-Ended Colpitts mmW SRO in IHP 0.13-µm SiGe BiCMOS

fosc (GHz) 160

PDC (mW) 6.6

fsw (GHz) 5

Pout (dBm) -8.4

Area (mm2) 0.64

Gain (dB) 18.4

Vb1 GND Iinj GND Vcc Io Vb2

INJ

GND

GND

OUT

GND

GND

SW

GN

D

GN

D

active

area

zero-Ohm

lines

Q1

Q2

Q3

Cout

C1

TL1

TL2

SW

Vb1

Io

Iinj

Vb2

OUT

INJ

Vcc

RbRm

TL3

TL4

Rc1

Rc2

Cm

Q4

Q5

Q6

R1

R2

-70

-60

-50

-40

-30

-20

-10

0

140 150 160 170 180

Sp

ec

tra

l P

ow

er

(dB

m)

Frequency (GHz)

Simulation

Measurement

Sinc Envelope

a)



180 GHz QAM Modulator and

High Speed DAC Design



Functionality

Generates 180 GHz carrier frequency with a times ten frequency multiplier

16 QAM modulation achieved via two radio-frequency Digital-to-Analog

Converters of 2 bit each with a modulation rate of up to 18 GS/s

SPARS based frontend



Radio-Frequency Digital-to-Analog Converter

0°

90°

• RFDAC combines D/A conversion and upsampling

• Reduced components compared

to e.g. homodyne architecture

I-Data

Q-Data

LO



Current steering principle

– Better spectral purity and wider bandwidth

Upsides

– Rejection of all outputs at DC and even

harmonics of fLO

– All transistors act as switches, hence no

linearity constraints

Linearity of output signal defined by:

– Resolution of converter

– Output impedance modulation

– Mismatch in timing

Radio-Frequency Digital-to-Analog Converter

Example of RF-DAC output

stage



Each RF-DAC consists of three identical

RF-DAC cells

– Current summation at the output via

broadband transmission lines

– Buffers for signal boosting and for

blocking of clock feed through

– Flip-Flops for retiming purposes

Output stage of each RF-DAC cell features

two parallel connected Gilbert cells working

as BPSK modulators

– Ratio between the transistors and

currents of the two Gilbert cells to be 3:1

– Transformer increases linearity and SNR

Design of a 2 bit 180 GHz RF-DAC for SPARS

RF-DAC Cell

RF-DAC output stage



High Speed Receiver Analog Baseband

Architectures and Design



SPARS baseband receiver

Functionality • Digitization of wideband inphase (I) and quadrature (Q) receive signals (> 9 GHz) by

PGA+ADC solution • External data storage on FPGA to ensure a sufficient number of receive samples for

• system demonstration experiments and • evaluation of link synchronization parameters (e.g., I/Q gain and phase

mismatches, etc.)

Analog baseband receiver



SPARS PGA

PGA architecture

PGA

. . . Programmable Gain Amplifier

0.4

mm

0.6 mm

G

S

S

G

G

S

S

G

C4 P C2 C0

DC P C3 C1

50 Ω 50 Ω Gain Control Circuitry with Preset

Voltage reference generator

50 Ω Transmission Line

5

16 dB0 dB

8 dB0 dB

4 dB0 dB

2 dB0 dB

1 dB0 dB

C<0:4>

Test Driver

in−

+out

−

+

DC Sense

Binary Control Signals

Die photograph Specifications

Gain range: Gain accuracy: Bandwidth:

31 dB in 1 dB steps -0.19/0.46 dB @ 1 GHz >10.1 GHz

implemented in 0.13 µm SiGe BiCMOS from IHP



Measurement Results

Achievements • Low-complexity PGA architecture • 31 dB gain range programmable in 1 dB steps • Gain accuracy smaller than 0.46 dB • >10.1 GHz 3-dB bandwidth



SPARS ADC

RF PCB (left) and die photograph (right)

ADC architecture

0.9

mm

1.4 mm

ADC PRBS FD

. . . Analog-to-Digital Converter . . . Pseudo Random Bit Sequence . . . Frequency Divider

implemented in 0.13 µm SiGe BiCMOS from IHP

50 Ω 50 Ω

2.6 V

clk

in

50 Ω 50 Ω 15 4

2.4 V

4

1:64 FD

4

MU

X

− +

− +

− +

− +

− +

D<0:3>

PRBS

DIV

4 bit flash ADC core

Scrambler

Gray encoder

211-1 PRBS

4

ref− +

Retiming Output Driver



b.)

a.)

c.)

d.)

e.)

f.)

g.)

ENA_PRBSENA_SCR

4



Measurement Results

Real-time measurement with 70 GHz sub-sampling scope

• Enables sampling rates from DC to 42 GS/s => more than 60% speed improvement to current state- of-the-art single-core ADCs with digital encoder (25 GS/s) • ENOB > 3 bits and SFDR >24.8 dBc within DC-20 GHz frequency band up to 39 GS/s • FOM = 8.3 pJ/conv.

FOM . . . Figure of Merit

Achievements



Novel transceiver architecture concept based on „Simultaneous Phase and

Amplitude Regenerative Sampling“

– significantly reduced system size and power consumption

(single-stage instead of multi-stage amplifiers, no receiver synthesizer, …)

– verified to be competitive to homodyne system in terms of noise and data

rate with scaled demonstrator

mmW Super-Regenerative Oscillator for 180 GHz target frequency

implemented and successfully verified

Transmitter RFDAC concept investigated and implemented to exploit relaxed

power level requirements from high SRO gain

4 bit ADC with up to 42 GS/s and outstanding performance as well as

wideband baseband PGA demonstrated experimentally

Next steps: Component integration to demonstrate mmW self-mixing

receiver

Conclusion



C. Carlowitz and M. Vossiek, “Demonstration of an Efficient High Speed Communication Link

Based on Regenerative Sampling,” in Proceedings of the International Microwave Symposium

(IMS2017), Honolulu, Hawaii, USA, June 2017.

C. Carlowitz and M. Vossiek, “Concept for a Novel Low-Complexity QAM Transceiver Architecture

Suitable for Close to Transition Frequency Operation,” in Proceedings of the IEEE MTT-S

International Microwave Symposium 2015 (IMS 2015), Phoenix, Arizona, USA, May 2015.

C. Carlowitz and M. Vossiek, “PSK Modulator for Regenerative Sampling Gigabit UWB

Communication,” in Proceedings of the 8th German Microwave Conference (GeMiC2014), Aachen,

Germany, Mar. 2014.

C. Carlowitz, A. Esswein, R. Weigel and M. Vossiek, “Concepts for Generation of Angle Modulated

mm-Wave UWB Signals for Communication and Ranging,” presented at the IMS 2013 Workshop

on RFICs/MMICs and Their Professional Wireless Sensing Applications, Seattle, USA, June 2013.

C. Carlowitz, A. Esswein, R. Weigel and M. Vossiek, “Regenerative Sampling Self-Mixing Receiver:

A Novel Concept for Low Complexity Phase Demodulation,” in Proceedings of the IEEE

International Microwave Symposium 2013, Seattle, USA, June 2013.

H. Ghaleb, M. El-Shennawy, Udo Jörges, C. Carta, and F. Ellinger, “Nonlinear Modeling of Cross-

Coupled Regenerative Sampling Oscillators,” IEEE PRIME, 2017.

H. Ghaleb, P. V. Testa, S. Schumann, C. Carta, and F. Ellinger, “A 160-GHz Switched Injection-

Locked Oscillator for Phase and Amplitude Regenerative Sampling,” accepted for publication in

IEEE MWCL, 2017.

H. Ghaleb, M. El-Shennawy, C. Carta, and F. Ellinger, “A 148-GHz Regenerative Sampling

Oscillator,” accepted for publication in IEEE EuMIC, 2017.

References (I)



X.-Q. Du, A. Knobloch, M. Grözing, M. Buck and M. Berroth, "A DC to 10.1 GHz, 31 dB Gain

Range Control, Digital Programmable Gain Amplifier," IEEE German Microwave Conference

(GeMiC), Bochum, 2016, pp. 144-147.

X.-Q. Du, A. Knobloch, M. Grözing, M. Buck and M. Berroth, "Analysis and Design of a Linear

Digital Programmable Gain Amplifier,“ Frequenz, Degruyter, vol. 71, no. 3, pp. 143-150, Mar. 2017.

M. Grözing, H. Huang, X.-Q. Du and M. Berroth, "Data converters for 100 Gbit/s communication

links and beyond," IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

(SiRF), Austin, TX, 2016, pp. 104-106.

X.-Q. Du, M. Grözing, M. Buck and M. Berroth, "A 40 GS/s 4 bit SiGe BiCMOS Flash ADC," IEEE

Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), to be published.

T. Girg, D. Schrüfer, M. Dietz, A. Hagelauer, D. Kissinger, and R. Weigel, "Low Complexity 60-GHz

Receiver Architecture for Simultaneous Phase and Amplitude Regenerative Sampling Systems" in

International Symposium on Integrated Circuits, Singapur, 2016, pp. 1-4.

T. Girg, C. Beck, M. Dietz, A. Hagelauer, D. Kissinger, and R. Weigel, "A 180 GHz Frequency

Multiplier in a 130 nm SiGe BiCMOS Technology" in 2016 IEEE 14th International NEWCAS

Conference, Vancouver, 2016, pp. 1-4.

D. Kissinger, T. Girg, C. Beck, I. Nasr, H. Forstner, M. Wojnowski, K. Pressel, and R. Weigel,

"Integrated millimeter-wave transceiver concepts and technologies for wireless multi-Gbps

communication" in IEEE MTT-S International Microwave Symposium, Phoenix, AZ, 2015, pp. 1-3.

A. Balteanu, P. Schvan and S. P. Voinigescu, "A 6-bit Segmented DAC Architecture With up to 56-

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and Techniques, vol. 64, no. 3, pp. 881-891, March 2016.

References (II)

Documents

WS-03 | Wireless 100Gb/s and Beyond: Progress in Ultra