WRR ARBITERFinal Presentation

Students: Ofer SobelGuy Marcus

Supervisor: Moshe Porian 26/10/11

AGENDA

• Introduction• Overview• Design• Testing & simulation• SW design• Synthesis• SW & Integration• Documentation• Summary

• WRR algorithm arbitrates between clients, requesting usage of the same resource.

• Arbitration is performed considering priority weights, assigned to each client.

ARBITER

INTRODUCTION

Project goal: Implementing a WRR ARBITER on an FPGA

Requirements:• Generic number of clients (1 to 4)• Communication with host via UART protocol• Real-Time configurable arbitration weights• Interaction with switches and LEDs• 60 MHZ system clock (generated from board’s 50MHz

clock)• Automated and textual test environment• Real time performance report to host

OVERVIEW

RX

TX UART TRANSMITTER

MSG DECODER

FIFOREGISTER

BUSMASTER

MSG ENCODER

FIFO

ARBITER COMPONENT

REQUESTS

GRANTS

FILT

ERS

EXT_CLK

EXT_RST_N

CLK 60

RESET_BLOCK

SYS_CLK

SYS_RST_NCONTROLLER

CRC

CRC

WRR ARBITER

HOST

REG

ISTE

R B

US

GRANT TRACKER

TICK GENERATOR

ARBITER MODULE

COMMUNICATION MODULE

UART RECEIVER

TOP LEVELDESIGN

RX

TX UART TRANSMITTER

MSG DECODER

FIFOREGISTER

BUSMASTER

MSG ENCODER

FIFO

CRC

CRC

HOST

UARTRECEIVER

REG

ISTE

R B

US

Start bit Stop bitData Parity

STARTTYPE

ADDRESSLENGTH

DATACRC

END

TYPE

ADDRESSLENGTH

DATA

COMMUNICATION MODULE

ARBITER MODULE

ARBITER COMPONENT

FILT

ERS

GRANT TRACKER

TICK GENERATOR

REGI

STER

BUS

GRANT 1

GRANT 2

GRANT 3

GRANT 4

REQ 1

REQ 2

REQ 3

REQ 4

REG I/F

HISTORY

MODE

INT REQ

TICK MASK

TICK LEN

WEIGHTS

ENABLE

ARBITER COMPONENT

FILT

ERS

GRANT TRACKER

TICK GENERATOR

REGI

STER

BUS

GRANT 1

GRANT 2

GRANT 3

GRANT 4

REQ 1

REQ 2

REQ 3

REQ 4

REG I/F

HISTORY

MODE

INT REQ

TICK MASK

TICK LEN

WEIGHTS

ENABLE

ARBITER MODULE

ARBITER COMPONENT

FILT

ERS

GRANT TRACKER

TICK GENERATOR

REGI

STER

BUS

GRANT 1

GRANT 2

GRANT 3

GRANT 4

REQ 1

REQ 2

REQ 3

REQ 4

REG I/F

HISTORY

MODE

INT REQ

TICK MASK

TICK LEN

WEIGHTS

ENABLE

ARBITER MODULE

ARBITRATION FLOWCHART

No grant

Arbiter enable

noyes

Grant requesting client with lowest ID

Client/s requesting

Keep granting

same client

Other client/s

requesting ?

Time’sup!

Grant Next* requesting

client

Granted client stopped

requestingOther

client/s requesting

?

no

yes

Next* = lowest ID higher than current (up-to clients-num), otherwise lowest ID

ARBITRATION STATE-MACHINE (3 CLIENTS)

None

1

2 3

P1

P3P2

P1 P2

P3

P1

P2P3 P3 P1

P2

ARBITRATION EXAMPLE(3 CLIENTS)

1

2 3

0

No grant

Arbiter enable

noyes

Grant requesting client with lowest ID

Client/s requesting

Keep granting

same client

Other client/s

requesting ?

Time’sup!

Grant Next* requesting

client

Granted client stopped

requesting Other client/s

requesting ?

no

yes 321

ARBITRATION EXAMPLE(3 CLIENTS)

1

2 3

0

No grant

Arbiter enable

noyes

Grant requesting client with lowest ID

Client/s requesting

Keep granting

same client

Other client/s

requesting ?

Time’sup!

Grant Next* requesting

client

Granted client stopped

requesting Other client/s

requesting ?

no

yes 321

ARBITRATION EXAMPLE(3 CLIENTS)

1

2 3

0

No grant

Arbiter enable

noyes

Grant requesting client with lowest ID

Client/s requesting

Keep granting

same client

Other client/s

requesting ?

Time’sup!

Grant Next* requesting

client

Granted client stopped

requesting Other client/s

requesting ?

no

yes 321

ARBITRATION EXAMPLE(3 CLIENTS)

1

2 3

0

No grant

Arbiter enable

noyes

Grant requesting client with lowest ID

Client/s requesting

Keep granting

same client

Other client/s

requesting ?

Time’sup!

Grant Next* requesting

client

Granted client stopped

requesting Other client/s

requesting ?

no

yes 321

ARBITRATION EXAMPLE(3 CLIENTS)

1

2 3

0

No grant

Arbiter enable

noyes

Grant requesting client with lowest ID

Client/s requesting

Keep granting

same client

Other client/s

requesting ?

Time’sup!

Grant Next* requesting

client

Granted client stopped

requesting Other client/s

requesting ?

no

yes 321

TESTING & SIMULATION

Simulation environment characteristics:• Mentor Graphics Modelsim 6.3C• Automated testing –

– Textual input files– Test logs– Batches of tests

• Arbitration golden model reference• Test-benches fitted for specific modules –

– Communication module TB– Peripherals TB– Arbiter module TB– Top TB

COMMUNICATION MODULE TESTING

REG

ISTE

R B

US

TESTINPUTFILE

CONTROLLERREGISTERS

MODEL

COMMUNICATION MODULE

ARBITERREGISTERS

MODEL

UART TXMODEL

UART RXMODEL

PARSER

TESTLOGFILE

ERRORSIG

LOGGER

RX

TX

ERRORS

TICK REQ, CTRL REQ

1. Messages types test

WR MSGRD MSG

RPLY

RPLYWR MSGRD MSGCTRL RD REQARB RD REQ

MSG

MSG

COMMUNICATION MODULE TESTING

REG

ISTE

R B

US

TESTINPUTFILE

CONTROLLERREGISTERS

MODEL

COMMUNICATION MODULE

ARBITERREGISTERS

MODEL

UART TXMODEL

UART RXMODEL

PARSER

TESTLOGFILE

ERRORSIG

LOGGER

RX

TX

ERRORS

TICK REQ, CTRL REQ

1. Messages types test2. UART errors test

Invalid WR MSG

RX ERRX

RD MSG

RPLY(unchanged)

Invalid RD MSG

RX ERR

XX

COMMUNICATION MODULE TESTING

REG

ISTE

R B

US

TESTINPUTFILE

CONTROLLERREGISTERS

MODEL

COMMUNICATION MODULE

ARBITERREGISTERS

MODEL

UART TXMODEL

UART RXMODEL

PARSER

TESTLOGFILE

ERRORSIG

LOGGER

RX

TX

ERRORS

TICK REQ, CTRL REQ

1. Messages types test2. UART errors test3. Message errors test

DEC ERRX

Invalid MSG

START byteTYPE byteCRC byteEND byte

X

Invalid MSG

ADDRES byte (write permission)ADDRESS byte (false CS)LENGTH byte (write permission)

RBM ERRXX

PERIPHERALS TB

TESTINPUTFILE

CLOCK 60

PARSER

TESTLOGFILE

SYS CLOCKMODEL

RST BLOCK

EXT CLOCKMODEL

LOCK

EXT RST high

SYS RST low

50 MHz

60 MHz

SYNC

60 MHzLOCK

SYS RST high

INT RST(low pulse)

SYS RST(low pulse)

EXT RST lowEXT RST high

SYS RST lowSYS RST high

ARBITER MODULE TB

REG

ISTE

R B

US

TESTINPUTFILE

REGISTERSMODEL

ARBITER MODULE

GOLDENMODEL

REQUESTGENERATOR

PARSER

TESTLOGFILE

LOGGER

REQUESTS

ARBITRATION ERROR

TICKREQ

GRNTS

1. Reset & Registers test

RESET

Read (“00”)

Write random values

Read back

Read RO registers

Write (“FF”)

Read back

RESET

Read (“00”)

ARBITER MODULE TB

REG

ISTE

R B

US

TESTINPUTFILE

REGISTERSMODEL

ARBITER MODULE

GOLDENMODEL

REQUESTGENERATOR

PARSER

TESTLOGFILE

LOGGER

REQUESTS

ARBITRATION ERROR

TICKREQ

GRNTS

1. Reset & Registers test2. Arbiter steady state test

Specific weightsRequest

all

Request all

Request all

Specific weightsSpecific weights

Random TICK len

Random TICK lenRandom TICK len

Arbiter enable

Arbiter enableArbiter enable

GRANTSGRANTSGRANTS

GRANTS compare

Process repeats for all requests combinations

and various weights

Read history

ARBITER MODULE TB

REG

ISTE

R B

US

TESTINPUTFILE

REGISTERSMODEL

ARBITER MODULE

GOLDENMODEL

REQUESTGENERATOR

PARSER

TESTLOGFILE

LOGGER

REQUESTS

ARBITRATION ERROR

TICKREQ

GRNTS

1. Reset & Registers test2. Arbiter steady state test3. Dynamic arbitration test

Specific weights

Set requests

Set requests

Set requests

Specific weightsSpecific weights

Set TICK len

Set TICK len

Set TICK len

Arbiter enable

Arbiter enableArbiter enable

GRANTSGRANTSGRANTS

Read history

Change requests

Change requests

Change requests

Process repeats for various request vectors, for the following weights: all

‘0’, all equal (>0), unequal

ARBITER MODULE TB

REG

ISTE

R B

US

TESTINPUTFILE

REGISTERSMODEL

ARBITER MODULE

GOLDENMODEL

REQUESTGENERATOR

PARSER

TESTLOGFILE

LOGGER

REQUESTS

ARBITRATION ERROR

TICKREQ

GRNTS

1. Reset & Registers test2. Arbiter steady state test3. Dynamic arbitration test4. Filter test

Random weightsRequests

“00”

Random weights

Set TICK len

Set TICK len

Arbiter enable

Arbiter enable

GRANTSGRANTS

filter_depth_g = 5De-met_enable_g = ‘true’

Req pulse 1 cycle

X

Req pulse 2 cycles

X

Repeat process up to a pulse of 5 clock cycles

Req pulse 6 cycles

Requests all

Req low pulse 1 cyReq low

pulse 2 cy

GRANTS unchangedGRANTS

unchanged

Process is symetric to the 1st part of the test…

ARBITER MODULE TB

REG

ISTE

R B

US

TESTINPUTFILE

REGISTERSMODEL

ARBITER MODULE

GOLDENMODEL

REQUESTGENERATOR

PARSER

TESTLOGFILE

LOGGER

REQUESTS

ARBITRATION ERROR

TICKREQ

GRNTS

1. Reset & Registers test2. Arbiter steady state test3. Dynamic arbitration test4. Filter test

5. Configuration switch test

Set TICK len

Arbiter enable

Requests all

Set weights

Arbiter enableArbiter enable

Set TICK len

Set TICK lenSet

weightsSet

weights

GRANTSGRANTSGRANTS

Requests all

Requests all

Change weights

ChangeweightsChangeweightsRead

historyRead

history

GRANTS update

GRANTS update

GRANTS update

Repeat for various weights

ARBITER MODULE TB

REG

ISTE

R B

US

TESTINPUTFILE

REGISTERSMODEL

ARBITER MODULE

GOLDENMODEL

REQUESTGENERATOR

PARSER

TESTLOGFILE

LOGGER

REQUESTS

ARBITRATION ERROR

TICKREQ

GRNTS

1. Reset & Registers test2. Arbiter steady state test3. Dynamic arbitration test4. Filter test

5. Configuration switch test6. Random arbitration test

Set random TICK lenArbiter enable

Randomize requests

Set random weights

Arbiter enableArbiter enable

Set random TICK len

Set random TICK len

Set random weights

Set random weights

GRANTSGRANTSGRANTS

Repeat for 15 iterations of random weights

TOP TB

1. Top messages test

WRR ARBITER TOP

GOLDENMODEL

REQUESTGENERATOR

LOGGER

REQUESTS

GRNTSTESTINPUTFILE

UART TXMODEL

UART RXMODEL

PARSER

TESTLOGFILE

RSETHS

StatusRead CTRL

REGS

RPLYConfigure ARB REGSRead ARB

REGS

RPLYConfigure

golden modelAdjust TICK

Enable Arbiter

Request all

Request all

Request all

TICK messages

TOP TB

1. Top messages test2. Top error test

WRR ARBITER TOP

GOLDENMODEL

REQUESTGENERATOR

LOGGER

REQUESTS

GRNTSTESTINPUTFILE

UART TXMODEL

UART RXMODEL

PARSER

TESTLOGFILE

RSETHS

StatusWR MSG with

parity err

Status (RX err)RX error messageRead CTRL

statusClear errorsRead status

Status (no err)WR MSG with

start byte err

DEC error messageClear

errorsWR MSG with addr byte err

Clear errors

RBM error messageMask

errors

WR MSG with parity err

No error message is to be received

unMask errorsRead status

Status (RX error)

TOP TB

1. Top messages test2. Top error test3. Top reset test

WRR ARBITER TOP

GOLDENMODEL

REQUESTGENERATOR

LOGGER

REQUESTS

GRNTSTESTINPUTFILE

UART TXMODEL

UART RXMODEL

PARSER

TESTLOGFILE

RSETHS

StatusWR MSG to

Arbiter moduleInternal

resetHS

StatusRD REG from

Arbiter module

RPLY (“00”)

TOP TB

1. Top messages test2. Top error test3. Top reset test4. Top Golden model test

WRR ARBITER TOP

GOLDENMODEL

REQUESTGENERATOR

LOGGER

REQUESTS

GRNTSTESTINPUTFILE

UART TXMODEL

UART RXMODEL

PARSER

TESTLOGFILE

RSETHS

Status

Set TICK lengthSet TICK lengthSet weightsSet weightsEnable ArbiterRequest all

Request allRequest all

Enable TICK messages

TICK messagesRandomize

requests

GrantsGrantsGrants

SYNTHESIS RESULTS

• Synthesis successful with clock at 60Mhz.

SYNTHESIS RESULTS

• No timing violations.

Type Slack Required Time Actual Time Failed Paths

Worst-case tsu N/A None 6.874 ns 0

Worst-case tco N/A None 7.025 ns 0

Worst-case th N/A None -1.685 ns 0

Clock Setup: 'clock_60:\sim_clk_gen_false:u_clock_60|pll:pll_inst|altpll:altpll_component|_clk0' 2.103 ns

60.00 MHz( period = 16.666 ns )

68.67 MHz ( period = 14.563 ns ) 0

Clock Setup: 'ext_clk' 18.927 ns50.00 MHz

( period = 20.000 ns )Restricted to 420.17 MHz

( period = 2.380 ns ) 0

Clock Hold: 'clock_60:\sim_clk_gen_false:u_clock_60|pll:pll_inst|altpll:altpll_component|_clk0' 0.391 ns

60.00 MHz( period = 16.666 ns ) N/A 0

Clock Hold: 'ext_clk' 0.391 ns50.00 MHz

( period = 20.000 ns ) N/A 0Total number of failed paths       0

SW & INTEGRATION

GENERIC WRR ARBITER CODE GENERATION

• The Arbiter component RTL code can be generated for any number of clients using the shared resource (integer 2 to ∞).

• Code is generated using a matlab GUI.

DOCUMENTATION

• Version control using the faculty SVN server• Design documents:

– Specification document– Test plan document– HW/ SW interface document

SUMMARY

• Deviation from preliminary specifications:– Generality of client number– Generality of UART bit number

• Referenced blocks: – uart_receiver (from RunLen project)– reset_block sub-blocks (from RunLen project)– crc_generator (from www.ElectronicDesignworks.com)– pll (Altera MegaFunction)

SUMMARY (cont’d)

• Project highlights:– Full system design (VHDL, Verification, Synthesis, SW and

integration)– Autonomous component (and not “just a core”)– Very easy integration thanks to a thorough verification

phase– Coding guidelines – synthesis oriented, flexibility oriented,

well documented