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SoCKET Project Workshop
October 15, 2010 Grenoble, L. Maillet-Contoz (ST), E.Vaumorin (MDS)
SocKET design flow and
Application on industrial use cases
Agenda
Motivations
SoCKET Co-Design flow
SoCKET platform assembly flow
Conclusion
Introduction to industrial case studies
Design flow for critical embedded system
Requ
irement
s
SW
MemoryMap
Certificat
ion pr
ocess
Qua
lifica
tion
pro
cess
Requ
irement
s
System = hardware + software
Certificat
ion pr
ocess
Qua
lifica
tion
pro
cess
Real timeconstraints
Critical embedded system
Objectives
Define a “seamless” development flow, integrating the equipment qualification/certification, from the system level, to the IC and validated SW on these ICs;
Master the SoC solutions for critical embedded systems;
Master the “system dimension” (software + hardware) into the SoCs integration problematics;
Master the complexity, the time cycle reduction, design optimisation of SoC-based systems;
Evaluate the HW simulation models (get from the design flow) usage for the integration and the validation of the critical embedded SWs.
SocKET key technological axis
Ensure requirement traceabilityRefine and map requirements to architectural blocks along the design flow
Adopt and extend IP-Xact for the
Adopt a Hardware/Software Co-Design approachAssistance to system architecture definition
Concurrent hardware and software development
Automation of code generation and validation
Adopt and extend IP-Xact for the integration of various contents
Virtual Prototyping of critical embedded systems
“Seamless” design flow
Formalisms unification
Remove any semantic holes into HW/SW interfaces
Models transformation operators
Automation
Co-design processClassical processSystem Specifications
HW/SWPartitioning
HW Design SW Design
HW Design SW Design
HW/SWPartitioning
System Specifications
Executable Specification(system level simulation)
Alternate architecturesexploration
Automation
Traceability
Overall coherency insurance
Tools interoperability
Keystone of 2 previous points
HW Simulation
HW Synthesis(netlist)
Unit Tests
Equipment Tests
SW Simulation
SW Compilation(code binaire)
Modules Unit Tests
SW Validation Tests
HW/SW Integration
HW Synthesis(netlist)
Unit Tests
Equipment Tests
SW Compilation(binary code)
Modules Unit Tests
SW Validation Tests
HW/SW Integration
HW Design
HW Simulation
SW Design
SW Simulation
HW/SWco-simulation
TO
Agenda
Motivations
SoCKET Co-Design flow
SoCKET platform assembly flow
Conclusion
Introduction to industrial case studies
SoCKET Co-Design flow
Global SoC spec.
SoCArchitecture
System requirements
MetricsHLS
System Properties
Trafficgenerators
Metrics
Requirement traceability
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set
Simulator
Platform assembly
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
IP-XactSoC
Header generation
RTL SoftwareRequirement traceability
Requirements in critical embedded systems
A requirement based development process (mandatory in certification/qualification frame)
Example: A video processing must operate 30 frames per second
Requirements are expressedAt the system level
Are allocated and refined when the system definition is refined
Hw platform requirements and then in sub systems
SW application requirements and then in Sw architecture
SoCKET flow must provide requirement traceabilityEnsure a stepwise consistency between requirements and implementation
Requirements in critical embedded systems
Global SoC spec.
SoCArchitecture
System requirements
Metrics
HLS Trafficgenerators
Metrics
REQsREQs REQs
After HW/SWpartitioning,
System implementation (HW+SW integration)
Soft IPs and HW platform models
SW IPs and
application code
C/C++/ASM
HW Platform assembly IP-XactSoC
SW Header generation
SystemC, VHDL, Verilog
REQs REQsREQs
REQs
partitioning,
IP-XACT is used as a backbone for Reqstraceability
Requirement traceability
How to support req traceability in the flowIntegrate existing tools for Requirement import and traceability (eg. Reqtify): checks and verification
Benefit from IP-XACT centric representation of HW platform to handle HW and HDS layers (Hardware Dependant Software) requirements
Envisage another XML schema for SW application structureEnvisage another XML schema for SW application structure
Ip-Xact is not targeting initially req traceabilityDedicated to description of hardware structure
IP exchange and integration
Link with IP-Xact Define vendor extensions (tag IP-XACT elements with requirements descriptions)
Propagate requirements in models & software from centric representation in XML meta-models
Generation of HDS layers
Header files
Structure and Functions
Parts of drivers
Content management with IP-Xact
IP/SoCFunctional
Specification
C/C++/ASM/…
TLMLT Software
IP-XactSoC
Generation of
TLM model skeleton
Top netlist for virtual platform
Hardware platform documentation
TLMLT
TLMAT
Software
Software
Silicon Software
RTL Software
Consistency vs. heterogeneity
Various formalisms (architectures, timing, functionality, power, …)
Various levels of abstraction and languages
Implementation in hardware and software
SoC Architecture definition
Global SoC spec.
SoCArchitecture
System requirements
MetricsHLS
System Properties
Trafficgenerators
Metrics
Requirement traceability
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set
Simulator
Platform assembly
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
IP-XactSoC
Header generation
RTL SoftwareRequirement traceability
SoC Architecture definition
Define the appropriate partitioning between hardware and software
Conform with system requirements
An architect-driven decision processguided by metrics Global SoC spec.
System requirements
System Propertiesguided by metrics
High Level Synthesis
Provides IP internal information
IP Traffic Generators
Assess bandwidth and latency scenarios
Resulting architecture is described in the IP-Xact formatRefined requirements are associated to the architecture
Global SoC spec.
SoCArchitecture
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set
Simulator
Platform assembly
MetricsHLS
Properties
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
Trafficgenerators
Metrics
IP-XactSoC
Header generation
RTL Software
Requirement traceability
Academic tool
Public Domain (CECILL-B License)
Open source and free
Dedicated to DSP applications
Data-dominated algorithm
Control and Data oriented applicationswill be handle in future release
High Level Synthesis: GAUT
Global SoC spec.
System requirements
System Propertieswill be handle in future release
Inputs :
Algorithm written in bit-accurate C/C++Bit-accurate integer and fixed-point from Mentor Graphics
Synthesis constraints (data average throughput, clock, I/O constraints…)
Outputs :
RTL Architecture written in VHDL (IEEE 1076)
Simulation model in SystemC
Automated Test-bench generation
Global SoC spec.
SoCArchitecture
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set
Simulator
Platform assembly
MetricsHLS
Properties
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
Trafficgenerators
Metrics
IP-XactSoC
Header generation
RTL Software
Requirement traceability
Traffic Generators
ObjectiveAnalyze interconnect bandwidth and latency
MeansGlobal SoC spec.
System requirements
System Properties
For each IP, characterize traffic profile
Assemble a platform with a BCA/RTL interconnect and memory models
Generate traffic
Exploit results with analysis tools
Global SoC spec.
SoCArchitecture
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set
Simulator
Platform assembly
MetricsHLS
Properties
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
Trafficgenerators
Metrics
IP-XactSoC
Header generation
RTL Software
Requirement traceability
Transaction Level models (LT)
Global SoC spec.
SoCArchitecture
System requirements
MetricsHLS
System Properties
Trafficgenerators
Metrics
Requirement traceability
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set
Simulator
Platform assembly
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
IP-XactSoC
Header generation
RTL SoftwareRequirement traceability
Transaction Level models (LT)
Model IPs/subsystems at the transaction levelBit true behavior & communication
System synchronization points
No clock/cycle, but functional timing (e.g. timer)Fast to implement and simulate
18
TLM LT models often built usingC reference model
TLM wrapper Model registers
serve read/write accesses
Used for Embedded software development
Functional verification activities for RTL IPs
Global SoC spec.
SoCArchitecture
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set Simulator
System requirements
Platform assembly
MetricsHLS
System Properties
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
Trafficgenerators
Metrics
IP-XactSoC
Header generation
RTL Software
Requirement traceability
Validation of LT models
The TLM LT model is the golden reference
Functional test suite is built using the LT model
TLM LT testbench is used to validate the RTL IP
High level of confidence for reusing the model
Global SoC spec.
SoCArchitecture
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set Simulator
System requirements
Platform assembly
MetricsHLS
System Properties
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
Trafficgenerators
Metrics
IP-XactSoC
Header generation
RTL Software
Requirement traceability
Transaction Level Models (AT)
Global SoC spec.
SoCArchitecture
System requirements
MetricsHLS
System Properties
Trafficgenerators
Metrics
Requirement traceability
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set
Simulator
Platform assembly
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
IP-XactSoC
Header generation
RTL SoftwareRequirement traceability
Transaction Level Models (AT)
Targeting performance evaluationHardware architecture
Software
Captures micro-architecture information/timing
Timing accuracy may be trimmed
Global SoC spec.
SoCArchitecture
System requirements
Metrics
HLS
System Properties
Trafficgenerators
Metrics
21
Timing accuracy may be trimmed
Several technical optionsLT Model refinement -> rewriting
LT Model annotation
Composition of LT and T models
Generation of a CA model from RTL
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set Simulator
Platform assembly
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
IP-XactSoC
Header generation
RTL Software
Requirement traceability
Validation of AT models
Functionality of AT models can be assessed with the LT tests
Building the temporal model is difficultExtract timing information from the RTL
Implement the micro-architecture model
Global SoC spec.
SoCArchitecture
System requirements
Metrics
HLS
System Properties
Trafficgenerators
Metrics
Implement the micro-architecture model
Statistical approach
And impacts significantly the simulation speed
The hard topic is the temporal validationReuse of Implementation Verification Patterns when available
As difficult as the validation of cycle accurate models
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set Simulator
Platform assembly
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
IP-XactSoC
Header generation
RTL Software
Requirement traceability
Comparing abstraction levels
TLM LT
Same functional behavior
Same functional TLM AT
RTL
Same timedbehavior
Same functional behavior
RTL Level
Global SoC spec.
SoCArchitecture
System requirements
MetricsHLS
System Properties
Trafficgenerators
Metrics
Requirement traceability
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set
Simulator
Platform assembly
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
IP-XactSoC
Header generation
RTL SoftwareRequirement traceability
RTL level
Entry point for logic synthesis flow
RTL models might be Implemented manually
Generated from higher description (HLS flow)Global SoC spec.
System requirements
System Properties
Co-simulationJoint simulation of SystemC/TLM and VHDL/Verilog models
Co-emulation
Simulation of SystemC with the execution of VHDL/Verilog models mapped on a hardware emulators
SoCArchitecture
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set
Simulator
Platform assembly
MetricsHLS
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
Trafficgenerators
Metrics
IP-XactSoC
Header generation
RTL Software
Requirement traceability
Verification concern
Reqs
Each model is a golden model for his level of abstraction
Verification at a lower level extends the validation capacities
Verification flow is connected to requirement management
Requirement update impacts all relevant models
IP-Xact
TLMLT
TLMAT
RTL
Performance verification
Functional verification
Implementation verification
Reqs
Reqs
Reqs
Verification means
Conformance of IP-Xact descriptionsWith the IP-Xact schema
With the models (correct-by-construction)
Validation of the modelsValidation of the modelsDevelopment of test suites reused on the RTL IPs
SystemC simulations
Formal or semi-formal verification techniques
Expressing properties
Global SoC spec.
SoCArchitecture
System requirements
MetricsHLS
System Properties
Trafficgenerators
Metrics
Requirement traceability
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set
Simulator
Platform assembly
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
IP-XactSoC
Header generation
RTL SoftwareRequirement traceability
Hardware and software properties
Properties: verifiable features of functional or timed behavior of a system
Can be refined as hardware or software properties
Verification of Hardware propertiesISIS / Horus
SystemC or RTL monitors to check PSL assertions
Software propertiesWCET analysis with Otawa
Global SoC spec.
SoCArchitecture
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set
Simulator
System requirements
Platform assembly
MetricsHLS
System Properties
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
Trafficgenerators
Metrics
IP-XactSoC
Header generation
RTL Software
Requirement traceability
Agenda
Motivations
SoCKET Co-Design flow
SoCKET platform assembly flow
Conclusion
Introduction to industrial case studies
Architecture
SpecificationsFunctional
Specifications
Performance Analysis
HW/SW mapping & partitioning
Application Architecture
Platform Architecture
High-level description
Verification &
D1 D2
Platform assembly in the global flow
System assembly is part of 3 main steps in the global flow:
Specifications
Architecture exploration
Implementation
In SoCKet, assembly is Architecture Exploration
Implementation
SystemSpecifications
Models
Platform TLM LT + SW Assembly
Verification & validation
D4 D3
Platform TLM AT + SW Assembly
Platform RTL + SW Assembly
Verification & validation
Verification & validation
Verification & Validation plan
• IP-XACT description
• Code (netlist, HAL, makefile)
• Documentation
D5
In SoCKet, assembly is targeting:
Setting up TLM virtual platforms for verification, validation, perf. analysis
HW+SW integration
Implementation
By delivering:
Simulatable specifications
Models
Documentation
SoCKET platform assembly flow
The SoCKet platform assembly flow is made of 3 steps:
P0: Set-up environment (using IP-XACT)
IP selection, instanciation, parametrization in the HW platform description
P1: HW platform description in IP-XACTP1: HW platform description in IP-XACT
Description on the connections between components of the HW platform
Configuration and parametrization of the whole HW platform
P2: HW platform verification and SW integration
Generation (from IP-XACT) of the files required for the verification/validation of the platform (with or without integrated SW)
Integration of SW on HW platform (once the HW platform is validated)
SoCKET platform assembly flow
SoCKET platform assembly flow
The SoCKet platform assembly flow is made of 3 steps:
P0: Set-up environment (using IP-XACT)
IP selection, instanciation, parameterization in the HW platform description
P1: HW platform description in IP-XACT
Description on the connections between components of the HW platform
Configuration and parameterization of the whole HW platform
P2: HW platform verification and SW integration
Generation (from IP-XACT) of the files required for the verification/validation of the platform (with or without integrated SW)
Integration of SW on HW platform (once the HW platform is validated)
SoC Configuration Reporting
IP Flow
HW Platform specifications
IP sub-project export IP configuration & connection
Set-up Environment
HW Platform instantiation
Project
IP library
Specification XML
SoC status
IP selection
Adaptor insertion
P1HW Platform DescriptionP0
Set-up Environment
SoC Configuration ReportingIP sub-project import
Code generation
Project
updaterejected
Testbench assemblyIP library
Integration test
• Netlist• Bill of Material
• Integration test• HAL
Checkerslegacy
Validation plan
SoC status
TestBench statusTestBench Configuration Reporting
P2HW Platform Verification
Test results
HAL generation + SW mapping
Goal:Deliver in a work space, all IPsrequired for beginning the assemblyprocess, taking in accountdependencies, versions, accessibility,and other criteria (e.g. qualificationlevel)
Tools:�Tlm_infra� Magillem Platform Assembly
To be handled in IP-XACTextensions:
� Attributes on components for Selection criteria's
SoCKET platform assembly flow
The SoCKet platform assembly flow is made of 3 steps:
P0: Set-up environment (using IP-XACT)
IP selection, instanciation, parameterization in the HW platform description
P1: HW platform description in IP-XACT
Description on the connections between components of the HW platform
Configuration and parameterization of the whole HW platform
P2: HW platform verification and SW integration
Generation (from IP-XACT) of the files required for the verification/validation of the platform (with or without integrated SW)
Integration of SW on HW platform (once the HW platform is validated)
Architecture
SpecificationsFunctional
Specifications
Performance Analysis
HW/SW mapping & partitioning
Application Architecture
Platform Architecture
High-level description
Verification &
D1 D2
HW platform description in IP-XACT
Goals:IP-XACT description of the
whole HW platform (TLM orRTL)Generation of documentation
and configuration status Architecture Exploration
Implementation
SystemSpecifications
Models
Platform TLM LT + SW Assembly
Verification & validation
D4 D3
Platform TLM AT + SW Assembly
Platform RTL + SW Assembly
Verification & validation
Verification & validation
Verification & Validation plan
• IP-XACT description
• Code (netlist, HAL, makefile)
• Documentation
D5
and configuration status
SoC Configuration Reporting
IP Flow
HW Platform specifications
IP sub-project export IP configuration & connection
Set-up Environment
HW Platform instantiation
Project
IP library
Specification XML
SoC status
IP selection
Adaptor insertion
P1HW Platform DescriptionP0
HW platform description
SoC Configuration ReportingIP sub-project import
Code generation
Project
updaterejected
TestBench assemblyIP library
Integration test
• Netlist• Bill of Material
• Integration test• HAL
Checkerslegacy
Validation plan
SoC status
TestBench statusTestBench Configuration Reporting
P2HW Platform Verification
Test results
HAL generation + SW mapping
Tools:� Magillem Platform Assembly� Magillem Generator Studio
To be handled in IP-XACT extensions:� Complete configuration status of the platform for requirement traceability and verification tools
SoCKET platform assembly flow
The SoCKet platform assembly flow is made of 3 steps:
P0: Set-up environment (using IP-XACT)
IP selection, instantiation, parameterization in the HW platform description
P1: HW platform description in IP-XACT
Description on the connections between components of the HW platform
Configuration and parameterization of the whole HW platform
P2: HW platform verification and SW integration
Generation (from IP-XACT) of the files required for the verification/validation of the platform (with or without integrated SW)
Integration of SW on HW platform (once the HW platform is validated)
Architecture
SpecificationsFunctional
Specifications
Performance Analysis
HW/SW mapping & partitioning
Application Architecture
Platform Architecture
High-level description
Verification &
D1 D2
HW platform verification and SW integration
Goals: Setting up the tests to be
performedVerify the consistency of the
HW platform descriptionCheck conformity with Architecture
Exploration
Implementation
SystemSpecifications
Models
Platform TLM LT + SW Assembly
Verification & validation
D4 D3
Platform TLM AT + SW Assembly
Platform RTL + SW Assembly
Verification & validation
Verification & validation
Verification & Validation plan
• IP-XACT description
• Code (netlist, HAL, makefile)
• Documentation
D5
Check conformity with requirementsHW+SW integration
SoC Configuration Reporting
IP Flow
HW Platform specifications
IP sub-project export IP configuration & connection
Set-up Environment
HW Platform instantiation
Project
IP library
Specification XML
SoC status
IP selection
Adaptor insertion
P1HW Platform DescriptionP0
HW platform verification and SW integration
Tools:� Magillem Platform Assembly� Magillem Generator Studio� HORUS� ISIS� Simulation tools� Reqtify
To be linked with Verification Environments (E.g.. SoC Configuration ReportingIP sub-project import
Code generation
Project
updaterejected
Testbench assemblyIP library
Integration test
• Netlist• Bill of Material
• Integration test• HAL
Checkerslegacy
Validation plan
SoC status
Testbench statusTestbench Configuration Reporting
P2HW Platform Verification
Test results
HAL generation + SW mapping
Environments (E.g.. VM+Japser+Questa)
Agenda
Motivations
SoCKET Co-Design flow
SoCKET platform assembly flow
Conclusion
Introduction to industrial case studies
Conclusion
SoCKET Co-Design flow has been consolidated amongst the partners
Requirement traceability
Virtual prototyping using SystemC
It is built on top of standardsIP-Xact: IEEE 1685
SystemC: IEEE 1666
Instrumentation of the flow is in progress
Industrial case studies are going to exercise the SoCKET flow
Agenda
Motivations
SoCKET Co-Design flow
SoCKET platform assembly flow
Conclusion
Introduction to industrial case studies
Application to industrial case studies: Airbus
Traceability based on IP-Xact format – Case of avionics domain
Global SoC spec.
SoCArchitecture
System requirements
MetricsHLS
System Properties
Trafficgenerators
Metrics
Requirement traceability
Architecture
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set
Simulator
Platform assembly
HLS
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
generators
IP-XactSoC
Header generation
RTL Software
Requirement traceability
Application to industrial case studies: Astrium
Separation of time and functionality in timed TLM modelling
Time modelling of a transactional memory controller
Gaut usage feedback
Global SoC spec.
System requirements
System Properties
Requirement traceability
SoCArchitecture
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set
Simulator
Platform assembly
MetricsHLS
Properties
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
Trafficgenerators
Metrics
IP-XactSoC
Header generation
RTL Software
Requirement traceability
Application to industrial case studies: CNES
Modélisation SystemC d’un contrôleur mémoire durci
Global SoC spec.
SoCArchitecture
System requirements
MetricsHLS
System Properties
Trafficgenerators
Metrics
Requirement traceability
Architecture
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set
Simulator
Platform assembly
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
generators
IP-XactSoC
Header generation
RTL Software
Requirement traceability
Application to industrial case studies: Thales
Exploration and mapping of application on System on Chip: IP-Xact description flow
Exploration and mapping of application on System on Chip: fast prototyping
Global SoC spec.
System requirements
System Properties
Requirement traceability
SoCArchitecture
Functional validation
SW Performance validation
C/C++/ASM
Functionality
Functionality+
timing
Instruction Set
Simulator
Platform assembly
MetricsHLS
Properties
HW Properties
SW Properties
TLMLT
TLMAT
Software
Software
Co-simulation/Co-emulation
Silicon SoftwareDevice execution
HLS
Trafficgenerators
Metrics
IP-XactSoC
Header generation
RTL Software
Requirement traceability