Working With Flipflops

8/14/2019 Working With Flipflops

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shown in Fig. 2. That way high input sig-nals can reach the S -R Hip-Hop only whe nthe cloclc ti) signal is also high. Th ere-fbrc. when CI I; is low, hot11 inputs o f theflin-tfop are held low, irrcspcctive o f [h e. .states of the SET and l i t s ~ rnputs. so thef l ip-f lop funct ions as a 'permanent"nlemory. However, when ( -LX is high, thecircuit functions as n standard S--R Hip-flop. Conseq~~ently,nformation is not au-tomaticailv latched into the H~D-HOD,butFlip-flops are the basis of all digital circuits. Learn must be "I-~ocl


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CLK goes high, the slave flip-flopstate. Note that the output statesge on the arrival of the leading edgeIt takes two clock pulses to change theone state to another and back

as a Toggle (or type-T) flip-

e D flip-flopThe type-T flip-flop is a special devicevider. A

5-(1. In that circuit, ans an d K

of phase, and the input5-0 and5-c show the s y~ nb ol nd the truththe type-D flip-flop, respectively.A type- D flip-flop can be used as a data

latch by connecting it as shown in Fig.6-(1,or as a binary co unter idivid er by con-necting it as shown in Fig. 6-b.The JK flip-flopFigure 7-ti shows the basic circui t of aneven more versat i le c locked f l ip- f lop ,which is universally known as the JK-type. It can function eit her as a data latch,a counteridivider, or as a do -nothing ele-ment by suitably connecting the J and Kterminals. The symbol of the J K flip-flopis shown in Fig. 7-0, and its truth table isshown in Fig. 7-c.In essence , the JK flip-flop firnctions asa T-type when inputs are both high , and asa D-type when they're different. Whenthey're both low, the outputs remain un-changed when a pulse arrives.Real-world devicesThe two best-known clocked CMOSflip-flops are the 4013 D-type and the4027 JK-type. Each 1C contains two inde-pendent flip-flops that share power andground connections. Figure 8-0 shows the

THE DATA OR TYPE -D FLIP-FLOP a is built from a clocke d master-slave flip-flop. Its symbol isb, and its truth table in c.

(a )or as a divide-by-two counter (c )

functional diagram of the 4013; the truthtable of its clocked inp uts is shown in Fig.8-h . and that of its direct inputs is shownin Fig. 8-c . Corresponding diagrams forthe 4027 are shown in Fig. 9-ti, Fig. 9 4 ,and Fig. 9-c.Note that both the 4013 and the 4027have SET an d RESET inputs in addition tothe normal clocked inputs. For both IC's

7-THE JK FLIP-FLOP'S CIRCUIT is shown in a, along with its symbol (b)and action table (c.)

those terminals are direct inputs that en-able the clocked action of the flip-flop tobe overridden, in which case the devicefunctions as a simple unclocked S-R flip-flop. For normal clocked operation, thedirect inputs must be grounded.The 4013 and 4027 are fast-actin g, so itis important that their clock signals beabsolutely noise-free and bounce less, andthat they have risetimes and falltimes ofless than five ps. Both IC's clock on thepositive transition of the clock signal.Ripple countersThe most popular application of theclocked flip-flop is as a binary counter.Fig. 10-0 shows how to connect the 4013as a divide-by-two counter; Fig. 10-hshows the corresponding connections forthe 4027. When clocked by a fixed-fre-quency waveform, both circuits give asymmetrical square-wave output at halfthe clock frequency.As shown in Fig. 11, you can cascadeseveral ripple counters ( so called becauseof the way that cl&k pulses appear toripple from stage to stage) to provide divi -sion by successive powers of two. Figure11-0 shows how to cascade two D-typeflip-flops, and Fig. 11-h shows how tocascade two JK-type flip-flops to provide adivision ratio of 4 (2 x 2 or 2'). In a lik emanner, Fig. 12-a and Fig. 12-0 show howthree stages can be cascaded to give adivision ratio of eight (23). In fact, anarbitrary number of stages can be cas-caded, as shown in Fig. 13, to provide adivision ratio of 211, where rz is the num berof stages.

The circuits shown in Fig. 11-Fig. 13are known as ripple counters, becauseeach stage is clocked by the ou tput of thepreceding stage, rather than by a masterclock signal. The effect, therefore, is thatthe c lock s igna l s eems to " r ipp le"through the counter chain. The problem isthat the propagation delays of all the di-viders add together and provide a delaythat prevents the counter s tages fromclocking synchronously. Counters of thatsort are in fact called asy nchronous cou n-ters. If the outputs of the stages are de-coded via gate networks, output glitchesand inaccurate decoding can result. .Long ripple countersAlthough 4013 and 4027 counters canbe cascaded to give any desired nu mb er ofstages, when more than four stages areneeded, it's usually economical to use aspecial-purpose MSI ripple-carry b~narycounteridivider IC. Our next few figuresshow several examples. LThe 4024 , shown in Fig. 14, is a seven- 2stage ripple counter; all seven outputs are rnexternally accessible. The IC provides a &maximum division ratio of 128 (27). The 2


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FIG. 11-TO DIVIDE FREQUENCY BY FOUR, youcan use a pair of D (a ) r JK (b ) lip-flops.

shown in b and c, respectively.

FIG. 12-TO DIVIDE FREQUENC Y BY EIGHT, yotican use three D (a) r JK (b) lip-flops.

trary factor 2", us e n stages.. . . .i n b and c, respectively.

a 14-stage counter; all outputs except 2and 3 are externally accessible. The 40 20provides a maximum division ratio of16,384 (214).Figure 17-0 shows details of the 406 0.It is another 14-stage device, but outputs1, 2, 3, and I1 are not accessible. A spe-cial feature of the IC is that it incorpora tesa built-in oscillator circuit. As shown inFig. 17-6 and Fig. 17-c, he device can usecan use a D (a) or a JK (b) lip-flop. I you either a crystal or an RC netwo rk to set thefrequency of oscillation. '40 40 , shown in Fig. 15, is a 12-stage de- The 40 20 , 40 24 , 404 0, and 406 0 IC'svice, of which all outpu ts are accessible. all have Schmitt-trigger inputs that triggerIt provides a maximum division ratio of on the negative transition of each input40 96 (21'). The 402 0, sh own in Fig. 16, is pulse. All of those counters can be set to

zero by ap plying a high level to the RESETline.GlitchesA t wo-s t a ge d i v i de -by- four r i pp l ecounter, like that shown in Fig. 18-a, canhave four possible o utput states, as shownin Fig. 18-b. Both ou tputs can be high,both can be low, one can be high and theother low, or the former low and the latterhigh. Before any clock pulses have beenreceived, the Q2 an d QI outputs are low.When the first pulse arriv es, QIgoes high.When the second pulse arrives, 02 goeshigh and QI goes low. On the third pulse,Q? an d QIboth go high. La st, on the fourthpulse, ~ 7 - - nd QI both go low again.


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state, as shown in Fig. 18-c. Because the Up and down counters.ripple counter is an asynchronous dev ice, A standard r ipple counter counts u phowever, the propagation delay between the decoded outpu ts increase in value withthe two flip-flops may cause glitches to each succeeding clock pulse. It is possi-

14--PINOUT OF THE 4024 seven-stage rip-

15-PINOUT OF THE 4040 12-stage ripple

(120~tputs espond to (he input signal as shown in bywhen they're combined as shown inc, a glitchmay be generated, as shown in d.

G. IGP INO UT OF THE 4020 14-stage ripple

Each of the four possible states can beprovide four unique ou tputs byhe outputs that are unique to each

appear in the decoded o utputs, as shownin Fig. 18-d. Of course, those types ofglitches are possib le with any m ulti-stageripple counter, and the greater the numbe rof stages, the gr eater the total propagationdelay becom es, an d the greater the prob-lem with glitches. The solution to theglitch problem is to use a clocked-logicdevice, which we'll discus s momentarily.

ble, however, to build a counter that worksin the opposite direction. That type ofcounter is called a down (or a subtract)counter. The circuit is shown in Fig. 19-a;its truth table is shown in Fig. 19-b.Walking-ring (Johnson) countersRipple counters are useful where un-decoded binary division is needed, but


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FIG. 19--A DOWN-COUNTING RIPPLE COUNTER is shown in a; the truth-table is shown in b.

0 1 SET 02 LOW I 1 CHANGESTAT- - - - - - - - - - - - - - - -1 0 SET 02 HIGH 1 1 CHANGESTAT-- - - - - - - - - - - - - - -

SET 02 LOW 0 1 SET Q l LOW

- . - - - - - . - - --- -FIG. 20--THE SYNCHRONOUS COUNTER eliminates glitches; a divide-by-three circuit is shown in a,and its truth-table in b.

FIG. 21-A SYNCHRONOUS DIVIDE-BY-FOUR CIRCUIT is shown in a; its truth table is shown in b.

(because of glitches) not where decodedoutp uts are required. Fortunately, an alter-native circuit, which is suitable for gener-ating decoded outputs, is available. It isknown as the walking ring or Johnsoncounter. It relies on the "progran~mable"nature of the JK flip-flop. which enables itto act as a SET (or a RESET) latch, as a

binary divider, or as a "do nothing" de-vice. In a walking-ring counter, all flip-flops are clocked simultaneously, so it isalso known as a synchronous counter.Figure 20-0 shows the circuit and Fig.20-b the truth table of a synchronous di-vide-by-three counter. Note that the truthtable shows the state of each flip-flop at

each stage of the counting cycle. Re-member that, when the clock is low, the"instruction" is loaded (via the .I and Kinputs ) into the flip-flop; the instruction iscarried out as the clock goes high.So, at the start of the cycle, ~z and QIare both low, and the "change state" in-struction (JK code 11) is loaded into thefirst flip-flop. Then the instru ction "set 0 2low" (J K cod e 01) is loaded into the firstflip-flop. When the first clock pulse ar-rives. the instruction is carried out, QIgoes high, and ~ 2 stays low.When the clock goes low again, newprogram information is fed to the flip-flops. Flip-flop 1 is instructed to changestate (JK code ll), and flip-flop 2 is in-structed to set 4 2 high (JK c od e 10). Tho seinstructions are executed on the positivetransition of the second clock p ulse, caus-ing ~ 2 to go high and QI to go low. Whenthe clock goes low again, new programinformation is again fed to each flip-flopfrom the output of its partner. The count-ing sequence then repeats a d injniturn.So i n t he wa l k i ng- r i ng or Johnsoncounter, all flip-flops are clocke d in p aral-lel, but are cross-coupled so that the re-sponse of one stage (to a clock pulse)depends on the states of the o ther stages.Walking-ring counters can be config-ured to give any desired count ratio. Forexam ple, Fig. 21-a and Fig. 21-b show thecircuit and truth table respectively of adivide-by-four counter. Figure 22-n andFig. 22-h show the circuit and truth tablerespectively of a divide-by-five coun ter.

The 4018When syn chronous counts greater thanfour are needed, it is usually economicalto use an MSI IC rather then several4027's. A suitable device is a 4018, apresettable divide-by-N counter that canbe made to divide any whole num ber be-tween 2 and 10 by cross-coupling inputand outp ut terminals in various ways. Th atIC incorpora tes a f ive-s tage Johnsoncounter, has a built-in Schmitt trigger inits clock line, and clocks on the positivetransition of the input signal. The counteris said to be presettable because the out-puts can be set to a desired state at anytime by feeding the inverted binary codeto the Jam inputs (11-~5) and then loadingthe data by taking pin 10 high.Figure 23 shows how to connect the4018 to give any whole-number divisionratio between 2 and 10. No additionalcompon ents are needed to obtain an evendivision ratio, but a two-input A N D gate (a4081, for examp le) is required to obtain anodd division ratio.Greater-than-ten divisionEven division ratios greater than tencan ~ ~ s u a l l ye obtained simply by cascad -ing suitably scaled counter stages, asshown in Fig. 24-a-Fig. 24-d. Non-stan-dard and uneven division ratios can be


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Figure 26 shows how to make a four-bitSerial-InISerial-Out (S ISO ) shift register.A bit of binary data applied to the input ispassed to the output of the first flip-flop onthe application of the first clock pulse, tothe output of the second on the secondpulse. to the output of the third on thethird pulse, and .to the fourth (and final)output on the fourth pulse. The circuit canhold four bits of data at any given mo-ment. The $1~0egister is useful for d e-laying binary signals. o r for storing bits ofbinary data and unloading them (in serialform) when reauired.

IG. 22-A SYNCHRONOUS DIVIDE-BY-FIVE CIRCUIT is shown in a; i ts truth table is shown in b. Figure 27 shbws how the previous cir-

FIG. 2 G T O STORE FOUR BITS OF DATA, a ll four inputs are clocked simultaneously.

3--TO OBTAIN AN ODD DIVISION RATIOthe 4018, an externalAND gate must be used.

FIG. 26 FOUR TYPE-D FLIP-FLOPS are cascaded to create a four-bit SISO shif t register.

factor. In a is(2 x 6) circuit, in b a divide-by-36x E), in c a divide-by-50(5 x lo),and ina divide-by-1000(10 x 10 x 10)circuit.

4018. for ex am ~ le ) nd de-to geneiat; suitablepulses when the desired Figure 25 s ho w s h ow t o m ak e a fou r-b it c u i t c a n b e c o n v e r t e d t o a S e -data latch from four D-type flip-flop s. The rial-lnIParalle1-Out (SIPO ) shift registerdata latch is useful for storing binary num- simply by using the Q outpu ts of each flip-and registers bers or data. Input data is ignored until a flop. The circuit might be useful, for ex- 5Now let's move away from cou nter s and positive-going STORE pulse is applied. at ample, in converting data transmittedbrief look at three other applica- which point the latch stores the data and from a remote location in serial form to gmaster-slave flip-flop. outputs it on the Q outputs. the parallel form used by computers. R-E "

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Working With Flipflops