WINLAB Open Cognitive Radio Platform Architecture v1.0

WINLAB Open Cognitive Radio Platform

Architecture v1.0

WINLAB – Rutgers University

Date : July 27th 2009

Authors :

Prasanthi Maddala, [email protected]

Khanh Le, [email protected]

Ivan Seskar, [email protected]

OCRP Architecture 2

SDR Tx

The SDR Tx takes either Control or Data Commands.

These commands are sent as IP packets.

OCRP Architecture 3

SDR Tx Architecture

Wibo SPI

Application Block

Dibo SPI

DAC Interface

wibo_senwibo_sclkwibo_sdatawibo_u2_sen

radio_io5 radio_io6 radio_io7

dibo_sdata

dibo_sclkdibo_sen

tx_sync

tx_data

other outputs

other outputs

RxEthernetInterface

Buffer

SystemController

MemoryControl

Command FIFO

CommandDescriptorGenerator

OCRP Architecture 4

Frame Format Control Frame

Application Code[4:0] Type [2:0]

00000 - DIBO 000 – Sys Control

00001 - WIBO 001 – App Control

00010 - Tx Application 010 – App Data

00011 – Rx Application

Sequence Number : A number given by the user to each frame to keep track of the commands that have been processed and that have been dropped.

OCRP Architecture 5

Data Frame

OCRP Architecture 6

Rx Ethernet Interface

The Rx Ethernet Interface detects an Ethernet frame by looking at the preamble and forwards the Ethernet payload to the next block.

It sends out data as 32 bit words and also sends start of frame, end of frame and data valid signals for the next block to sync up.

OCRP Architecture 7

Rx Ethernet Interface – FPGA Top IF

Signal Name In/Out Width Description

eth_data_valid In 1 Active High. Indicates that the data on eth_data port is valid.

eth_error In 1

eth_data In 8 Ethernet frame data that comes from Ethernet PHY module on the board. For an Ethernet link at 100Mbps only eth_data[3:0] is valid. If it is a 1Gbps link all the 8 bits are valid.

OCRP Architecture 8


Sof Out 1 Start-of-frame signal, indicating first word of payload.

Eof Out 1 End-of-frame signal, indicating last word of payload.

data Out 32 Ethernet payload data

data_valid Out 1 Active High. Indicates that the current data word is valid.

Rx Ethernet Interface – Command Descriptor Generator IF


frame_err Out 1 Active High. Indicates that there is an error in the frame Ex: eth_error signal is high or frame is incomplete – size in the Ethernet header does not match with the actual size.(No gaps are allowed in an Ethernet frame)

Rx Ethernet Interface – Register Map IF

OCRP Architecture 9

Command Descriptor Generator

Command descriptor generator performs the following functions

1. Parses the IP header to see if the destination IP address matches.

2. Generates command descriptors for both the control and data commands and writes them to the command FIFO.

3. Writes the application data to a buffer.

OCRP Architecture 10

Total Length: 16-bitsThis field indicates the size of the datagram, including the header and the data.


Command Descriptor Generator – Memory Control IF


buf_wr_req Out 1 Active high. Signal requesting the memory control for buf_wr_size bytes of space on the buffer to store data.

buf_wr_size Out 16 Size of data to be stored in the buffer(bytes) . It is calculated from the payload length given in the IP header.

buf_wr_ack In 1 Active High. Response to buf_wr_req indicating that the requested space is available at the address buf_wr_ptr. buf_wr_ack is sent as soon as buf_wr_req is detected by the memory control, i.e., the command descriptor generator can send a buffer request and check for buf_wr_ack in the next clock cycle. If buf_wr_ack is not high, it means that the requested buffer space is not available.

buf_wr_ptr In 16 Address at which the data would be written. This address will be inserted in the data command descriptor.

sof Out 1 Start-of-frame for the app data to be stored. The memory control expects an sof (or a buf_wr_cancel) as soon as the buf_wr_req is pulled low. If the buf_wr_req remains low for a clock cycle or more before sending the sof, then the data write operation is ignored.

eof Out 1 End-of-frame for the app data to be stored

buf_wr_data Out 32 App data word to be stored

buf_data_valid Out 1 Active High. Indicates that the data word on buf_wr_data is valid

buf_wr_cancel Out 1 Active High. Command descriptor generator can cancel a data write operation at any time, by setting this signal high. A write operation starts when the buffer request is sent to the memory control and ends when eof is sent.


Command Descriptor Generator – Command FIFO IF


Sof Out 1 Start-of-frame signal, indicating the first word of command descriptor

Eof Out 1 End-of-frame signal, indicating the last(second) word of command descriptor.

cmd_data Out 32 Command descriptor word.

cmd_write Out 1 Active High. Indicates that the current word on cmd_data is valid and acts a write request for the command FIFO.

cmd_full_flag In 1 Active High. Indicates that the command FIFO is full and can not accept any commands



Sof In 1 Start-of-frame signal, indicating first word of payload.

Eof In 1 End-of-frame signal, indicating last word of payload.

data In 32 Ethernet payload data

data_valid In 1 Active High. Indicates that the current data word is valid.

Command Descriptor Generator - Rx Ethernet Interface (As defined in Rx Ethernet Interface – Command Descriptor Generator IF)



buf_full_err Out 1 Active High. Indicates that the buffer is full and no more data can be accepted.

cmd_full_err Out 1 Active High. Indicates that the command fifo is full and no more commands can be accepted.

Sequence_no Out 8 Sequence no of the data frame which was not stored in the buffer due to a buf_full_err, or cmd_full_err, or a frame_length_err.

hdr_err Out 1 Active High. Indicates that there is an error in the IP header – not enough no. of words

ip_addr_err Out 1 Active High. Indicates that the destination IP address in the data frame does not match with the IP address of the board.

frame_length_err Out 1 Active High. Indicates that the frame length calculated from IP payload length does not match with the actual frame length.

In case of a control command, it might indicate that the frame length is not equal to 2 words (8 bytes).

In case of a data command, if the actual frame length is more than the calculated length, only the calculated length no.of words are stored and the rest are discarded. If the actual frame length is less, the write operation is considered incomplete and is canceled.

Command Descriptor Generator – Register Map IF


Memory Control

The Memory Control

1. Keeps track of available buffer space (with the help of write and read ptrs)

2. Sends an ack or nack on receiving a write request from the command descriptor generator.

3. Write ptr is updated as and when data is written to the buffer and is wrapped around once it reaches the end.

4. Read ptr is updated by incrementing the current value by last_app_size whenever the last_app_size_valid is high. When System Control receives app_done for a command it sends out the data size (last_app_size) of the command to the memory control, indicating that the buffer space can be overwritten and the read ptr be updated.


Memory Control - Command Descriptor Generator IF(As defined in Command Descriptor Generator – Memory Control IF)


buf_wr_req In 1 Active high. Signal requesting the memory control for buf_wr_size bytes of space on the buffer to store data.

buf_wr_size In 16 Size of data to be stored in the buffer(bytes) . It is calculated from the payload length given in the IP header.

buf_wr_ack Out 1 Active High. Response to buf_wr_req indicating that the requested space is available at the address buf_wr_ptr. buf_wr_ack is sent as soon as buf_wr_req is detected by the memory control, i.e., the command descriptor generator can send a buffer request and check for buf_wr_ack in the next clock cycle. If buf_wr_ack is not high, it means that the requested buffer space is not available.

buf_wr_ptr Out 16 Address at which the data would be written. This address will be inserted in the data command descriptor.

sof In 1 Start-of-frame for the app data to be stored. The memory control expects an sof (or a buf_wr_cancel) as soon as the buf_wr_req is pulled low. If the buf_wr_req remains low for a clock cycle or more before sending the sof, then the data write operation is ignored.

eof In 1 End-of-frame for the app data to be stored

buf_wr_data In 32 App data word to be stored

buf_data_valid In 1 Active High. Indicates that the data word on buf_wr_data is valid

buf_wr_cancel In 1 Active High. Command descriptor generator can cancel a data write operation at any time, by setting this signal high. A write operation starts when the buffer request is sent to the memory control and ends when eof is sent.


Memory Control – Buffer IF


buf_wr_data Out 32 Data word to be stored in the buffer

buf_write Out 1 Active high.Indicates that the word on buf_wr_data is valid

buf_wr_address Out 12 Address at which the data word has to be written


Memory Control – System Control IF


last_app_size In 16 Size of the last app command (app command that has been processed) in bytes.

last_app_size_valid In 1 Active high. Indicates that the data on last_app_size is valid


System Control


System Control – Command FIFO Interface


Sof In 1 Start-of-frame signal, indicating first word of descriptor.

Eof In 1 End-of-frame signal, indicating last word of descriptor.

Cmd_data In 32 Descriptor data from Command FIFO

Cmd_empty_flag In 1 Command FIFO empty flag. If Cmd_empty_flag /= 1 then Command FIFO has data.

Cmd_read Out 1 Command FIFO read signal. Cmd_read == 1 to fetch next word in queue.


System Control - Memory Control IF


last_app_size Out 16 Size of the last app command (app command that has been processed) in bytes.

last_app_size_valid Out 1 Active high. Indicates that the data on last_app_size is valid


System Control – Tx Application Interface


tx_app_param_valid Out 1 Parameter available sync pulse. Active High for one clock cycle.

tx_app_param_addr Out 8 Register map address field

tx_app_param_data Out 24 Parameter values e.g. register map values.

tx_app_req Out 1 Application processing request signal. Active high. This indicates that data/control frames are available within Buffer. Application shall fetch data/control information using App_type, App_ptr and App_size information.

tx_app_type Out 2 Type of frame within Buffer :

00 – control

01 – data

Others – reserved

tx_app_ptr Out 16 Address pointer to location of data/control frames

tx_app_size Out 16 Size of data/control frames

tx_app_done In 1 Application processing done signal. Indicates that Application block has completed the processing request. System Control may assert a new request. Active High.


System Control – Rx Application Interface


rx_app_param_valid Out 1 Parameter available sync pulse. Active High for one clock cycle.

rx_app_param_addr Out 8 Register map address field

rx_app_param_data Out 24 Parameter values e.g. register map values.

rx_app_req (not used) Out 1 Application processing request signal. Active high. This indicates that data/control frames are available within Buffer. Application shall fetch data/control information using App_type, App_ptr and App_size information.

rx_app_type (not used) Out 2 Type of frame within Buffer :

00 – control

01 – data

Others – reserved

rx_app_ptr (not used) Out 16 Address pointer to location of data/control frames

rx_app_size (not used) Out 16 Size of data/control frames

rx_app_done In 1 Application processing done signal. Indicates that Application block has completed the processing request. System Control may assert a new request. Active High.


System Control – WIBO SPI Interface


Wibo_valid Out 1 WIBO SPI request signal

Wibo_param_addr Out 8 WIBO SPI address field

Wibo_param_data Out 23 WIBO SPI data field

Wibo_done In 1 WIBO SPI done signal. Indicates that the WIBO Spi block has completed processing the command I.e., it has sent out the register data on SPI or has set the antenna switches and is ready to take in the next SPI register data.


System Control – DIBO SPI Interface


Dibo_valid Out 1 DIBO SPI request signal

Dibo_param_addr Out 8 DIBO SPI address field

Dibo_param_data Out 23 DIBO SPI data field

Dibo_done In 1 DIBO SPI done signal. Indicates that the DIBO Spi block has completed processing the command I.e., it has sent out the register data on SPI and is ready to take in the next SPI register data.


W iBoSPI

w ibo_param _addr[7:0 ]

w ibo_valid

w ibo_param _data [23 :0]

w ibo_done

w ibo_sclk

w ibo_sen

w ibo_sdata

rad io_io6

rad io_ io5

rad io_ io7

w ibo_u2_sen

w ibo_spi_clk

SystemC ontro l

In terface

WiBo SPI

Used to configure the RF chip(MAX2829), U2,and antenna switches on wibo.

No Data Commands, 1 Control Command

Number of Parameters = 3 - SPI register,U2, Antenna Switches

SPI register (17 : 0)

SPI reg data [13:0] SPI reg addr[3:0 ]

17 0


WIBO SPI - System Control IF(As defined in System Control – WIBO SPI Interface)


Wibo_valid In 1 WIBO SPI request signal

Wibo_param_addr In 8 WIBO SPI address field

Wibo_param_data In 23 WIBO SPI data field

Wibo_done Out 1 WIBO SPI done signal. Indicates that the WIBO Spi block has completed processing the command I.e., it has sent out the register data on SPI or has set the antenna switches and is ready to take in the next SPI register data.


Dibo SPI

D iBoSPI

dibo_param _addr[7:0 ]

d ibo_valid

d ibo_param _data [23:0]

d ibo_done

dibo_sclk

d ibo_sen

dibo_sdata

dibo_spi_clk

SystemC ontro l

In terface

Used to configure the ADC/DAC chip (AD9860) on dibo.

No Data Commands, 1 Control Command

Number of Parameters = 1 - SPI register

SPI register (15 : 0)

SPI reg data [7:0]SPI reg addr[7 :0]

15 0


DiBo SPI - System Control IF(As defined in System Control – DIBO SPI Interface)


Dibo_valid In 1 DIBO SPI request signal

Dibo_param_addr In 8 DIBO SPI address field

Dibo_param_data In 23 DIBO SPI data field

Dibo_done Out 1 DIBO SPI done signal. Indicates that the DIBO Spi block has completed processing the command I.e., it has sent out the register data on SPI and is ready to take in the next SPI register data.


Application Block

System Control IF :

1. Application Register map values are provided using Parameter setting options e.g. app_param_valid , app_param_data

2. Data pointer and size information are provided such that App can fetch data/control information from buffer.

Buffer IF :

1. App fetches buffer data without intervention from System Control. Note that buffer data could be either data or control frame.

Application DAC Interface

BufferInterface

buf_addr[15:0]

tx_data_i[15:0]

buf_rd

buf_data[31:0]

data_out_valid

tx_data_q[15:0]

app_req

app_param_addr[7:0]

app_param_data[23:0]

app_ptr[15:0]

app_size[15:0]

SystemControl

Interface

app_done

app_type[1:0]

app_param_valid


Application – System Control Interface (as defined in System Control – Application Interface)


App_param_valid In 1 Parameter available sync pulse. Active High for one clock cycle.

App_param_addr In 8 Register map address field

App_param_data In 24 Parameter values e.g. register map values.

App_req In 1 Application processing request signal. Active high. This indicates that data/control frames are available within Buffer. Application shall fetch data/control information using App_type, App_ptr and App_size information.

App_type In 2 Type of frame within Buffer :

00 – control

01 – data

Others – reserved

App_ptr In 16 Address pointer to location of data/control frames

App_size In 16 Size of data/control frames

App_done Out 1 Application processing done signal. Indicates that Application block has completed the processing request. System Control may assert a new request. Active High.


Application – Buffer Interface


Buf_addr Out 16 Buffer address bus.

Buf_rd Out 1 Buffer read enable.

Buf_data In 32 Buffer read data bus (should be one clock latency between assertion of buf_addr until buf_data is available).


Application – DAC Interface


Data_out_valid Out 1 DAC Data valid

Tx_data_i Out 16 DAC I signal

Tx_data_q Out 16 DAC Q signal


DAC Interface

Interleaves the I and Q data from the app block and gives out tx_sync, tx_data to the DAC.

No commands at this point.


DAC Interface - Application IF(As defined in Application – DAC Interface)


data_out_valid In 1 DAC Data valid

tx_data_i In 16 DAC I signal

tx_data_q In 16 DAC Q signal


DAC Interface – FPGA Top IF


dac_sync Out 1 Sync signal which allows 2 streams of data to be sent to the DAC (I and Q). By default tx_sync = 0 for I data tx_sync = 1 for Q data. This can be changed by programming the appropriate register.

dac_data Out 14 Data to the DAC


Documents

WINLAB Open Cognitive Radio Platform Architecture v1.0