BWW

Principles and Elements of

POWER ELECTRONICS Devices, Drivers, Applications, and Passive Components Barry W Williams B.Sc., Dipl.Eng., B.Eng., M.Eng.Sc., Ph.D., D.I.C.

Professor of Electrical Engineering University of Strathclyde Glasgow

Published by Barry W Williams ISBN 978-0-9553384-0-3

Barry W Williams 2006

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Table of Contents

1 1

Basic Semiconductor Physics and Technology

Example 1.1: Resistance of homogeneously doped silicon 2 1.1 Processes forming pn junctions 4

1.1.1 The alloyed junction 1.1.2 The diffused junction Example 1.2: Constant Surface Concentration diffusion predepostion 7 Example 1.3: Constant Total Dopant diffusion drive in 8 Example 1.4: Constant Total Dopant diffusion drive in 8 1.1.3 The epitaxy junction 1.1.4 The ion-implanted junction

Example 1.5: Ion implantation 12 1.2 Thin Film Deposition

1.2.1 Chemical Vapour Deposition (CVD) 1.2.2 Physical Vapour deposition (PVD)

1.3 Thermal oxidation and the masking process 17 1.4 Polysilicon deposition 20 1.5. Lithography optical and electron 21

1.5.1 Optical Lithography 1.5.2 Electron Lithography

1.6 Etching 26

1.6.1 Wet Chemical Etching 1.6.2 Dry Chemical Etching

1.7 Lift-off Processing 32 1.8 Resistor Fabrication 32 1.9 Isolation Techniques 33 1.10 Wafer Cleaning 33 1.11 Planarization 35 1.12 Gettering 35 1.13 Lifetime control 36 1.14 Silicide formation 36 1.15 Ohmic contact 38 1.16 Glassivation 41 1.17 Back side metallisation and die separation 41

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1.18 Wire bonding 41 1.19 Types of silicon 43

1.19.1 Purifying silicon 1.19.2 Crystallinity 1.19.3 Single crystal silicon

1.19.3i Czochralski process 1.19.3ii Float-zone process 1.19.3iii Ribbon silicon

1.19.4 Multi-crystalline Silicon 1.19.5 Amorphous Silicon

1.20 Silicon Carbide 48 1.21 Si and SiC physical and electrical properties compared 48

2

51 The pn Junction

Example 2.1: Built-in potential of an abrupt junction 52

2.1 The pn junction under forward bias (steady-state) 53 2.2 The pn junction under reverse bias (steady-state) 53

2.2.1 Punch-through voltage 2.2.2 Avalanche breakdown 2.2.3 Zener breakdown 2.3 Thermal effects 54 2.4 Models for the bipolar junction diode 55

2.4.1 Piecewise-linear junction diode model Example 2.2: Using the pwl junction diode model 56 Example 2.3: Static linear diode model 56

2.4.2 Semiconductor physics based junction diode model 2.4.2i - Determination of zero bias junction capacitance, Cjo 2.4.2ii - One-sided pn diode equations

Example 2.4: Space charge layer parameter values 60

3

65 Power Switching Devices

and their Static Electrical Characteristics 3.1 Power diodes 65

3.1.1 The pn fast-recovery diode 3.1.2 The p-i-n diode 3.1.3 The power Zener diode 3.1.4 The Schottky barrier diode 3.1.5 The silicon carbide Schottky barrier diode

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3.2 Power switching transistors 70

3.2.1 The bipolar npn power switching junction transistor (BJT) 70 3.2.1i - BJT gain

3.2.1ii - BJT operating states 3.2.1iii - BJT maximum voltage - first and second breakdown

3.2.2 The metal oxide semiconductor field effect transistor (MOSFET) 73 3.2.2i - MOSFET structure and characteristics 3.2.2ii - MOSFET drain current 3.2.2iii - MOSFET transconductance and output conductance 3.2.2iv - MOSFET on-state resistance 3.2.2v - MOSFET p-channel device

Example 3.1: Properties of an n-channel MOSFET cell 78 3.2.2vi - MOSFET parasitic BJT 3.2.2vii - MOSFET on-state resistance reduction

1 - Trench gate 2 - Vertical super-junction

3.2.3 The insulated gate bipolar transistor (IGBT) 81 3.2.3i - IGBT at turn-on 3.2.3ii - IGBT in the on-state

3.2.3iii - IGBT at turn-off 3.2.3iv - IGBT latch-up

1 - IGBT on-state SCR static latch-up 2 - IGBT turn-off SCR dynamic latch-up

3.2.4 Reverse blocking NPT IGBT 83 3.2.5 PT IGBT and NPT IGBT comparison 84

3.2.6 The junction field effect transistor (JFET) 84 3.3 Thyristors 85

3.3.1 The silicon-controlled rectifier (SCR) 3.3.1i - SCR turn-on 3.3.1ii - SCR cathode shorts 3.3.1iii - SCR amplifying gate

3.3.2 The asymmetrical silicon-controlled rectifier (ASCR) 3.3.3 The reverse-conducting thyristor (RCT) 3.3.4 The bi-directional-conducting thyristor (BCT) 3.3.5 The gate turn-off thyristor (GTO)

3.3.5i - GTO turn-off mechanism 3.3.6 The gate commutated thyristor (GCT) 3.3.6i - GCT turn-off 3.3.6ii - GCT turn-on

3.3.7 The light triggered thyristor (LTT) 3.3.8 The triac

3.4 Power packages and modules 95

4 99

Electrical Ratings and Characteristics of Power Semiconductor Switching Devices

4.1 General maximum ratings of power switching semiconductor devices 99

4.1.1 Voltage ratings 4.1.2 Forward current ratings

4.1.3 Temperature ratings 4.1.4 Power ratings 4.2 The fast-recovery diode 101

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4.2.1 Turn-on characteristics 4.2.2 Turn-off characteristics 4.2.3 Schottky diode dynamic characteristics

4.3 The bipolar, high-voltage, power switching npn junction transistor 104

4.3.1 Transistor ratings 4.3.1i - BJT collector voltage ratings 4.3.1ii - BJT safe operating area (SOA)

4.3.2 Transistor switching characteristics 4.3.2i - BJT turn-on time 4.3.2ii - BJT turn-off time

4.3.3 BJT phenomena 4.4 The power MOSFET 109

4.4.1 MOSFET absolute maximum ratings 4.4.2 Dynamic characteristics

4.4.2i - MOSFET device capacitances 4.4.2ii - MOSFET switching characteristics

1 - MOSFET turn-on 2 - MOSFET turn-off 4.5 The insulated gate bipolar transistor 114

4.5.1 IGBT switching 4.5.2 IGBT short circuit operation

4.6 The thyristor 116

4.6.1 SCR ratings 4.6.1i - SCR anode ratings 4.6.1ii - SCR gate ratings 4.6.2 Static characteristics 4.6.2i - SCR gate trigger requirements 4.6.2ii - SCR holding and latching currents 4.6.3 Dynamic characteristics 4.6.3i - SCR anode at turn-on 4.6.3ii - SCR anode at turn-off 4.7 The gate turn-off thyristor 119

4.7.1 Turn-on characteristics 4.7.2 Turn-off characteristics 4.8 Appendix: Effects on MOSFET switching of negative gate drive 121

5 123

Cooling of Power Switching Semiconductor Devices 5.1 Thermal resistances 124

5.1.1 Contact thermal resistance, Rc-s 5.1.2 Heat-sink thermal resistance, Rs-a

5.2 Modes of power dissipation 130

5.2.1 Steady-state response 5.2.2 Pulse response Example 5.1: Semiconductor single power pulse capability 133 5.2.3 Repetitive transient response

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Example 5.2: Semiconductor transient repetitive power capability 135 5.3 Average power dissipation 136

5.3.1 Graphical integration 5.3.2 Practical superposition

5.4 Power losses from manufacturers data sheets 136

5.4.1 Switching transition power loss, Ps 5.4.2 Off-state leakage power loss, AP

5.4.3 Conduction power loss, Pc 5.4.4 Drive input device power loss, PG 5.5 Heat-sinking design cases 138

5.5.1 Heat-sinking for diodes and thyristors 5.5.1i - Low-frequency switching 5.5.1ii - High-frequency switching

Example 5.3: Heat-sink design for a diode 141 5.5.2 Heat-sinking for IGBTs Example 5.4: Heat-sink design for an IGBT - repetitive operation at a high duty cycle 141

5.5.3 Heat-sinking for power MOSFETs Example 5.5: Heat-sink for a MOSFET - repetitive operation at high peak current, low duty cycle 142 Example 5.6: Heat-sink design for a mosfet - repetitive operation at high duty cycle 143 Example 5.7: Two thermal elements on a common heatsink 143 Example 5.8: Six thermal elements in a common package 144

5.6 Appendix: Comparison between aluminium oxide and aluminium nitride 145 5.7 Appendix: Properties of substrate and module materials 147 5.8 Appendix: Ampacities and Mechanical Properties of Rectangular Copper Busbars 147

6 151

Load, Switch, and Commutation Considerations 6.1 Load types 151

6.1.1 The resistive load Example 6.1: Resistive load switching losses 154 Example 6.2: Transistor switching loss for non-linear electrical transitions 155 6.1.2 The inductive load Example 6.3: Zener diode, switch voltage clamping 157 Example 6.4: Inductive load switching losses 161

6.1.3 Diode reverse recovery with an inductive load Example 6.5: Inductive load switching losses with device models 162 6.2 Switch characteristics 164 6.3 Switching classification 164

6.3.1 Hard switching 6.3.2 Soft switching 6.3.3 Resonant switching 6.3.4 Naturally-commutated switching

6.4 Switch configurations 166

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7 169

Driving Transistors and Thyristors 7.1 Application of the power MOSFET and IGBT 169

7.1.1 Gate drive circuits 7.1.1i - Negative gate drive 7.1.1ii - Floating power supplies

1 - capacitive coupled charge pump 2 - diode bootstrap

7.1.2 Gate drive design procedure Example 7.1: MOSFET input capacitance and switching times 177

7.2 Application of the Thyristor 177

7.2.1 Thyristor gate drive circuits 7.2.2 Thyristor gate drive design Example 7.2: A light dimmer 180

7.3 Drive design for GCT and GTO thyristors 181

8 185

Protecting Diodes, Transistors, and Thyristors 8.1 The non-polarised R-C snubber 186

8.1.1 R-C switching aid circuit for the GCT, the MOSFET, and the diode Example 8.1: R-C snubber design for MOSFETs 187 8.1.2 Non-polarised R-C snubber circuit for a converter grade thyristor and a triac Example 8.2: Non-polarised R-C snubber design for a converter grade thyristor 189

8.2 The soft voltage clamp 190

Example 8.3: Soft voltage clamp design 191 8.3 Polarised switching-aid circuits 193

8.3.1 The polarised turn-off snubber circuit - assuming a linear current fall 8.3.2 The turn-off snubber circuit - assuming a cosinusoidal current fall

Example 8.4: Capacitive turn-off snubber design 200 8.3.3 The polarised turn-on snubber circuit - with air core (non-saturable) inductance Example 8.5: Turn-on air-core inductor snubber design 206

8.3.4 The polarised turn-on snubber circuit - with saturable ferrite inductance Example 8.6: Turn-on ferrite-core saturable inductor snubber design 209 8.3.5 The unified turn-on and turn-off snubber circuit

8.4 Snubbers for bridge legs 212

8.5 Appendix: Non-polarised turn-off R-C snubber circuit analysis 213 8.6 Appendix: Polarised turn-off R-C-D switching aid circuit analysis 216

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9 221

Switching-aid Circuits with Energy Recovery 9.1 Energy recovery for inductive turn-on snubber circuits 221

9.1.1 Passive recovery 9.1.2 Active recovery

9.2 Energy recovery for capacitive turn-off snubber circuits 225

9.2.1 Passive recovery 9.2.2 Active recovery 9.3 Unified turn-on and turn-off snubber circuit energy recovery 232

9.3.1 Passive recovery 9.3.2 Active recovery

9.4 Inverter bridge legs 238

9.4.1 Turn-on snubbers 9.4.2 Turn-on and turn-off snubbers

9.5 Snubbers for multi-level inverters 241

9.5.1 Snubbers for the cascaded H-bridge multi-level inverter 9.5.2 Snubbers for the diode-clamped multi-level inverter 9.5.3 Snubbers for the flying-capacitor multi-level inverter 9.6 Snubbers for series connected devices 242

9.6.1 Turn-off snubber circuit active energy recovery 9.6.2 Turn-on snubber circuit active energy recovery 9.6.3 Turn-on and turn-off snubber circuit active energy recovery 9.6.4 General active recovery concepts

9.7 Snubber energy recovery for magnetically coupled based switching circuits 249 9.7.1 Passive recovery

9.7.2 Active recovery 9.8 General passive snubber energy recovery concepts 250

10

257 Series and Parallel Device Operation, Protection,

and Interference 10.1 Parallel and series connection and operation of power semiconductor devices 257

10.1.1 Series semiconductor device operation 10.1.1i - Steady-state voltage sharing

Example 10.1: Series device connection static voltage balancing 259 10.1.1ii - Transient voltage sharing

Example 10.2: Series device connection dynamic voltage balancing 262 10.1.2 Parallel semiconductor device operation

10.1.2i - Matched devices 10.1.2ii - External forced current sharing

Example 10.3: Resistive parallel current sharing static current balancing 265 (a) current sharing analysis for two devices: ro = 0 (b) current sharing analysis for two devices: ro 0 (c) current sharing analysis for n devices: ro = 0

Example 10.4: Transformer current sharingstatic and dynamic current balancing 270

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10.2 Protection 271

10.2.1 Overcurrent 10.2.1i - Pre-arcing I2t

10.2.1ii - Total I2t let-through 10.2.1iii - Fuse link and semiconductor I2t co-ordination

10.2.1iv - Fuse link derating and losses Example 10.5: AC circuit fuse link design 276

10.2.1v - Fuse link dc operation 10.2.1vi - Alternatives to dc fuse operation

Example 10.6: DC circuit fuse link design 278 10.2.2 Overvoltage

10.2.2i - Transient voltage suppression devices 10.2.2ii - Comparison between Zener diodes and varistors

Example 10.7: Non-linear voltage clamp 273 10.2.3 The Crowbar

10.3 Interference 284

10.3.1 Noise 10.3.1i - Conducted noise 10.3.1ii - Radiated electromagnetic field coupling 10.3.1iii - Electric field coupling 10.3.1iv - Magnetic field coupling 10.3.2 Mains filters 10.3.3 Noise filtering precautions

11

289 Naturally Commutating AC to DC Converters

Uncontrolled Rectifiers 11.1 Single-phase uncontrolled converter circuits - ac rectifiers 289

11.1.1 Half-wave circuit with a resistive load, R 11.1.2 Half-wave circuit with a resistive and back emf R-E load Example 11.1: Half-wave rectifier with resistive and back emf load 291 11.1.3 Single-phase half-wave circuit with an R-L load

11.1.3i - Inductor equal voltage area criterion 11.1.3ii - Load current zero slope criterion Example 11.2: Half-wave rectifier with source resistance 295

11.1.4 Single-phase half-wave circuit with an R-L load and freewheel diode Example 11.3: Half-wave rectifier with load freewheel diode 299 11.1.5 Single-phase full-wave bridge rectifier circuit with a resistive load, R

11.1.6 Single-phase full-wave bridge rectifier circuit with a resistive and back emf load Example 11.4: Full-wave rectifier with resistive and back emf load 253

11.1.7 Single-phase full-wave bridge rectifier circuit with an R-L load 11.1.7i - Single-phase full-wave bridge rectifier circuit with an output L-C filter Example 11.5: Full-wave diode rectifier with L-C filter and continuous load current 305

11.1.7ii - Single-phase full-wave bridge recifier with highly inductive loadsconstant load current 11.1.7iii - Single-phase full-wave bridge rectifier circuit with a C-filter and resistive load

Example 11.6: Single-phase full-wave bridge circuit with C-filter and resistive load 311 11.1.7iv - Other single-phase bridge rectifier circuit configurations

11.2 Three-phase uncontrolled rectifier converter circuits 313

11.2.1 Three-phase half-wave rectifier circuit with an inductive R-L load 11.2.2 Three-phase full-wave rectifier circuit with an inductive R-L load

11.2.2i - Three-phase full-wave bridge rectifier circuit with continuous load current 11.2.2ii - Three-phase full-wave bridge rectifier circuit with highly inductive load

Example 11.7: Three-phase full-wave rectifier 318 Example 11.8: Rectifier average load voltage 319

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11.3 DC MMFs in converter transformers 320

11.3.1 Effect of multiple coils on multiple limb transformers 11.3.2 Single-phase toroidal core mmf imbalance cancellation zig-zag winding 11.3.3 Single-phase transformer connection, with full-wave rectification 11.3.4 Three-phase transformer connections 11.3.5 Three-phase transformer, half-wave rectifiers - core mmf imbalance 11.3.6 Three-phase transformer with hexa-phase rectification, mmf imbalance 11.3.7 Three-phase transformer mmf imbalance cancellation zig-zag winding 11.3.8 Three-phase transformer full-wave rectifiers zero core mmf

11.4 Voltage multipliers 345

11.4.1 Half-Wave Series Multipliers 11.4.2 Half-Wave Parallel Multipliers 11.4.3 Full-Wave Series Multipliers Example 11.9: Half-wave voltage multiplier 349 Example 11.10: Full-wave voltage multiplier 350 11.4.4 Three-phase voltage multipliers 11.4.5 Series versus parallel voltage multipliers

11.5 Marx voltage generator 350 11.6 Definitions 352 11.7 Output pulse number 352 11.8 AC-dc converter generalised equations 353

12

361 Naturally Commutating AC to DC Converters

Controlled Rectifiers 12.1 Single-phase full-wave half-controlled converter 361

12.1i - Discontinuous load current 12.1ii - Continuous load current

12.2 Single-phase controlled thyristor converter circuits 365

12.2.1 Single-phase half-wave circuit with an R-L load 12.2.1i - Case 1: Purely resistive load 12.2.1ii - Case 2: Purely inductive load 12.2.1iii - Case 3: Back emf E and R-L load

Example 12.1: Half-wave controlled rectifier 368 12.2.2 Single-phase half-wave half-controlled

12.2.2i - discontinuous conduction 12.2.2ii - continuous conduction

12.2.3 Single-phase full-wave controlled rectifier circuit with an R-L load 12.2.3i - , - > < , discontinuous load current

12.2.3ii - , - = = , verge of continuous load current 12.2.3iii - < , - = , continuous load current (and also purely inductive load)

Example 12.2: Controlled full-wave converter continuous and discontinuous conduction 375 12.2.4 Single-phase full-wave, fully-controlled circuit with R-L and emf load, E

12.2.4i - Discontinuous load current 12.2.4ii - Continuous load current

Example 12.3: Controlled converter - continuous conduction and back emf 380 Example 12.4: Controlled converter constant load current, back emf, and overlap 381

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12.3 Three-phase half-controlled converter 382

12.3i - 12.3ii -

12.4 Three-phase fully-controlled thyristor converter circuits 384

12.4.1 Three-phase half-wave, fully controlled circuit with an inductive load 12.4.2 Three-phase half-wave converter with freewheel diode 12.4.2i - < /6 12.4.2ii - >/6 12.4.2iii - >5/6

Example 12.5: Three-phase half-wave rectifier with freewheel diode 386 12.4.3 Three-phase full-wave fully-controlled circuit with an inductive load

12.4.3i - Resistive load 12.4.3ii - Highly inductive load constant load current

Example 12.6: Three-phase full-wave controlled rectifier with constant output current 391 12.4.4 Three-phase full-wave converter with freewheel diode

Example 12.7: Converter average load voltage 393

12.7 Overlap 394 12.6 Overlap inversion 397

Example 12.8: Converter overlap 399 12.7 Summary 400

(i) Half-wave and full-wave, fully-controlled converter (ii) Full-wave, half-controlled converter (iii) Half-wave and full-wave controlled converter with load freewheel diode 12.8 Definitions 401 12.9 Output pulse number 402 12.10 AC-dc converter generalised equations 404

13

413 AC Voltage Regulators 13.1 Single-phase ac regulator 413

13.1.1 Single-phase ac regulator phase control with line commutation Case 1: > Case 2:

13.1.1i - Resistive Load 13.1.1ii - Pure inductive Load 13.1.1iii - Load sinusoidal back emf 13.1.1iv - Semi-controlled single-phase ac regulator

Example 13.1a: Single-phase ac regulator 1 423 Example 13.1b: Single-phase ac regulator - 2 424 Example 13.1c: Single-phase ac regulator pure inductive load 245 Example 13.1d: Single-phase ac regulator 1 with ac back emf composite load 427

13.1.2 Single-phase ac regulator integral cycle control line commutated Example 13.2: Integral cycle control 430

13.2 Single-phase transformer tap-changer line commutated 432

Example 13.3: Tap changing converter 434 13.3 Single-phase ac chopper regulator commutable switches 437

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13.4 Three-phase ac regulator 437

13.4.1 Fully-controlled three-phase ac regulator with wye load and isolated neutral Purely resistive load

i. 0 [mode 3/2] ii. [mode 2/2] iii. [mode 2/0]

Inductive-resistive load Purely inductive load

i. [mode 3/2] ii. [mode 2/0]

13.4.2 Fully-controlled three-phase ac regulator with wye load and neutral connected 13.4.3 Fully-controlled three-phase ac regulator with delta load 13.4.4 Half-controlled three-phase ac regulator

Resistive load i. 0

ii. iii. 7/6 Purely inductive load

13.4.5 Other thyristor three-phase ac regulators i. Delta connected fully controlled regulator ii. Three-thyristor delta connected regulator

Example 13.4: Star-load three-phase ac regulator untapped neutral 444 13.5 Cycloconverter 449 13.6 The matrix converter 452 13.7 Power Quality: load efficiency and supply current power factor 454

13.7.1 Load waveforms 13.7.2 Supply waveforms Example 13.5: Power quality - load efficiency 456

Example 13.6: Power quality - sinusoidal source and constant current load 456 Example 13.7: Power quality - sinusoidal source and non-linear load 457

14

461 DC Choppers 14.1 DC chopper variations 461 14.2 First Quadrant dc chopper 462

14.2.1 Continuous load current Steady-state time domain analysis of first quadrant chopper

- with load back emf and continuous output current i. Fourier coefficients ii. Time domain differential equations

14.2.2 Discontinuous load current Steady-state time domain analysis of first quadrant chopper

- with load back emf and discontinuous output current i. Fourier coefficients ii. Time domain differential equations

Example 14.1: DC chopper (first quadrant) with load back emf 470 Example 14.2: DC chopper with load back emf - verge of discontinuous conduction 474 Example 14.3: DC chopper with load back emf - discontinuous conduction 475

14.3 Second Quadrant dc chopper 478

14.3.1 Continuous load inductor current 14.3.2 Discontinuous load inductor current Example 14.4: Second quadrant DC chopper - continuous inductor current 482

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14.4 Two quadrant dc chopper - Q I and Q II 484

Example 14.5: Two quadrant DC chopper with load back emf 484 14.5 Two quadrant dc chopper Q 1 and Q IV 433

14.5.1 dc chopper: Q I and Q IV multilevel output voltage switching (three level) 14.5.2 dc chopper: Q I and Q IV bipolar voltage switching (two level)

14.5.3 Multilevel output voltage states, dc chopper Example 14.6: Asymmetrical, half H-bridge, dc chopper 497

14.6 Four quadrant dc chopper 499

14.6.1 Unified four quadrant dc chopper - bipolar voltage output switching 14.6.2 Unified four quadrant dc chopper - multilevel voltage output switching Example 14.7: Four quadrant dc chopper 506

15

509 DC to AC Inverters Switched Mode 15.1 dc to ac voltage-source inverter bridge topologies 509

15.1.1 Single-phase voltage-source inverter bridge 15.1.1i - Square-wave (bipolar) output

15.1.1ii - Quasi-square-wave (multilevel) output Example 15.1: Single-phase H-bridge with an L-R load 515 Example 15.2: H-bridge inverter ac output factors 516 Example 15.3: Harmonic analysis of H-bridge with an L-R load 518 Example 15.4: Single-phase half-bridge with an L-R load 518

15.1.1iii - PWM-wave output 15.1.2 Three-phase voltage-source inverter bridge 15.1.2i - 180 () conduction 15.1.2ii - 120 () conduction 15.1.3 Inverter ac output voltage and frequency control techniques

15.1.3i - Variable voltage dc link 15.1.3ii - Single-pulse width modulation

Example 15.5: Single-pulse width modulation 529 15.1.3iii - Multi-pulse width modulation 15.1.3iv - Multi-pulse, selected notching modulation 15.1.3v - Sinusoidal pulse-width modulation (pwm) 1 - Natural sampling 2 - Regular sampling

3 - Frequency spectra of pwm waveforms 15.1.3vi - Phase dead-banding 15.1.3vii - Triplen Injection modulation

1 - Triplens injected into the modulation waveform 2 - Voltage space vector pwm

15.2 dc-to-ac controlled current-source inverters 543

15.2.1 Single-phase current source inverter 15.2.2 Three-phase current source inverter 15.3 Multi-level voltage-source inverters 546

15.3.1 Diode clamped multilevel inverter 15.3.2 Flying capacitor multilevel inverter 15.3.3 Cascaded H-bridge multilevel inverter 15.3.4 PWM for multilevel inverters

15.3.4i - Multiple offset triangular carriers 15.3.4ii - Multilevel rotating voltage space vector

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15.4 Reversible dc link converters 554

15.4.1 Independent control 15.4.2 Simultaneous control 15.4.3 Inverter regeneration

15.5 Standby inverters and uninterruptible power supplies 557

15.5.1 Single-phase ups 15.5.2 Three-phase ups

15.6 Power filters 559

16

561 DC to AC Inverters Resonant Mode 16.1 Resonant dc-ac inverters 561

16.2 L-C resonant circuits 562 16.2.1 - Series resonant L-C-R circuit 16.2.2 - Parallel resonant L-C-R circuit

16.3 Series resonant inverters 565

16.3.1 - Series resonant inverter single inverter leg 1 - Lagging operation (advancing the switch turn-off angle) 2 - Leading operation (delaying the switch turn-on angle)

16.3.2 - Series resonant inverter H-bridge voltage-source inverter 16.3.3 - Circuit variations

16.4 Parallel resonant current-source inverters 570

16.4.1 - Parallel resonant inverter single inverter leg 16.4.2 - Parallel resonant inverter H-bridge current-source inverter Example 16.1: Half-bridge with a series L-C-R load 572

16.5 Single-switch, current source, series resonant inverter 575

17

577 DC to DC Converters - Switched Mode 17.1 The forward converter 578

17.1.1 Continuous inductor current 17.1.2 Discontinuous inductor current

17.1.3 Load conditions for discontinuous inductor current 17.1.4 Control methods for discontinuous inductor current

17.1.4i - fixed on-time tT, variable switching frequency fvar 17.1.4ii - fixed switching frequency fs, variable on-time tTvar

17.1.5 Output ripple voltage Example 17.1: Buck (step-down forward) converter 583

17.1.6 Underlying operational mechanisms of the forward converter 17.2 Flyback converters 588 17.3 The boost converter 589

17.3.1 Continuous inductor current

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17.3.2 Discontinuous capacitor charging current in the switch off-state 17.3.3 Discontinuous inductor current 17.3.4 Load conditions for discontinuous inductor current 17.3.5 Control methods for discontinuous inductor current

17.3.5i - fixed on-time tT, variable switching frequency fvar 17.3.5ii - fixed switching frequency fs, variable on-time tTvar

17.3.6 Output ripple voltage Example 17.2: Boost (step-up flyback) converter 593 Example 17.3: Alternative boost (step-up flyback) converter 595

17.4 The buck-boost converter 597

17.4.1 Continuous choke (inductor) current 17.4.2 Discontinuous capacitor charging current in the switch off-state

17.4.3 Discontinuous choke current 17.4.4 Load conditions for discontinuous inductor current

17.4.5 Control methods for discontinuous inductor current 17.4.5i - fixed on-time tT, variable switching frequency fvar 17.4.5ii - fixed switching frequency fs, variable on-time tTvar

17.4.6 Output ripple voltage 17.4.7 Buck-boost, flyback converter design procedure

Example 17.4: Buck-boost flyback converter 602 17.5 Flyback converters a conceptual assessment 604 17.6 The output reversible converter 607

17.6.1 Continuous inductor current 17.6.2 Discontinuous inductor current 17.6.3 Load conditions for discontinuous inductor current 17.6.4 Control methods for discontinuous inductor current

17.6.4i - fixed on-time tT, variable switching frequency fvar 17.6.4ii - fixed switching frequency fs, variable on-time tTvar

Example 17.5: Reversible forward converter 610 17.6.5 Comparison of the reversible converter with alternative converters

17.7 The uk converter 612

17.7.1 Continuous inductor current 17.7.2 Discontinuous inductor current 17.7.3 Optimal inductance relationship 17.7.4 Output voltage ripple Example 17.6: Cuk converter 614

17.8 Comparison of basic converters 615

17.8.1 Critical load current 17.8.2 Bidirectional converters

17.8.3 Isolation 17.8.3i - The isolated output, forward converter 17.8.3ii - The isolated output, flyback converter

Example 17.7: Transformer coupled flyback converter 621 Example 17.8: Transformer coupled forward converter 623 17.9 Multiple-switch, balanced, isolated converters 625

17.9.1 The push-pull converter 17.9.2 Bridge converters 17.10 Basic generic smps transfer function mapping 627 17.11 Appendix: Analysis of non-continuous inductor current operation 629

Operation with constant input voltage, Ei Operation with constant output voltage, vo

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18 647

DC to DC Converters - Resonant Mode 18.1 Series loaded resonant dc to dc converters 647

18.1.1 Modes of operation - series resonant circuit 18.1.2 Circuit variations

18.2 Parallel loaded resonant dc to dc converters 652

18.2.1 Modes of operation- parallel resonant circuit 18.2.2 Circuit variations

18.3 Seriesparallel load resonant dc to dc converters 655

18.3.1 LCC resonant tank circuit 18.3.2 LLC resonant tank circuit Example 18.1: Transformer-coupled, series-resonant, dc-to-dc converter 658

18.4 Resonant switch, dc to dc step-down voltage converters 660

18.4.1 Zero-current, resonant-switch, dc-to-dc converter - wave, CR parallel with load version

18.4.1i - Zero-current, full-wave resonant switch converter 18.4.2 Zero-current, resonant-switch, dc-to-dc converter

- wave, CR parallel with switch version 18.4.3 Zero-voltage, resonant-switch, dc-to-dc converter

- wave, CR parallel with switch version 18.4.3i - Zero-voltage, full-wave resonant switch converter

18.4.4 Zero-voltage, resonant-switch, dc-to-dc converter - wave, CR parallel with load version

Example 18.2: Zero-current, resonant-switch, dc-to-dc converter - wave 673 Example 18.3: Zero-current, resonant-switch, dc-to-dc converter - full-wave 675 Example 18.4: Zero-voltage, resonant-switch, dc-to-dc converter - wave 676

18.5 Resonant switch, dc to dc step-up voltage converters 677 18.5.1 ZCS resonant-switch, dc-to-dc step-up voltage converters 18.5.2 ZVS resonant-switch, dc-to-dc step-up voltage converters

18.5 Appendix: Matrices of resonant switch buck, boost, and buck/boost converters 681

19 687

HV Direct-Current Transmission 19.1 HVDC electrical power transmission 687

19.2 HVDC Configurations 688

19.2i - Monopole and earth return 19.2ii - Bipolar 19.2iii - Tripole 19.2iv - Back-to-back 19.2v - Multi-terminal

19.3 Typical HVDC transmission system 689 19.4 Twelve-pulse ac line frequency converters 690

19.4.1 Rectifier mode 19.4.2 Inverter mode

Power Electronics

xvii

19.5 Twelve-pulse ac line frequency converter operation control 695

19.5.1 Control and protection 19.5.2 HVDC Control objectives

19.6 Filtering and power factor correction 698

Example 19.1: Basic six-pulse converter based hvdc transmission 699

Example 19.2: 12-pulse hvdc transmission 700 19.7 VSC-Based HVDC 702

19.7.1 VSC-Based HVDC control 19.7.2 Power control concept

19.8 HVDC Components 705

Example 19.3: HVDC transmission with voltage source controlled dc-link 707 19.9 Twelve-pulse transformer based HVDC 709 19.10 HVDC VSC Features 709 19.11 Features of conventional HVDC and HVAC transmission 710

20 713

FACTS Devices and Custom Controllers 20.1 Flexible AC Transmission Systems - FACTS 713 20.2 Power Quality 713 20.3 Principles of Power Transmission 714

Example 20.1: AC transmission line VAr 715

20.4 Static Reactive Power Compensation 717 20.5 Static Shunt Reactive Power Compensation 718

20.5.1 - Thyristor controlled reactor TCR 20.5.2 - Thyristor switched capacitor TSC 20.5.3 - Shunt Static VAr compensator SVC (TCR//TSC)

Example 20.3: Shunt thyristor controlled reactor specification 723

20.6 Static Series Reactive Power Compensation 724 20.6.1 - Thyristor switched series capacitor TSSC 20.6.2 - Thyristor controlled series capacitor TCSC 20.6.3 - Series Static VAr compensator SVC (TCR//C) Example 20.3: Series thyristor controlled reactor specification integral control 728 Example 20.4: Series thyristor controlled reactor specification Vernier control 730 20.6.4 Static series phase angle reactive power compensation/shift SPS

20.7 Custom Power 735 20.7.1 - Static synchronous series compensator or Dynamic Voltage Restorer - DVR 20.7.2 - Static synchronous shunt compensator STATCOM

Power Electronics xviii

20.7.3 - Unified power flow controller - UPFC

20.8 Combined Active and Passive Filters 747 20.8.1 - Current compensation shunt filtering 20.8.2 - Voltage compensation series filtering 20.8.3 - Active and passive combination filtering

20.9 Summary of Compensator Comparison and Features 749 20.10 Summary of General Advantages of AC Transmission over DC Transmission 750

21 751

Energy Sources and Storage: Primary Sources

21.1 Hydrocarbon attributes 751

21.2 The fuel cell 753 21.3 Materials and cell design 755

21.3.1 Electrodes 21.3.2 Catalyst 21.3.3 Electrolyte 21.3.4 Interconnect 21.3.5 Stack design

21.4 Fuel Cell Chemistries 758

21.4.1 Proton H+ Cation Conducting Electrolyte 21.4.2 Anion (OH-, CO32-, O2-) Conducting Electrolyte

21.5 Six different Fuel Cells 760 21.6 Low-temperature Fuel Cell Types 761

21.6.1 Polymer exchange membrane fuel cell 21.6.2 Alkaline fuel cell 21.6.3 Direct-methanol fuel cell

21.7 High-temperature Fuel Cell Types 764

21.7.1 Phosphoric-acid fuel cell 21.7.2 Molten-carbonate fuel cell 21.7.3 Solid oxide fuel cell

21.8 Fuel Cell Summary 768 21.9 Fuels 768 21.10 Fuel Reformers 769

21.10.1 Natural gas reforming

21.11 Hydrogen storage and generation from Sodium Borohydride 772 21.12 Fuel Cell Emissions 772 21.13 Fuel Cell Electrical characteristics 773

Power Electronics

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21.14 Thermodynamics 774

Example 21.1: Formation of water vapour 775 Example 21.2: Derivation of Ideal Fuel Cell Voltage 776

Example 21.3: Carbon fuel cell 778

21.15 Fuel Cell features 779 21.16 Fuel Cell Challenges 780

21.16.1 Chemical Technology Challenges 21.16.2 System Technology Challenges

21.17 Fuel cell summary 781 21.18 Photovoltaic Cells: Converting Photons to Electrons 784 21.19 Silicon structural physics 784 21.20 Semiconductor materials and structures 785

21.20.1 Silicon 21.20.2 Polycrystalline thin films 21.20.3 Single-Crystalline Thin Film 21.20.4 Nanocrystalline

21.21 PV Cell Structures 794

21.21.1 Homojunction Device 21.21.2 Heterojunction Device 21.21.3 p-i-n and n-i-p Devices 21.21.4 Multi-junction Devices

21.22 Equivalent circuit of a PV cell 797

21.22.1 Ideal PV cell model 21.22.2 Practical PV cell model 21.22.3 Maximum-power point

21.23 Photovoltaic cell efficiency factors 800

21.24 Module (or array) series and parallel PV cell connection 801

Example 21.4: PV cell and module characteristics 802

21.25 Battery storage 803 21.26 The organic photovoltaic cell 804 21.27 Summary of PV cell technology 806

22 809

Energy Sources and Storage: Secondary Sources 22.1 Batteries 809 22.2 The secondary electro-chemical cell 810

22.2.1 REDOX Galvanic Action 22.2.2 Intercalation Action

Power Electronics xx

22.3 Characteristics of Secondary Batteries 814 22.4 The lead-acid battery 816

21.4.1 The Flooded lead acid cell 22.4.2 Different lead-acid cell and battery arrangements 22.4.3 Lead-acid battery properties

22.5 The nickel-cadmium battery 820

22.5.1 Nickel-Cadmium battery properties 22.6 The nickel-metal-hydride battery 823

22.6.1 Nickel-metal-hydride battery properties 22.6.2 Nickel-metal-hydride battery characteristics

22.7 The lithium-ion battery 825

22.7.1 Cathode variants cells 22.7.2 General Lithium-ion Cell characteristics 22.7.3 General Lithium-ion Cell properties 22.7.4 Cell protection circuits

22.8 Summary of key primary and secondary cell technologies 832 22.9 The Electrochemical Double Layer Capacitor - supercapacitor 833

22.9.1 Double layer capacitor model 22.9.2 Supercapacitor general properties

23

839 Inverter Grid Connection for Embedded Generation 24

843 Inductors and Transformers 24.1 Inductor and transformer electrical characteristics 844

24.1.1 Inductors 24.1.2 Transformers or magnetically coupled circuits

24.2 Magnetic material types 846

24.2.1 Ferromagnetic materials 24.2.1i - Steel 24.2.1ii - Iron powders

24.2.1iii - Alloy powders 24.2.1iv - Nanocrystalline

24.2.2 Ferrimagnetic materials- soft ferrites 24.3 Comparison of material types 847 24.4 Ferrite characteristics 848

Power Electronics

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24.4.1 Dimensions and parameters 24.4.2 Permeability 24.4.2i - Initial or intrinsic permeability, i

24.4.2ii - Amplitude permeability, a and maximum permeability, 24.4.2iii - Reversible or incremental permeability, rev,

24.4.2iv - Effective permeability, e 24.4.2v - Complex permeability,

24.4.3 Coercive force and remanence 24.4.4 Core losses

24.4.4i - Core losses at low H 24.4.4ii - Core losses at high H

24.4.5 Temperature effects on core characteristics 24.4.6 Inductance stability

24.4.6i - Parameter effects 24.4.6ii - Time effects

Example 24.1: Inductance variation with time 858 24.4.6iii - Temperature effects

Example 24.2: Temperature effect on inductance 858 24.4.7 Stored energy in inductors 24.5 Ferrite inductor and choke design, when carrying dc current 860

24.5.1 Linear inductors and chokes Example 24.3: Inductor design with Hanna curves 862

24.5.1i - Core temperature and size considerations Example 24.4: Inductor design including copper loss 865 24.5.2 Saturable inductors

24.5.3 Saturable inductor design Example 24.5: Saturable inductor design 869

24.6 Power ferrite transformer design 869

24.6.1 Ferrite voltage transformer design Example 24.6: Ferrite voltage transformer design 873

24.6.2 Ferrite current transformer 24.6.3 Current transformer design requirements 24.6.4 Current transformer design procedure

Example 24.7: Ferrite current transformer design 878 24.6.5 Current measurement: closed loop ferrite transformer 24.6.6 Current measurement: Rogowski Coil

24.7 Appendix: Soft ferrite general technical data 881 24.8 Appendix: Technical data for a ferrite applicable to power applications 882 24.9 Appendix: Technical data for iron, nickel, and cobalt applicable to power applications 882 24.10 Appendix: Cylindrical inductor design 883

Example 24.8: Wound strip air core inductor 883 Example 24.9: Multi-layer air core inductor 884

24.11 Appendix: Copper wire design data 885 24.12 Appendix: Minimisation of stray inductance 885

24.11.1 Reduction in wiring residual inductance 24.11.2 Reduction in component residual inductance

24.11.2i - Capacitors 24.11.2ii - Capacitors - parallel connected 24.11.2iii - Transformers 24.13 Appendix: Laminated bus bar design 888

Power Electronics xxii

24.14 Appendix: Materials by types of magnetization 891

25 895

Resistors 25.1 Resistor types 896 25.2 Resistor construction 896

25.2.1 Film resistor construction 25.2.2 Carbon composition film resistor construction Example 25.1: Carbon film resistor 896 25.2.3 Solid Carbon ceramic resistor construction

25.2.4 Wire-wound resistor construction 25.3 Electrical properties 899

25.3.1 Resistor/Resistance coefficients 25.3.1i - Temperature coefficient of resistance

Example 25.2: Temperature coefficient of resistance for a thick film resistor 902 25.3.1ii - Voltage coefficient of resistance

25.3.2 Maximum working voltage 25.3.3 Residual capacitance and residual inductance

Example 25.3: Coefficients of resistance for a solid carbon ceramic resistor 905 25.4 Thermal properties 905

25.4.1 Resistors with heatsink Example 25.4: Derating of a resistor mounted on a heatsink 908 25.4.2 Short time or overload ratings Example 25.5: Non-repetitive pulse rating 909

25.5 Repetitive pulsed power resistor behaviour 909

Example 25.6: Pulsed power resistor design 910 25.5.1 Empirical pulse power

25.5.2 Mathematical pulse power models Example 25.7: Solid carbon ceramic resistor power rating 911 25.6 Stability and endurance 912

Example 25.8: Power resistor stability 913 25.7 Special function power resistors 914

25.7.1 Fusible resistors 25.7.2 Circuit breaker resistors 25.7.3 Temperature sensing resistors 25.7.4 Current sense resistors

25.8 Appendix: Carbon ceramic electrical and mechanical data and formula 917 25.9 Appendix: Preferred resistance values of resistors (and capacitors) 917

26 919

Capacitors 26.1 Capacitor general properties 920

26.1.1 Capacitance

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26.1.2 Volumetric efficiency 26.1.3 Equivalent circuit

26.1.4 Lifetime and failure rate Example 26.1: Failure rate 924 Example 26.2: Capacitor reliability 924 26.1.5 Self-healing 26.1.6 Temperature range and capacitance dependence

26.1.7 Dielectric absorption 26.2 Liquid (organic) and solid, metal oxide dielectric capacitors 926

26.2.1 Construction 26.2.2 Voltage ratings 26.2.3 Leakage current 26.2.4 Ripple current Example 26.3: Capacitor ripple current rating 930 26.2.5 Service lifetime and reliability

26.2.5i - Liquid, oxide capacitors Example 26.4: A1203 capacitor service life 932

26.2.5ii - Solid, oxide capacitors Example 26.5: Lifetime of tantalum capacitors 933

26.3 Plastic film dielectric capacitors 934

26.3.1 Construction 26.3.1i - Metallised plastic film dielectric capacitors 26.3.1ii - Foil and plastic film capacitors

26.3.1iii - Mixed dielectric capacitors 26.3.2 Insulation

26.3.3 Electrical characteristics 26.3.3i - Temperature dependence 26.3.3ii - Dissipation factor and impedance

26.3.3iii - Voltage derating Example 26.6: Power dissipation limits - ac voltage 940

26.3.3iv - Pulse dVR /dt rating 26.3.4 Non-sinusoidal repetitive voltages Example 26.7: Capacitor non-sinusoidal voltage rating 942 Example 26.8: Capacitor power rating for non-sinusoidal voltages 943

26.4 Emi suppression capacitors 943

26.4.1 Class X capacitors 26.4.2 Class Y capacitors 26.4.3 Feed-through capacitors

26.5 Ceramic dielectric capacitors 945

26.5.1 Class I dielectrics 26.5.2 Class II dielectrics 26.5.3 Applications

26.6 Mica dielectric capacitors 948

26.6.1 Properties and applications 26.7 Capacitor type comparison based on key properties 950 26.8 Appendix: Minimisation of stray capacitance 950 26.9 Appendix: Capacitor lifetime derating 950

Power Electronics xxiv

Glossary of terms 953

Glossary of wafer processing terminology Glossary of electrochemical battery terminology Glossary of Fuel Cell Terminology Glossary of Solar Electric terminology Glossary of Capacitor terminology

Bibliography 972 Physical constants 982 INDEX 983

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PREFACE The book is in four parts. Part 1 covers power semiconductor switching devices, their static and dynamic electrical and thermal characteristics and properties. Part 2 describes device driving and protection, while Part 3 presents a number of generic applications. The final part, Part 4, introduces capacitors, magnetic components, and resistors, and their characteristics relevant to power electronic applications.

1 Basic Semiconductor Physics and Technology 2 The pn Junction 3 Power Switching Devices and their Static Electrical Characteristics 4 Electrical Ratings and Characteristics of Power Semiconductor Switching Devices 5 Cooling of Power Switching Semiconductor Devices

6 Load, Switch, and Commutation Considerations 7 Driving Transistors and Thyristors 8 Protecting Diodes, Transistors, and Thyristors 9 Switching-aid Circuits with Energy Recovery 10 Series and Parallel Device Operation, Protection, and Interference

11 Naturally Commutating AC to DC Converters Uncontrolled Rectifiers 12 Naturally Commutating AC to DC Converters Controlled Rectifiers 13 AC Voltage Regulators 14 DC Choppers 15 DC to AC Inverters Switched Mode 16 DC to AC Inverters Resonant Mode 17 DC to DC Converters - Switched-mode 18 DC to DC Converters - Resonant-mode 19 HV Direct-Current Transmission 20 FACTS Devices and Custom Controllers 21 Energy Sources and Storage: Primary Sources 22 Energy Sources and Storage: Secondary Sources 23 Inverter Grid Connection for Embedded Generation

24 Inductors and Transformers 25 Resistors 26 Capacitors

The 122 non-trivial worked examples cover the key issues in power electronics. BWW July 2008

BWW

CHAPTER 1 Basic Semiconductor Physics

and Technology

The majority of power electronic circuits utilise power semiconductor switching devices which ideally present infinite resistance when off, zero resistance when on, and switch instantaneously between those two states. It is necessary for the power electronics engineer to have a general appreciation of the semiconductor physics aspects applicable to power switching devices so as to be able to understand the vocabulary and the non-ideal device electrical phenomena. To this end, it is only necessary to attempt a qualitative description of switching devices and the relation between their geometry, material parameters, and physical operating mechanisms.

Typical power switching devices such as diodes, thyristors, and transistors are based on a monocrystalline group IV silicon semiconductor structure or a group IV polytype, silicon carbide. These semiconductor materials are distinguished by having a specific electrical conductivity, , somewhere between that of good conductors (>1020 free electron density) and that of good insulators (

Basic Semiconductor Physics and Technology 2

Electrons in n-type silicon and holes in p-type are called majority carriers, while holes in n-type and electrons in p-type are called minority carriers. In a given silicon material, at equilibrium, the product of the majority and minority carrier concentration is a constant: 2o o ip n n = (1.1) where po and no are the hole and electron equilibrium carrier concentrations. Therefore, the majority and minority concentrations are given by:

2

2

For an -type therefore and

For a -type therefore

io D o

D

io A o

A

nn n N pN

np p N nN

= =

= = (1.2)

These equations show that the number of minority carriers decreases as the doping level increases. The resistivity, , of doped silicon is ( )

1 1

n pq n p = = + (1.3)

where: = 1/ = conductivity, -1.cm-1 = 1/ = resistivity, .cm n = electron mobility, cm2/V-s p = hole mobility, cm2/V-s q = electron charge, C n = electron concentration, cm-3 p = hole concentration, cm-3

Figure 1.1. Elemental doped silicon.

Resistance of semiconductor materials is usually expressed in terms of sheet resistance, which is related to resistance as follows. The impurity depth xj, mobility , and impurity distribution N(x) are related to sheet resistance by

0

1/square

( )js xR

q N x dx= (1.4)

The average resistivity is s jR x = and given a length L and width W, as defined in figure 1.1, the resistance is given by

sL L LR RA t W W

= = = (1.5)

Example 1.1: Resistance of homogeneously doped silicon Silicon doped with phosphorous (ND = 1017 /cm3) measures 100m by 10m by 1m. Calculate the sheet resistance and resistance between opposite faces, assuming the electron mobility at this doping level is n = 720cm2/ V-s. Doping to produce a p-type material has a hole mobility of 40% that for electrons. Recalculate sheet resistance and resistance values. Solution

From equation (1.3), the resistivity, , of doped silicon is ( )

1 1

n pq n p = = +

Since n >> p in the n-type silicon

19 171 1

0.086cm1.6 10 720 10nq n

= = =

t

area

A=Wt

length L

width W

Power Electronics 3

For a length of 100m, the resistance is

4

4 4

100 100.086 8.6k

10 10 1 10Length LRArea W t

= = = =

From equation (1.5) the sheet resistance is given by

4

4

10 108.6k 860/square

100 10sWR RL

= = =

If the length is assumed to be one of the shorter dimensions, then for a length 10m or 1m, the resistance is 86 or 0.86, respectively, while the sheet resistance possibilities, depending on the thickness reference axis, are 86 /square and 8.6 /square. For a p-type material, the 40% decrease in mobility of holes p increases resistivity by a factor of 1/0.4 = 2.5. Each aspect resistance therefore increases by a factor 2.5, viz., increases to 21.5k, 215, and 2.15 for lengths 100m, 10m, and 1m, respectively. From equation (1.4) the sheet resistances are increased to 2.15k/square, 215/square, and 21.5/square.

The carrier concentration equilibrium can be significantly changed by irradiation by photons, the application of an electric field or by heat. Such carrier injection mechanisms create excess carriers.

If n-type silicon is irradiated by photons with enough energy to ionise the valence electrons, electron-hole pairs are generated. There is already an abundance of majority electrons in the n-type silicon, thus the photon-generated excess minority holes are of more relative and detectable importance. If the light source is removed, the time constant associated with recombination, or decay of excess minority carriers, is called the minority carrier hole lifetime, h. For a p-type silicon, exposed to light, excess minority electrons are generated and after the source is removed, decay at a rate called the minority carrier electron lifetime, e. The minority carrier lifetime is often called the recombination lifetime.

A difficulty faced by manufacturers of high-voltage, large-area semiconductor devices is that of

obtaining uniformity of n-type phosphorus doping throughout the usual high-resistivity silicon starting material. Normal crystal-growing (by liquid encapsulated, contactless, Czochralski crystal growth see section 1.19.3i) and doping techniques give no better than 10 per cent fluctuation around the wanted resistivity at the required low concentration levels (

Basic Semiconductor Physics and Technology 4

n

(a) (b)

step junction

n

(a) (b)

1.1 Processes forming and involved in forming semiconductor devices 1.1.1 Alloying At the desired region on an n-type wafer, a small amount of p-type impurity is deposited. The wafer is then heated in an inert atmosphere and a thin film of melt forms on the interface. On gradual, slow, cooling, a continuous crystalline structure results, having a step or abrupt pn junction as shown in figure 1.2. This process is not employed to form modern p-n junctions but can be used at the metallisation stage of wafer fabrication.

Figure 1.2. N-Si to A metal alloy junction: (a) cross-section where xj is the junction depth below the metal-semiconductor boundary and

(b) doping profile of the formed step junction. 1.1.2 Diffusion Diffusion, the movement of a chemical species from an area of high concentration to an area of lower concentration, is one of the two major processes by which chemical dopants are introduced into a semiconductor (the other process being ion implantation). The controlled diffusion of dopants into silicon to alter the type and level of conductivity of semiconductor materials is the foundation of forming a p-n junction and formation of devices during wafer fabrication, as shown in figure 1.3. It is used to form bases, emitters, and resistors in bipolar devices, as well as drains and sources in MOS devices. It is also used to dope polysilicon layers.

Figure 1.3. Diffused pn junction: (a) cross-section where xj is the junction depth below the silicon surface and (b) doping concentration profile.

The mathematics that govern the mass transport phenomena of diffusion are based on two concepts. First Concept Whenever an impurity concentration gradient, C/x, exists in a finite volume of a matrix substance (the silicon substrate in this context), the impurity material has a natural tendency to move in order to distribute itself more evenly within the matrix and decrease the concentration gradient. Given time, this flow of impurities eventually results in homogeneity within the matrix, causing the net flow of impurities to stop. The mathematics of this transport mechanism is based on the flux of material across a given plane is proportional to the concentration gradient across the plane. That is:

Power Electronics 5

( ), N x tJ Dx

= (1.6) where J is the flux,

D=KT is the diffusion constant or diffusivity for the material that is diffusing the solvent, m/s, N(x,t)/x is the concentration gradient. The diffusion constant of a material is also referred to as diffusion coefficient or diffusivity and is related to mobility by D = KT. It is expressed in units of length2/time, such as m2/hour. The negative sign of the right side of the equation indicates that the impurities flow to the lower concentration. Second Concept Equation (1.6) does not account for the fact that the gradient and local concentration of the impurities in a finite volume of material decreases with an increase in time, an aspect that is important to diffusion processes. The flux J1 of impurities entering a section of a material with a concentration gradient is different from the flux J2 of impurities leaving the same section. From the law of conservation of matter, the difference between J1 and J2 must result in a change in the concentration of impurities within the section, assuming that no impurities are formed or consumed in the section. The second concept states that the change in impurity concentration over time is equal to the change in local diffusion flux, or

( ),

N x t J

t x =

or, from the first concept, equation (1.6)

( )

( ),,

N x tD

xN x tt x

= (1.7) If the diffusion coefficient is independent of position, such as when the impurity concentration is low, then the second concept may be simplified to:

( ) ( )2

2

, ,

N x t N x tD

t x = (1.8)

There are two major ways by which to deposit impurities into a substance by thermal diffusion. In the first method, known as predeposition, a flux of impurities continuously arrives at the surface of the substrate such that the concentration gradient of the impurity remains constant at the surface of the substrate, as shown in figure 1.4b. In the second method, known as redistribution or drive-in diffusion, a thin layer of the impurity material is deposited on the substrate. In this case, the impurity gradient at the surface of the substrate decreases with time, as shown in figure 1.4c. The semiconductor diffusion process is usually performed in two steps: predeposition and then drive-in.

During predeposition, the impurity dopant is added to the wafer n-type silicon substrate. Predeposition is done in a diffusion furnace at temperatures around 1000 to 1250C. The dopant is introduced into the furnace, and may be in the form of a gas, solid, or liquid. Gaseous dopants are mixed with an inert carrier gas, such as nitrogen or argon, and introduced into the furnace. Solid dopants are often applied in a powder form. The solid is heated and a stream of carrier gas moves the dopant into the furnace. Liquid sources are used by bubbling an inert carrier gas through the liquid dopant, and the gas saturated with the liquid is added to the furnace. This compound breaks down as a result of the high temperature, and is slowly diffused into the substrate. The maximum impurity concentration occurs at the surface, tailing off towards the inside.

The wafers are then put into a second furnace at higher temperatures (about 1300C) to drive-in the dopant. The drive-in process usually occurs in an oxidizing atmosphere so that a protective layer of Si02 is grown over the diffused layer.

Table 1.1 Dopants and chemical reactions.

Dopant state Dopant type dopant chemistry p-type diborane B2H6 B2H6+302B203+H20

gas n-type arsine AsH3 phosphine PH3

p-type BBr3 4BBr3+3022B203+6Br2 liquid n-type AsC3, P0C3 4P0C3+3022P205+6C2 p-type BN

solid n-type As203, P205 2As203+3Si4As+3Si02

Basic Semiconductor Physics and Technology 6

Typical dopants and silicon chemical reactions are shown in Table 1.1, while common diffusion coefficients and activation energies, referenced to 0K, are shown in Table 1.2. The diffusion process is the only junction forming technique that is not applicable to silicon carbide wafer processing.

Figure 1.4. Diffusion processes: (a) pictorial representation of mechanism; (b) predeposition diffusion; and (c) drive in diffusion.

The doping profile is mathematically defined and is varied by controlling the vapour mixture concentration, the furnace temperature, and time of diffusion. If the source concentration is continuously replenished predeposition dose, thus maintained constant, the surface concentration is N(0,t) = Ns, and the initial concentration is N(x,0)=0, then the doping profile is given by a complementary error function, erfc.

( )

( )( )2

0

,2

21 1 1

2

where 2

s

u

s s s

xN x t N erfcDt

xN erf N erf u N e dDt

xuDt

= = = =

=

(1.9)

The area under the diffusion profile is the total amount of dopant diffused into the wafer:

( ) ( ) 2, 1.13s so

Q t N x t dx N Dt N Dt

= = = (1.10) The junction depth is where the doping profile N(x,t) equals the background doping NB level, that is

( ),2

jj s B

xN x t N erfc N

Dt = =

Rearranging, gives the junction depth xj as

12 Bjs

Nx Dt erfcN

= (1.11) If natural depletion of dopant occurs drive in, that is the initial dose S at the surface is not replenished, then the profile is an exponential function, which gives a Gaussian diffusion distribution.

( )2

4,xDtSN x t e

Dt=

(1.12)

where

( ), non-replenished inital surface doseo

N x t dx S

= = (1.13) The diffusion length, x = 2Dt, is an approximate measure of how far the dopant has diffused, which is the distance from the surface to where the concentration has fallen to 1/e.

Impurity diffusion

silicon dioxide silicon wafer

(a) (b) (c)

backgroundsubstrate

No or Ns

No

Predeposition Drive in

Power Electronics 7

The surface concentration, which is not replenished, diminishes with time, according to

( )0, SN tDt= (1.14)

The junction depth is where the doping profile N(x,t) equals the background doping NB level, that is

( ) 24, xDtj BSN x t e NDt= =

Rearranging, gives the junction depth xj as

( )0,

2 n 2 njBB

N tSx Dt DtNDt N

= =

A A (1.15) Diffusivity D varies with temperature according to

eaE

kToD D

= (1.16) where Do = diffusion coefficient (in cm2/s) extrapolated to infinite temperature Ea = activation or theshold energy in eV, which is not particularly temperature dependant. Table 1.2 Typical diffusion coefficients and activation energies at 0K.

Do Ea Element 0K cm2/s eV

boron B 1.0 3.50 phosphorous P 4.7 3.68 antimony At 4.58 3.88 arsenic As 9.17 3.99 indium In 1.20 3.50

Example 1.2: Constant Surface Concentration diffusion - predepostion For a constant-source boron diffusion into n-type 1015 cm-3 silicon at 1000C, the surface concentration is maintained at 1019 cm-3 and the diffusion time is 1 hour. Find

i. Total amount of dopant diffused, Q(t) and the gradient at x = 0 and ii. The gradient and location (junction depth) where the dopant concentration reaches 1015 cm-3.

Solution

Using data for boron in Table 1.2, equation (1.16) gives the diffusion coefficient of boron at 1000C as

53.05

14 28.614 10 127324 1.39 10 cm /saE

kToD D e e

= = = so the diffusion length is

14 61.39 10 3600 7.07 10 cmDt = =

i. The area under the diffusion profile from equation (1.10) is

( ) 19 6 13 -2

1923 -4

60

1.13 1.13 10 7.07 10 8.0 10 cm

107.98 10 cm

7.07 10

s

s

x

Q t N Dt

NdNdx Dt

=

= = = = = =

ii. From equation (1.9) rearranged, when NB = 1015 cm-3, xj is given by

151 1

19

6

102 2

10

2 7.07 10 2.75 0.389m

Bj

s

Nx Dt erfc Dt erfcN

= = = =

2

20 -44

0.389m

4.0 10 cmx

s Dt

x

NdN edx Dt

== =

Basic Semiconductor Physics and Technology 8

Example 1.3: Constant Total Dopant diffusion drive in Arsenic was pre-deposited by arsine gas, and the resulting dopant per unit area was 1014 cm-2. How long would it take to drive the arsenic in to xj = 1 m? Assume a background doping of Nsub = 1015 cm-3, and a drive-in temperature of 1200C. For As, assume Do = 24 cm2/s, and Ea = 4.08 eV at 1200C. Solution

From equation (1.16) the diffusion coefficient for arsenic at 1200C is

54.08

138.614 10 147324 2.602 10aE

kToD D e e

= = = Rearranging equation (1.12) gives

5

2 8 12 1.106 1010 4 n 1.04 10 njB

Sx Dt tN Dt t

= = = A A

That is n 23.2 19230 0t t t + =A An iterative solution gives t =1993.3s or approximately 33 minutes. Example 1.4: Constant Total Dopant diffusion drive in An arsenic constant-dose diffusion is performed with an initial dose of 1014 cm-2. The diffusion temperature is 1100C for 2 hours. The starting wafer had a p-type substrate background doping of 1017 cm-3. Find the concentration of the As at the surface and find the junction depth. Solution From Table 1.2

53.99

14 28.614 10 1100 2739.17 2.07 10 cm /saE

kToD D e e

+= = = Then the diffusion length is

14 52.07 10 7200 1.22 10 cmDt = = The surface concentration is

18

18 -3

50

104.6 10 cm

1.22 10s

ox

NdN Ndx Dt = = = = =

From equation (1.12) rearranged, the junction depth for Gaussian diffusions is

18 -3

517 -3

2 n

4.6 10 cm2 1.22 10 cm n

10 cm

0.467m

oj

B

Nx Dt

N

= =

=

A

A

1.1.3 Epitaxy growth - deposition Epitaxy or epitaxial growth is the process of depositing a non-volatile, thin solid layer typically 0.5 to 100 m, of single crystal material over a single crystal substrate, usually through chemical vapour deposition (CVD). The semiconductor deposited film is often the same material as the substrate, and the process is known as homoepitaxy, or simply, epi, as with silicon deposition on a silicon substrate. If the substrate is an ordered semiconductor crystal (that is mono-silicon, gallium arsenide), the process continues building on the substrate with the same crystallographic orientation, with the substrate acting as a seed for the deposition. If an amorphous/polycrystalline substrate surface is used, the film will also be amorphous or polycrystalline. A key feature of epitaxy is that a lightly doped layer of epitaxial silicon can be grown on top of a heavily doped silicon substrate, thus creating a layer of differing conductivity that can serve as an insulating layer or intrinsic buffer region. The chemical vapour deposition CVD (see section 1.2.1) of silicon epitaxy occurs in an epitaxial reactor that consists of a quartz induction heated reaction chamber into which a susceptor is placed. The susceptor provides two features:

mechanical support for the wafers and an environment with uniform thermal distribution.

Power Electronics 9

The technological method of introducing reactant gases with only the substrates heated inside a reactor is called Vapour Phase Epitaxy, a schematic of which is shown in figure 1.5. A possible fabrication process is as follows. A pre-cleaned, polished, almost perfect silicon crystal surface acts as a substrate for subsequent deposition. Usually hydrogen chloride is first used to etch the wafers. The pre-doped silicon is heated to about 1150C in a quartz reactor tube at atmospheric pressure. A hydrogen gas flow carrying a compound of silicon such as silicon tetrachloride SiC4 or silane SiH4 is passed over the hot substrate surface, and silicon atoms are deposited, growing a new continuous lattice. If phosphine (PH3) arsine (AsH3) or diborane (B2H6) is included in the silicon compound carrier gas flow of H2 and N2, a layer of the required type and resistivity occurs. Up to 100m of doped silicon can be grown on substrates for power devices at a high growth rate of about 1 m/min at 1200C. A very low crystalline fault rate is essential if uniform electrical properties are to be attained. Selective deposition, depending on the surface masking of the substrate, is possible.

Figure 1.5. Typical cold-wall vapour phase epitaxial reactor. There are four major chemical sources of silicon for epitaxial deposition:

silane, SiH4 silicon tetrachloride, SiC4; trichlorosilane, SiHC3; and dichlorosilane, SiH2C2.

Chemical reactions equations can describe the growth of epitaxial layers. Each of the chemical sources mentioned can be described by an over-all reaction equation that shows how the vapour phase reactants form the silicon epitaxial film. For example, the over-all pyrolytic reaction for silicon epitaxy by silane decomposition reaction is: ( )4 2 2 1000C to 1100CSiH Si H + (1.17) Hydrogen reduction of trichlorosilane is 3 2 3SiHC H Si HC+ +A A (1.18) Reduction of dichlorosilane is 2 2 2SiH C Si HC +A A (1.19) However, such over-all reaction equations do not describe the complete CVD process in regard to how the gas phase reactants interact or how the epi species are adsorbed on the substrate surface. For instance, the over-all reaction for the hydrogen reduction of silicon tetrachloride SiC4 to form a silicon epitaxial layer is as follows: ( )4 2 2 4 1150C to 1300CSiC H Si HC+ +A A (1.20) Yet, the intermediate chemical species such as SiHC3 and SiH2C2 are present during the silicon epitaxial growth:

4 2 33 2 2 2

SiC H SiHC HCSiHC H SiH C HC

+ ++ +

A A AA A A

2 2 2 2

3 2

2 2

2

SiH C SiC HSiHC SiC HC

SiC H Si HC

+ +

+ +

A AA A A

A A

These equations confirm that even if a given process is described by a single over-all reaction, the process is actually a combination of many simultaneous chemical reactions. The growth rate of an epitaxial layer depends on several factors:

the chemical sources; the deposition temperature; and the mole fraction of reactants.

gas inlet vent

RF induction heating coils

graphite susceptor

wafers

Basic Semiconductor Physics and Technology 10

Silicon epitaxy improves the performance of bipolar devices. By growing a lightly doped epi layer over a heavily-doped silicon substrate, a higher breakdown voltage across the collector-substrate junction is achieved while maintaining low collector resistance. Lower collector resistance allows a higher operating speed with the same current. Epitaxy is also used in IC fabrication. By fabricating a CMOS device on a thin (3 to 7 microns) lightly doped epi layer grown over a heavily-doped substrate, latch-up occurrence is minimized a phenomena applicable to power devices such as the MOSFET and IGBT. As well as improving the performance of devices, epitaxy also allows better control of doping concentrations of the devices. The layer can also be made oxygen and carbon free. The disadvantages of epitaxy include higher cost of wafer fabrication, additional process complexities, and problems associated with defects in the epi layer. 1.1.4 Ion-implantation and damage annealing Ion Implantation is the process of depositing chemical dopant species (atoms stripped of electrons) into a substrate by directly bombarding the substrate with high-energy ions of the chemical being deposited, as shown in figure 1.6. Diffusion and ion implant are the two major processes by which chemical species or dopants are introduced into a semiconductor such as silicon to form electronic structures. The advantage of ion implant over diffusion is its more precise control for depositing dopant atoms into the substrate (1011 to 1018 cm-2), giving excellent doping level uniformity and production repeatability. The implanted profile shown in figure 1.6b can be approximated by a Gaussian distribution function:

2 2

2 2

( ) ( )

2 2( ) e e2

p p

p p

x R x R

pp

Sn x N

= = (1.21) where S is the ion dose per unit area, p is the symmetrical standard deviation in the projected range of the implanted ions

Figure 1.6. Ion implantation: (a) pictorial representation of mechanism; (b) implanted ion distribution; and (c) implanting system.

Rp

Np

0.61 Np

distance into the material x

Rp+p Rp-p im

purit

y co

ncen

tratio

n

n

2

2( )

2( ) ep

p

x R

pn x N

=

ion beam

wafer

Si02

Si02

implant

gas source

ion source

ion source power supply

sourcediffusion pump

ion beam

analysermagnet

resolving aperture

accelerationtube

Y scan plates X scan plates

wafer targeting position

wafer feeder

Faraday cage

beam- line and end station diffusion

pumps

V

ground

(a) (b)

(c)

Power Electronics 11

The depth of average or mean projected range (peak) is at Rp along the axis of incidence, where the maximum concentration occurs.

ion beam current (A) implant time

implant areaqS

= (1.22)

The point where the diffused impurity profiles intersects the background concentration NB is the metallurgical junction depth, xj, where the net impurity concentration is zero. From equation (1.21)

2

2

( )

2e

2 n

j p

p

x R

B p

pj p p

B

N N

Nx R

N

=

= A (1.23)

where / 2p pN S = . Doping, which is the primary purpose of ion implanting, is used to alter the type and level of conductivity of semiconductor materials. It is used to form bases, emitters, and resistors in bipolar devices, as well as drains and sources in MOS devices. It is also used to dope polysilicon layers. Typically, a gaseous dopant is ionized by electric discharge or by heat from a hot filament. The ions are separated using an electromagnetic field that bends the positively-charged particles to a selected band. This ion band is then passed through a high-current accelerator. The high-velocity beam of ions is focused on the wafer, causing the dopant ions to strike the wafer surface and penetrate. Sometimes a mask is used to implant a designated pattern on the wafer. As with diffusion, ion implantation allows the formation of junctions by changing the conductivity characteristics of precise regions in the wafer. The basic procedure for ion implantation into silicon is as follows:

Ion impurities (B, P or As) are vaporised and accelerated by an electric field in a vacuum at high keV energies at the pre-doped silicon substrate, which is at room temperature. The ions penetrate the lattice to less than a few microns, typically 1m at about MeV. The resultant implanted doping profile is Gaussian, with the smaller ion like boron, penetrating deeper.

These high-energy atoms enter the crystal lattice and lose their energy by colliding with some silicon atoms before finally coming to rest at some depth. Adjusting the acceleration energy controls the average deposition depth of the impurity atoms. Heat treatment is subsequently used to anneal or repair the crystal lattice disturbances caused by the atomic collisions.

Every implanted ion collides with several target atoms before it comes to rest. Such collisions may involve the nucleus of the target atom or one of its electrons. The total power of a target to stop an ion, or its total stopping power S, is the sum of the stopping power of the nucleus and the stopping power of the electron. Stopping power is described as the energy loss of the ion per unit path length of the ion. Implantation energies are typically 10keV to 1MeV, giving ion distributions with depths of 10 nm to 10 m from doses vary from 1012 ions/cm2 for threshold voltage adjustment in MOSFETs to 1018 ions/cm2 for formation of buried insulating layers. The damage caused by atomic collisions and bombardment during high-energy ion implantation changes the material structure therefore electrical characteristics of the target substrate. Many target atoms are displaced, creating deep electron and hole traps which capture mobile carriers and increase resistivity. Annealing is therefore needed to repair the lattice damage and put dopant atoms in substitutional sites where they can be electrically active again. Silicon damage caused by ion implantation includes:

the formation of crystal defects such as Frenkel defects, vacancies, di-vacancies, higher-order vacancies, and interstitials;

the creation of local zones of amorphous material within the supposedly crystalline structure; and

formation of continuous amorphous layers as the localized amorphous regions grow and overlap.

The first two damage types are categorized as 'primary crystalline damage'. Restoring the ion-implanted substrate to its pre-implant condition requires the substrate being subjected to a reparative thermal process known as annealing. Ion implantation damage annealing has five major components:

electrical activation of the implanted impurities; primary crystalline damage annealing; annealing of continuous amorphous layers; dynamic annealing; and diffusion of implanted impurities.

Annealing is conducted in a neutral environment, such as in Ar or a N2 atmosphere in a stack furnace. Electrical activation of the implanted impurities refers to the process of increasing the electrical activity of newly implanted impurity atoms during annealing, which usually do not occupy substitutional sites after

Basic Semiconductor Physics and Technology 12

being implanted. Temperatures up to 500C remove trapping defects, releasing carriers to the valence or conduction bands in the process. Electrical activity decreases again at 500 to 600C, because of the formation of dislocations. Beyond 600C, electrical activation increases until a peak at 800 to 1000C. In summary, primary crystalline damage annealing consists of:

recombination of vacancies and self-interstitials in the low temperature range, up to 500C; formation of dislocations at 500 to 600C which can capture impurity atoms; and dissolution of these dislocations at 900 to 1000C.

Annealing of the continuous amorphous layers that extend to the surface occur by solid-phase epitaxy between 500 to 600C. The crystalline substrate beneath the amorphous layers initiates the recrystallization of the amorphous layers, with the regrowth proceeding towards the substrate surface. Factors affecting the recrystallization rate include crystal orientation and the implanted impurities. Amorphous layers that do not extend to the surface anneal differently, with the solid-phase epitaxy occurring at both amorphous-single crystal interfaces and the regrowth interfaces meeting below the surface. Dynamic annealing effects refers to the healing of implant damage while the implantation process is occurring. This takes place because the heat applied to the wafer during implantation makes the point defects more mobile. Diffusion of implanted impurities relates to the mass transport of implanted species across a concentration gradient within an implanted layer during the annealing process. The presence of implant damage makes this diffusion process more complex than what occurs in an undamaged single-crystal substrate. Diffusion of implanted impurities during annealing degrades devices that have shallow junctions or narrow base and emitter regions if the thermal processing is not rapid enough, particularly in the case of boron ion implantation. Example 1.5: Ion implantation For a 100 keV boron implant with a dose of S=51014 cm-2, calculate

i. the peak concentration if this concentration occurs at a depth of Rp = 0.31 m and the ion implant standard deviation is p = 0.07 m,

ii. the junction depth, if the substrate phosphorus background doping level is 1015 /cm3, and iii. the surface concentration.

Solution

i. From equation (1.21)

2

2

( )

2( ) e2

p

p

x R

p

Sn x

= Differentiation gives

2

2

( )

2

2

2( )e 0

22

p

p

x R

p

pp

x Rdn Sdx

= = which confirms that the maximum concentration occurs when x = Rp. Substitution into equation (1.21) gives the concentration n(x = Rp = 0.31 m) = 2.851018 cm-3. ii. The junction depth is given by equation (1.23), that is

18

15

2 n

2.85 100.31 0.07 2 n 0.31 0.28m

10

pj p p

B

Nx R

N=

= =

A

A

Two junctions are created, at 0.03 m and 0.59 m. iii. Since the ion implant has formed two junctions within the n-substrate, the surface concentration is dominated by the background doping level of the substrate, 1015 /cm3. The surface ion implant doping is given by equation (1.21)

22

2 20.31

2 18 14 32 0.07( 0) e 2.85 10 e 1.57 10 /cm2

p

p

R

p

Sn x = = = =

The n-type surface concentration is 1015 /cm3 1.571014 /cm3 = 8.41014 /cm3.

Power Electronics 13

1.2 Thin Film Deposition A thin film is a layer with a high surface-to-volume ratio. Thin films are extensively used to apply dopants and sealants to wafers and microelectronic parts, and can be a resistor, a conductor, an insulator, or a semiconductor. Thin films can be deposited with a thickness of between a few nanometre to about 100m. The film can subsequently be locally etched using processes described in the Lithography and Etching sections of this chapter, sections 1.5 and 1.6, respectively. Thins films behave differently from bulk materials of the same chemical composition in several ways. Thin films are sensitive to surface properties while bulk materials generally are not. Thin films are also more sensitive to thermo-mechanical stresses. Thin film integrity is influenced by the quality of its adhesion to and conformal coverage of the underlying layer, residual or intrinsic stresses after deposition, and the presence of surface imperfections such as pinholes. The adhesion of a thin film to the substrate or underlying layer is paramount to ensuring thin film reliability. A thin film that is initially adhering to the underlying layer may lift off after the device is subjected to thermo-mechanical stresses. Reliable thin film adhesion depends on the cleanliness of the surface upon which it is deposited. Optimum substrate roughness also affects thin film adhesion. An ultra-smooth substrate decreases adhesion tendency. A rough substrate on the other hand can result in coating defects, which can also lead to thin film adhesion failures. Regardless of the deposition process, thin films always have an intrinsic stress which can either be tensile or compressive. High residual stresses can lead to adhesion problems, corrosion, cracking, and deviations in electrical properties. Thus, proper deposition is critical to minimize intrinsic stresses in thin films. Deposition technology is classified into two reaction types, viz. chemical and physical: i. Depositions that results because of a chemical reaction:

Chemical Vapour Deposition (CVD) Electrodeposition Epitaxy Thermal oxidation

These processes exploit the creation of solid materials directly from chemical reactions in gas and/or liquid compositions or with the substrate material. The solid material is usually not the only product formed by the reaction. Byproducts can include gases, liquids and other solids. ii. Depositions that results because of a physical reaction:

Physical Vapour Deposition (PVD) Casting

Common for these processes is that the material deposited is physically moved onto the substrate. In other words, there is no chemical reaction which forms the material on the substrate. This is not completely correct for casting processes, though it is more convenient to classify them as such. Whether the process is physical or chemical, the processing depostion reactor uses either:

A cold wall system, where the heating process uses radio frequency or infra red heating, while A hot wall system uses a thermal heating resistive element or series of elements forming

heating zones. 1.2.1 Chemical Vapour Deposition (CVD) A fluid precursor undergoes a chemical change at a solid surface, leaving a solid layer. In this process, the substrate is placed inside a reactor to which a number of gases are supplied, as shown in figure 1.7. The fundamental principle of the process is that a chemical reaction takes place between the source gases. The product of that reaction is a solid material that condenses on all surfaces inside the reactor. CVD is capable of producing thick, dense, ductile, and good adhesive coatings on metals and non-metals such as glass and plastic. In contrast to PVD coating in the line of sight, CVD can simultaneously coat all surfaces of the substrate. The thin films from chemical deposition techniques tend to be conformal, rather than directional. CVD processes are used to produce a thin film with good step coverage. A variety of materials can be deposited, however, some form hazardous byproducts during processing. The quality of the material varies from process to process, however generally a higher process temperature yields a material with higher quality and fewer defects. They are generally not suitable for mixtures of materials. CVD processing is not possible for some materials; there simply is no suitable chemical reaction.

Basic Semiconductor Physics and Technology 14

Figure 1.7. Typical CVD processing reactor system. Chemical deposition is categorized by the phase of the precursor: Plating relies on liquid precursors, often a solution of water with a salt of the metal to be

deposited. Some plating processes are driven only by reagents in the solution (usually for noble metals), but the most important process is electroplating. It was not commonly used in semiconductor processing, but has resurfaced with the use of chemical-mechanical polishing techniques. 1 Conventional CVD coating processing requires a metal compound that will volatilize at a fairly

low temperature and decompose to a metal when it contacts the substrate at higher temperature. An example of CVD is the nickel carbonyl (NiC04) coating as thick as 2.5 mm on glass windows and containers to make them explosion or shatter resistant.

2 Diamond CVD coating processing is used to increase the surface hardness of cutting tools. The process is performed at the temperatures higher than 700C which softens most tool steels. Thus, the application of diamond CVD is limited to materials which do not soften at this temperature, such as cemented carbides.

3 Plasma-assisted CVD coating processing is performed at lower temperature than diamond CVD coating. Diamond coatings or silicon carbide barrier coatings are applied on plastic films and semiconductors, including sub-m semiconductors.

Chemical solution deposition uses a liquid precursor, usually a solution of organometallic powders

dissolved in an organic solvent. This is a relatively inexpensive, simple thin film process that is able to produce stoichiometrically accurate crystalline phases.

Figure 1.8. Typical PECVD re