Design and Analysis of an Equal Split

Wilkinson Power Divider

Group #5

Bajee Bobba

Dominic Labanowski

Tom Zajdel

Cameron Zeeb

ECE 710

12/01/2010

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Table of Contents Introduction ……………………………………….….………..………..………… 3

Design Procedure …………….………..……………….……..……...…...…………. 3

Simulation and Optimization ………………………..………..………….……….... 4

Experimental Results and Analysis ………………………………………………….. 7

Conclusion …………………………………………………………………………… 10

Appendix A: Design Proposal ……………………………………………………….. 11

Figures Figure 1: Ideal equal-split Wilkinson power divider in transmission lines ….…... 4

Figure 2: Final optimized ADS schematic ……………………………………..…. 5

Figure 3: Final microstrip layout …………………………………………......... 5

Figure 4: Photograph of final circuit ………..………..…………………..….…...... 6

Figure 5: Simulated versus Experimental results for reflection coefficient (S11). 7

Figure 6: Simulated versus Experimental results for power division (S12)…….. 8

Figure 7: Simulated versus Experimental results for isolation (S23) …………… 9

Tables Table 1: Ideal design parameters of Wilkinson power divider

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Introduction

In this project, an equal split Wilkinson power divider with a center frequency of 1.2 GHz

matched to 50 Ω transmission line was investigated. The circuit was designed and optimized

using ADS, then fabricated using copper microstrip lines with a Rogers Duroid substrate. The

circuit was then observed with a Network Analyzer, and these experimental results were

compared to the ADS simulation.

Design Procedure

To accomplish the design, ADS was used to design a power divider for the theoretically ideal

case. An ideal half-split power divider would divide incident power at port 1 equally between

ports 2 and 3. The S-matrix for the ideal Wilkinson divider is given below:

√ [

]

This ideal Wilkinson power divider would have perfect matching at all ports (S11 = 0, S22 = 0,

S33=0). Also, there would be perfect isolation between ports 2 and 3 (S23 = 0). The insertion loss

between ports 1 and 2 should be

√ , and the insertion loss between ports 1 and 3 should be

√

(|S12| = |S13| =

√ ). The implementation of the divider uses quarter wavelength lines that cause the

phase shift of π/2. Since the device is passive, the S-matrix is reciprocal.

Even-odd mode analysis can be used to derive the proper three-port circuit to use to create the

ideal Wilkinson power divider. This derivation can be found in the class notes. The results are

shown below, in Figure 1. Note: this figure was taken from the class notes.

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Figure 1: Ideal equal-split Wilkinson power divider

For this project, Z0 is 50 Ω and f = 1.2 GHz. This results in the following group of ideal values,

presented as Table 1:

Table 1: Ideal design parameters of Wilkinson power divider

Z0 2Z0 2Z0

(resistance) λ/4

50 Ω 70.71Ω 100 Ω 2460 mil

Simulation and Optimization

These values were used as the first-cut microstrip design in ADS. Note that the 2Z0 value was to

be implemented using a chip resistor. These values were then converted to microstrip line values

using LINECALC. These resulting microstrip widths and lengths were used in generating the

layout for the circuit. After several rounds of tweaking the circuit, the following schematic,

presented as Figure 2, was generated.

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Figure 2: Final optimized ADS schematic

This schematic was then converted into a layout, and the final layout is presented below, in

Figure 3.

Figure 3: Final microstrip layout

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The curved layout of the microstrip lines was essential to reduce the amount of coupling between

the splitting power lines. The lines had to be brought back together, however, in order to fit the

100 mil-long chip resistor between them. The lines were then immediately curved back away

from each other.

The simulated matching and isolation were not both completely centered at 1.2 GHz. It was

decided to optimize the centering for the matching (S11), because input power matching tends to

be more important for situations that require a power divider.

This circuit was used as the final design, and the microstrip realization was fabricated. SMA

connectors were attached to the three ports and soldered. A 100Ω chip resistor was also soldered

in its proper place. A picture of the final device is shown below in Figure 4.

Figure 4: Photograph of final circuit

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Experimental Results and Analysis

The circuit’s three main S-parameters were measured and compared against the ADS simulation.

The plots of these comparisons follow below, as Figure 5 (S11), Figure 6 (S12), and Figure 7

(S23). These indicate matching, power division, and port isolation, respectively.

Figure 5: Simulated versus Experimental results for reflection coefficient (S11)

The reflection coefficient performed as expected, centered at about 1.2 GHz, with an

approximate magnitude of -35 dB right at the center frequency, not far off from the simulated

-45 dB. The ideal reflection coefficient for good matching would be very low at the center

frequency. The response was rather uneven, which was likely due to noise in the measurement as

well as discontinuities in the SMA connections. The circuit had good matching.

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Figure 6: Simulated versus Experimental results for power division (S12)

The power division was fairly good. The simulated division was -3.05 dB at the center

frequency, which was close to the desired ideal -3 dB. The final physical realization of the circuit

fared slightly worse, at about -3.1 dB. This drop in power division is likely due to Ohmic losses

in the SMA connections as well as in the soldering connections.

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Figure 7: Simulated versus Experimental results for isolation (S23)

The port isolation would ideally be zero at the center frequency. The simulated isolation was

very close to being centered at 1.2 GHz, while the experimental results shifted about 50 MHz

lower. This shift could have been caused by the discontinuity between the 50 Ω microstrip

section and the 70.71 Ω section.

Here are the magnitudes of the measured S-matrix, compared to the magnitudes of the theoretical

S-matrix. They are quite close!

| |

√ [

]

| | [

]

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Conclusion

The physical circuit performed fairly well overall. There were small rough fluctuations in the

magnitude responses, likely due to measurement noise. The frequency centering of the circuit

was fairly good, with the isolation response drifting to a slightly lower frequency, most likely

due to the step discontinuity of the microstrip lines. The Wilkinson power divider did well with

power division, but seemed to have a .05 dB power loss, due to Ohmic losses in the system. With

more careful soldering, this design could be quite useful.

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APPENDIX A:

Design Proposal

Names: Bajee Bobba, Dominic Labanowski, Tom Zajdel, Cameron Zeeb

Date: 11/1/2010

Project Title: Design of an equal-split Wilkinson power divider

Design Goals:

1. Design of an equal-split (3dB) Wilkinson power divider with a characteristic impedance Z0= 50

Ohms and an operating frequency of 1.2 GHz.

2. Microstrip design will be laid out in ADS and then simulated and optimized in Momentum.

3. The microstrip layout will be generated with the layout tool.

4. The substrate used is Rogers Duroid 5880.

Design Procedure:

1. The first-cut design of this transformer will follow the example in section 7-3 in Pozar, where

two quarter wavelength lines with characteristic impedance Z0= 50*sqrt(2) Ohms are used to split

the power. A 100 Ohm shunt chip resistor will be connected between the two lines.

2. Linecalc will be used to calculate the dimensions of the microstrip lines for each section of the

transformer. The ADS circuit file of the transformer will be converted from transmission lines to

microstrips. MSTEP and MOPEN models will be used to account for discontinuities and the

resistor element will be realized with the MGAP element. Curves in the design will be accounted

for using the MCURVE model.

3. Momentum will be used to simulate the circuit designed in ADS, and the S-parameters S11, S23,

and S12 will be measured. Based on these simulation results, the microstrip dimensions in the

ADS layout will be tweaked to optimize the circuit’s performance.

4. The layout will be generated with ADS.

Measurement Results and Analysis:

S11, S23, and S12 will be measured and compared with the simulated results.

List of parts:

Size of Duroid circuit board: 2x4 inches

# of SMA launchers: 3

1 Chip resistor (100 Ohm)