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www.ilogix.com © I-Logix 2004 Tampere OO day 14/12/2004 What's New in UML 2.0 M.W.Richardson Lead Applications Engineer I-Logix UK [email protected]

What's New in UML2.0 - TUT · Microsoft PowerPoint - What's New in UML2.0.ppt Author: Mark Richardson Created Date: 12/16/2004 2:52:48 PM

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www.ilogix.com© I-Logix 2004 Tampere OO day 14/12/2004

What's New in UML 2.0

M.W.RichardsonLead Applications Engineer

I-Logix [email protected]

www.ilogix.com© I-Logix 2004 Tampere OO day 14/12/2004

What is UML?Unified Modeling LanguageComprehensive full life-cycle 3rd Generation modeling language

Standardized in 1997 by the OMGCreated by a consortium of 12 companies from various domainsI-Logix a key contributor to behavioral modeling

Incorporates state of the art Software and Systems A&D concepts Matches the growing complexity of real-time systems

Large scale systems, Networking, Web enabling, Data management

Extensible and configurableUnprecedented inter-disciplinary market penetrationUML 2.0 is latest version in the process of being released

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Advent of the UML

Mid 70s – Late 80s

Identifiable OO modelling languages began to appear

1989 1994

No Of Identifiable OO Modelling Languages Increases from <10 to >50

“Method Wars” Begin!

Methods begin to merge

1995

Grady Booch and Jim Rumbaugh begin unifying Booch & OMT

Ivar Jacobson (Objectory) join

them and add OOSE

1996

UML 0.9 & 0.91 Released

OMG Issues RFP

1997

RFP Response for UML 1.0

UML 1.1

1999

UML 1.3

UML 1.4

2001

UML 2.0

2004 2004+

UML 0.6 - Dr David Harel adds Statecharts

OOSE = Object Oriented Software Engineering MethodOMT = Object Modelling Technique

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UML 2.0 SubmissionsInfrastructure

Simplify and rework the “hairy underbelly” of the UMLAlign with MOF

SuperstructureContains most user-visible featuresImprove scalability and architectural supportImprove ability to model business workflowsAdd semantics of state machine inheritance

OCLObject Constraint Language is used in the definition of the UML itselfGeneral improvements of the OCL

Diagram InterchangeAdd ability to interchange diagram to the existing XMI

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UML 2.0 Diagrams

Communication Diagrams

Sequence Diagrams

Interaction Diagrams

Class Diagrams

DeploymentDiagrams

ComponentDiagrams

Object Diagrams

Structural Diagrams

State Machine Diagrams

Timing Diagrams

Activity Diagrams

Behavioral Diagrams

Use CaseDiagrams

PackageDiagramsStructure

Diagrams

Interaction Diagrams

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Ports & Ports & Structured ClassesStructured Classes

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How can we model the following in UML?

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PC System with UML 1.5

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Improved Design with UML 1.5

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Internal View of PC

Problem: Not obvious that the instance of Motherboard created by the PC is connected to the instances of USBCard and GraphicsCard created by the PC.

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PC System

Problem: No way to cleanly specify which instance of pc is connected to which instance of Keyboard

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UML 2.0 Ports

Ports are “named connection points”Ports allow a part to provide an interface across the boundary of its enclosing structured class without revealing to the client of the service the internal structure of the structured class

Client “talks to” the port without internal knowledge

Ports are “typed by” their interfacesProvided interfaces Required interfaces

These interfaces can consist of synchronous and / or asynchronous operations

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UML 2.0 Ports

ProvidedContract

RequiredContract

Port

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Devices

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PC System : Plug & Play

Connector

PartStructured

Class

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PC InternalsRelay Port

Behavioral Port

Note here that the PC actually does nothing, all the external ports are connected to internal parts.

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Things to Remember about PortsPorts are optional!

There is NOTHING you can do with ports that you can’t do without them

Ports enforce encapsulation of internal partsParts can publish services across the boundary of their owning composite classes without revealing the to the client of the service which part offers itParts are typed by interfaces

• Compatible ports are “conjugates” – one offers, the other requires the same or compatible interface

• Sub-classed provided interfaces are compatible with super-class required interfaces

Ports are a design patternAll design patterns have pros and cons

• Con: Ports are instantiable and so take up some amount of memory and require some amount of execution time

Ports are implemented by classes that provide behavioral delegation services to their clients

Ports can have multiplicity and can be connected dynamically

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Ports Example

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Easy testing

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White Box View

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SequenceSequenceDiagramsDiagrams

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Messaging between structured classes

Horizontal Decomposition

InteractionOccurrence

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Messaging between structured classes

Vertical Decomposition

Part Decomposition

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Interaction Fragment Operatorssd – named sequence diagramref – reference to “interaction fragment”loop – repeat interaction fragmentopt – optional “exemplar”alt – selectionpar – concurrent (parallel) regionsseq – partial ordering (default) (aka “weak”)strict – strict orderingcriticalRegion – identifies “atomic” fragmentsassert – required (i.e. causal)neg – “can’t happen” or a negative specificationIgnore/consider – messages outside/inside causal stream

Flow of Control

Naming

Ordering

Causality

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Interaction Operator : Loop

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Interaction Operator : Opt

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Interaction Operators : Critical Region

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InheritedInheritedState State BehaviourBehaviour

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Inherited State BehaviorAssumes Liskov substitution principle for generalization:

You canAdd new statesElaborate sub-states in inherited statesAdd new transitions and actions

You cannotDelete inherited transitions or states

A subclass must be freely substitutable for the super-class in any operation

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Example: Generalization

Modified action list

New sub-states and transitions

New and-states

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ActivityActivityDiagramsDiagrams

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Activity Diagrams

Joint 1 to a Joint 2 to b Openmanipulator

Compute jointangles (a,b)

Grasp Object

Rotatemanipulator

interruptablesection

event reception

swim lane representingthe objects executing

the activities nestedwithin

graspAt

Joint_1 Joint_2 Joint_3

Emergency Stopinterrupting edge

Position

Proximity Alert

Interruptingedge

Event receptionor exception

Interruptibleregion

Inputpin

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TimingTimingDiagramsDiagrams

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Timing Diagram

Time

Sending::Low

Sending::High

Receving::Low

Receiving::High

Sending

Receiving

Idle

Coil Driver

Transceiver

transmit(value)

Tristate

MonitorInitializing

Acquiring

ReportingIdle

send(value)

send(value)

tm(bitTime)

{1 ms +/- 0.2ms}

{3 ms +/- 0.2ms}

evDone

A Timing Diagram shows the timing between objects.

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UML 2.0 Summary

Makes it easier to construct scaleable architecturesMakes exchange of models between tools possibleFacilitates use of UML by Systems Engineers