Week 9a, Slide 1EECS42, Spring 2005 Prof. White

Week 9a

OUTLINE• MOSFET ID vs. VGS characteristic • Circuit models for the MOSFET

– resistive switch model– small-signal model

Reading• Rabaey et al.: Chapter 3.3.2• Hambley: Chapter 12 (through 12.5); Section 10.8

(Linear Small-Signal Equivalent Circuits)

Week 9a, Slide 2EECS42, Spring 2005 Prof. White

MOSFET ID vs. VGS Characteristic

Long-channel MOSFETVDS = 2.5 V > VDSAT

Short-channel MOSFETVDS = 2.5 V > VDSAT

• Typically, VDS is fixed when ID is plotted as a function of VGS

Week 9a, Slide 3EECS42, Spring 2005 Prof. White

MOSFET VT Measurement• VT can be determined by plotting ID vs. VGS,

using a low value of VDS :

DSDS

TGSnD VVVVLWkI ⎥⎦

⎤⎢⎣⎡ −−′=

2ID (A)

VGS (V)VT

0

Week 9a, Slide 4EECS42, Spring 2005 Prof. White

Subthreshold Conduction (Leakage Current)• The transition from the ON state to the OFF state

is gradual. This can be seen more clearly when ID is plotted on a logarithmic scale:

• In the subthreshold(VGS < VT) region,

This is essentially the channel-source pn junction current.(n, the emission factor, is between 1 and 2)(Some electrons diffuse from thesource into the channel, if thispn junction is forward biased.)

⎟⎠⎞

⎜⎝⎛∝

nkTqVI GS

D exp

VDS > 0

Week 9a, Slide 5EECS42, Spring 2005 Prof. White

Qualitative Explanation for Subthreshold Leakage

• The channel Vc (at the Si surface) is capacitivelycoupled to the gate voltage VG:

ox

dep

ox

depox

CC

CCC

n +=+

=⇒ 1

Cox

Cdep+

Vc

–

VG

Using the capacitive voltage divider formula:

p-type Si

n+ poly-Si

n+ n+

depletion region

VG

CIRCUIT MODELDEVICE

The forward bias on the channel-source pnjunction increases withVG scaled by the factor Cox / (Cox+Cdep)

VDG

depox

oxc V

CCCV ∆+

=∆

Adep

Sidep NW

C 1∝=

ε

Wdep

Week 9a, Slide 6EECS42, Spring 2005 Prof. White

Slope Factor (or Subthreshold Swing) S• S is defined to be the inverse slope of the log (ID)

vs. VGS characteristic in the subthreshold region:

VDS > 0

1/S is the slope

)10ln(⎟⎟⎠

⎞⎜⎜⎝

⎛≡

qkTnS

Units: Volts per decade

Note that S ≥ 60 mV/decat room temperature:

mV 60)10ln( =⎟⎟⎠

⎞⎜⎜⎝

⎛q

kT

Week 9a, Slide 7EECS42, Spring 2005 Prof. White

VT Design Trade-Off(Important consideration for digital-circuit applications)

• Low VT is desirable for high ON currentIDSAT ∝ (VDD - VT)η 1 < η < 2

where VDD is the power-supply voltage

…but high VT is needed for low OFF currentLow VT

High VT

IOFF,high VT

IOFF,low VT

VGS

log IDS

0

Week 9a, Slide 8EECS42, Spring 2005 Prof. White

The MOSFET as a Resistive Switch• For digital circuit applications, the MOSFET is

either OFF (VGS < VT) or ON (VGS = VDD). Thus, we only need to consider two ID vs. VDS curves:1. the curve for VGS < VT

2. the curve for VGS = VDD

ID

VDS

VGS = VDD (closed switch)

VGS < VT (open switch)

Req

Week 9a, Slide 9EECS42, Spring 2005 Prof. White

Equivalent Resistance Req

• In a digital circuit, an n-channel MOSFET in the ON state is typically used to discharge a capacitor connected to its drain terminal:– gate voltage VG = VDD

– source voltage VS = 0 V– drain voltage VD initially at VDD, discharging toward 0 V

The value of Req should be set to the value which gives the correct propagation delay (time required for output to fall to ½VDD):

Cload

⎟⎠⎞

⎜⎝⎛ −≅ DDn

DSATn

DDeq V

IVR λ

651

43

( )2

2 TnDDn

DSATn VVLWkI −

′=

Week 9a, Slide 10EECS42, Spring 2005 Prof. White

Figure 0.1 CMOS circuits and their schematic symbols

==

+Vdd

+Vdd

Week 9a, Slide 11EECS42, Spring 2005 Prof. White

Typical MOSFET Parameter Values• For a given MOSFET fabrication process

technology, the following parameters are known:– VT (~0.5 V)– Cox and k′ (<0.001 A/V2)– VDSAT (≤ 1 V)– λ (≤ 0.1 V-1)

Example Req values for 0.25 µm technology (W = L):

How can Req be decreased?

Week 9a, Slide 12EECS42, Spring 2005 Prof. White

P-Channel MOSFET Example• In a digital circuit, a p-channel MOSFET in the

ON state is typically used to charge a capacitor connected to its drain terminal:– gate voltage VG = 0 V– source voltage VS = VDD (power-supply voltage)– drain voltage VD initially at 0 V, charging toward VDD

Cload

⎟⎠⎞

⎜⎝⎛ −≅ DDp

DSATp

DDeq V

IVR λ

651

43

VDD

0 ViD

( )2

2 TpDDp

DSAT VVLWk

I −′

−=

Week 9a, Slide 13EECS42, Spring 2005 Prof. White

Common-Source (CS) Amplifier

• The input voltage vs causes vGS to vary with time, which in turn causes iD to vary.

VDD

RD

+

vOUT = vDS

−

+vIN = vGS

−

+–VBIAS

vs− +

iD

• The changing voltage drop across RD causes an amplified (and inverted) version of the input signal to appear at the drain terminal.

Week 9a, Slide 14EECS42, Spring 2005 Prof. White

Notation• Subscript convention:

VDS ≡ VD – VS , VGS ≡ VG – VS , etc.

• Double-subscripts denote DC sources:VDD , VCC , ISS , etc.

• To distinguish between DC and incremental components of an electrical quantity, the following convention is used:– DC quantity: upper-case letter with upper-case subscript

ID , VDS , etc.– Incremental quantity: lower-case letter with lower-case subscript

id , vds , etc.– Total (DC + incremental) quantity:

lower-case letter with upper-case subscriptiD , vDS , etc.

Week 9a, Slide 15EECS42, Spring 2005 Prof. White

Load-Line Analysis of CS Amplifier• The operating point of the circuit can be determined

by finding the intersection of the appropriate MOSFET iD vs. vDS characteristic and the load line:

DSDDDD viRV +=

vGS (V)

vDS (V)

iD (mA) load-line equation:

Week 9a, Slide 16EECS42, Spring 2005 Prof. White

Voltage Transfer Function

(1): transistor biased in cutoff region(2): vIN > VT ; transistor biased in saturation region(3): transistor biased in saturation region(4): transistor biased in “resistive” or “triode” region

Goal: Operate the amplifier in the high-gain region, so that small changes in vIN result in large changes in vOUTvIN

vOUT

Week 9a, Slide 17EECS42, Spring 2005 Prof. White

Quiescent Operating Point

• The operating point of the amplifier for zero input signal (vs = 0) is often referred to as the quiescent operating point. (Another word: bias.)– The bias point should be chosen so that the output

voltage is approximately centered between VDD and 0 V.– vs varies the input voltage around the input bias point.

Note: The relationship between vOUT and vIN is not linear; this can result in a distorted output voltage signal. If the input signal amplitude is very small, however, we can have amplification with negligible distortion.

Week 9a, Slide 18EECS42, Spring 2005 Prof. White

Bias Circuit Example

VDD

RD

R1

R2

Week 9a, Slide 19EECS42, Spring 2005 Prof. White

Rules for Small-Signal Analysis

• A DC supply voltage source acts as a short circuit– Even if AC current flows through the DC voltage source,

the AC voltage across it is zero.

• A DC supply current source acts as an open circuit– Even if AC voltage is applied across the current source,

the AC current through it is zero.

Week 9a, Slide 20EECS42, Spring 2005 Prof. White

NMOSFET Small-Signal Model

gmvgs ro

+

vgs

−

id

( )

DDS

Do

TGSGS

Dm

dsogsmdsDS

Dgs

GS

Dd

Ivig

VVkLW

vig

vgvgvviv

vii

λ≅∂∂

≡

−′≅∂∂

≡

+=∂∂

+∂∂

=

S

D

S

G

transconductance

output conductance

+

vds

−

Week 9a, Slide 21EECS42, Spring 2005 Prof. White

Small-Signal Equivalent Circuit

gmvgs ro

+

vgs

−

RD

+

vout

−

R1 R2

G

S S

D

+

vin

−

( )

( )Domin

outv

Dogsmout

RrgvvA

Rrvgv

||

||

−==

−=

voltage gain