Lecture 07 - 1ELE2110A © 2008

Week 7: Common-Collector Amplifier,MOS Field Effect Transistor

ELE 2110A Electronic Circuits

Lecture 07 - 2ELE2110A © 2008

Topics to cover …Common-Collector AmplifierMOS Field Effect Transistor– Physical Operation and I-V Characteristics of

n-channel devices– Non-ideal effects– P-channel devices and other types

Reading Assignment: Chap 14.1 – 14.5 of Jaeger and Blalock , orChap 5.7 of Sedra & SmithAndChap 4.1 – 4.4 of Jaeger and Blalock orChap 5.1-5.2 of Sedra & Smith

Lecture 07 - 3ELE2110A © 2008

Common-Collector Amplifier

AC/Small signal equivalent

21

74

||||

RRRRRR

B

L

==

OutputInput

AC ground

Load

Source

Also called “Emitter follower”

Lecture 07 - 4ELE2110A © 2008

Terminal Voltage Gain

LRmgL

RmgACC

vt

LRrL

R

bvov

ACCvt

+≅

++

+==

∴

1

)1(

)1(

βπ

β

1>>βfor

In most C-C amplifiers,

Output voltage at emitter follows input voltage, hence the circuit is named Emitter Followers.

1≅∴ACCvt

1>>LRmg

Lecture 07 - 5ELE2110A © 2008

Input Resistance and Overall Voltage Gain

Input resistance looking into the base terminal is given by

LRrib

vRCC

in )1( ++== βπ

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

⎟⎟⎠

⎞⎜⎜⎝

⎛

⎟⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜⎜

⎝

⎛

⎟⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜⎜

⎝

⎛

⎟⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜⎜

⎝

⎛

+=

===

RCCinBRIR

RCCinBR

ACCvt

ivb

vvtA

ivb

v

bvov

ivov

ACCv

Overall voltage gain is

Lecture 07 - 6ELE2110A © 2008

Example 1Problem: Find overall voltage gain.Given data: β=100, Q-point values: IC=245uA, VCE=3.64V, gm=9.8mΩ−1, rπ=10.2kΩ.Assumptions: Small-signal operating conditions.Analysis:

MΩkΩ.kΩ.L)R(βπrinR

kΩ.RRLR

kΩRRBR

17.1)210(1012101

51174

10421

=+=++=

==

==

99101

.

LRmgL

RmgvtA =

+= 9560.

RCCinBRIR

RCCinBR

vtAvA =+

=

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

⎟⎟⎠

⎞⎜⎜⎝

⎛

AC ground

Lecture 07 - 7ELE2110A © 2008

Input Signal RangeFor small-signal operation, magnitude of vbe < 5 mV.

If , vb can be increased beyond 5 mV limit.

Emitter followers can be used with relatively large input signals!

πrL

RLRmg

bv

L)R(βπr

πrbv

πirbev++

=++

==

11

)VLRmg(.βL

RLRmg.

bv

+≅

++≤⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛

⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛

10050

10050

1>>LRmg

Lecture 07 - 8ELE2110A © 2008

Output Resistance

111 ++

+=

+

+≅∴

+−−

+=−−=

⎟⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜⎜

⎝

⎛

βth

R

βπr

βπrth

RRCC

out

πrthR

xvβ

πrthR

xvβiixi

11

1 ++≅

++=

ββα th

R

mgth

R

mgRCC

out

BIth RRR ||=

11

++≅

βbasetoconnectedR

mgRCCout

Small output resistance!

Lecture 07 - 9ELE2110A © 2008

Example 2Problem: Find output resistance.Given data: β=100, Q-point values: IC=245uA,VCE=3.64V, gm=9.8mS, rπ=10.2kΩ, rο=219kΩ.Assumptions: Small-signal operating conditions.Analysis:

Ω=+=+

+= 120101

kΩ96.1mS80.9

990.01β

α thR

mgRCC

out

Lecture 07 - 10ELE2110A © 2008

Current Gain

Terminal current gain 11 +== βi

iACC

it

Lecture 07 - 11ELE2110A © 2008

Summary of Emitter FollowerVoltage gain: Close to unity.Input resistance: Large Output resistance: SmallInput signal range: relatively largeTerminal current gain: Large (β+1)

Excellent for use as a voltage buffer

Lecture 07 - 12ELE2110A © 2008

Voltage Buffer

VsRs

RL Vo ssLs

Lo vv

RRRv <<+

=

LOSiss

OL

Ls

iS

io

RRRRvAvRR

RAvRR

Rv

<<>>=≅

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

=

and for

Requirement of voltage buffer:- High input resistance- Low output resistance- Unity voltage gain

if sL RR <<

Without buffer:

With buffer:

Lecture 07 - 13ELE2110A © 2008

Summary of Single Stage BJT Amplifiers

ModerateLargeModerateSmallInput VoltageRange

1Non-inverting &

Large

Inverting & LargeInverting& Large

TerminalCurrent Gain

LargeLowLargeModerateOutput Resistance

LowLargeLargeModerateInput Resistance

Non-inverting & Large

1Inverting & moderate

Inverting& large

Terminal Voltage Gain

C-BC-CEmitter Degenerated C-E

C-E(RE=0)

Lecture 07 - 14ELE2110A © 2008

More Complicated Amplifier …

741 Op-amp - Built from single stage amplifiers

?

?

?

Lecture 07 - 15ELE2110A © 2008

Topics to cover …Common-Collector AmplifierMOS Field Effect Transistor– Physical Operation and I-V Characteristics of

n-channel devices– Non-ideal effects– P-channel devices and other types

Lecture 07 - 16ELE2110A © 2008

IntroductionMetal-Oxide Semiconductor Field-Effect Transistor (MOSFET) is the primary component in high-density chips such as memories and microprocessors

Compared with BJT, MOSFET has– Higher integration scale– Lower manufacturing cost– Simpler circuitry for digital logic and memory– Inferior analog circuit performance in general

Recent trend: more and more analog circuits are implemented in MOS technology for– lower cost– integration with digital circuits in a same chip (mixed-signal IC)

Lecture 07 - 17ELE2110A © 2008

Microphotograph ofa state-of-the-art CPU chip

Lecture 07 - 18ELE2110A © 2008

Structure of MOSFETFour terminals: – Gate, Source, Drain and

body

Two types– n-Channel (NMOS)– p-Channel (PMOS)

The minimum value of L is referred as the feature size of the fabrication technology.– E.g., 45nm is used for Intel’s

Core 2 processors.

symbol

Lecture 07 - 19ELE2110A © 2008

Low Gate Voltage

Body is commonly tied to groundWhen the gate is at a low voltage (VGS ~ 0):– P-type body is at low voltage– Source-body and drain-body diodes are OFF (reverse bias)– iG=0 (always), iDS = 0

Depletion region between n+ and p-type bulk– No current can flow, transistor is said in “Cutoff” mode

Lecture 07 - 20ELE2110A © 2008

Increase Gate Voltage

Vertical electric field establishedUnder the gate-oxide:– Holes (positive charges) repelled– Depletion region under gate oxide formed

Lecture 07 - 21ELE2110A © 2008

Further Increase Gate Voltage

Electrons (minorities in the p region) attracted by the electric field towards the gate, and stopped by the gate oxideA n-type inversion layer formed underneath the gate oxide when VGSreaches a certain value, called threshold voltage (Vt, or VTN for NMOS)The channel connects the S and D and now currents can flow between them

Lecture 07 - 22ELE2110A © 2008

Linear (Triode) Mode of OperationWhen vGS > Vt and a small vDS is applied– Current flows from D to S (Electrons flow from S to D)– iDS ∝ vDS

Increasing vGS above Vt increases the electron density in the channel, and in turn increases the conductivity between D & SSuch devices are called enhancement-type MOSFETIn this mode, transistor = a voltage controlled resistor

Lecture 07 - 23ELE2110A © 2008

vS

vG

vD

Increase Drain Voltage: Channel Pinch-Off

Increase vDS Decrease vGD less electrons at the drain side of the channelWhen vDS ≥ vGS – Vt

VGD ≤ Vtno channel exists at the drain side. The channel “pinches-off”

Lecture 07 - 24ELE2110A © 2008

vS

vG

vD

Saturation Mode of Operation

When channel pinches off, electrons still flows from S to D – Electrons are diffused from the channel to the depletion region near D,

where they are drifted by the lateral E-field to the D– Similar to a reverse-biased B-C junction in a BJT

Further increase of vDS no effect on the channel current is “saturated” and the transistor is in “Saturation Mode”In this mode, transistor = a voltage controlled current source

Lecture 07 - 25ELE2110A © 2008

Qualitative I-V Characteristic

Pinch Off

Lecture 07 - 26ELE2110A © 2008

I-V CharacteristicsIn the Linear region, drain current depends on– How much charge is in the channel– How fast the charge is moving

channel theacrossget tocarriers theit takes timechannel in the charge ofamount

=≡dtdQI

Lecture 07 - 27ELE2110A © 2008

Amount of Channel ChargeMOS structure looks like a parallel plate capacitorVGC is composed of two components– Vt to form the channel– (VGC-Vt) to accumulate negative

charges in the channel

( ) tDSGStGC

oxoxoxoxox

ox

channel

VvvVVV

tCWLCtWLC

CVQ

−−=−=

===

=

44344212/

/ where εε

Average gate-channel voltage

Ref: G.-Y. Wei, notes ES154, Harvard University

Lecture 07 - 28ELE2110A © 2008

Carrier VelocityCharge is carried by electrons.Carrier velocity v is proportional to the lateral E-field between source and drain

Time for carriers to cross the channel is

LvEEv

DS

nn

/mobility theis where

== µµ

DSnn vL

ELvLt

µµ

2

/ ===

Lecture 07 - 29ELE2110A © 2008

I-V Behavior: Linear ModeCombine the channel charge and velocity to find the current flow– Current = amount of charge in the channel / time it takes the carriers to

get across the channel

is a constant determined by the processing technology, and is denoted by K’nW/L is a main design parameter in integrated circuit design.

LWCKvvVvK

vvVvL

WC

Lv

vVvWLCt

Qi

oxnnDSDStGSn

DSDStGSoxn

DSnDStGSox

channelD

µ

µ

µ

=−−=

−−=

−−==

where)2/(

)2/(

)2/(2

⎥⎦⎤

⎢⎣⎡ −−= 2

21)()( DSDStGSoxnD vvVv

LWCi µ

)( oxnCµ

Lecture 07 - 30ELE2110A © 2008

I-V Behavior: Saturation ModeIf vGD ≤ Vt, channel pinches off near the drain– When vDS ≥ Vdsat = vGS – Vt

Now, drain voltage no longer increases with vDS

Putting vDS = vGS – Vt to the equation:

iD independent of vDS.

2)()(21 tGSoxnD Vv

LWCi −= µ for VGS > Vt and

VDS ≥ vGS - Vt

⎥⎦⎤

⎢⎣⎡ −−= 2

21)()( DSDStGSoxnD vvVv

LWCi µ

Lecture 07 - 31ELE2110A © 2008

Summary of NMOS I-V Characteristics

I-V relation

Conditions

SaturationTriodeCutoffRegion

tGSDS Vvv −< tGSDS Vvv −≥

2)('21

tGSnD VvL

WKi −=⎥⎦⎤

⎢⎣⎡ −−= 2

21)(' DSDStGSnD vvVv

LWKi

tGS Vv <

0=Di

tGS Vv ≥

tGS Vv <Cutoff region

Triode region

Saturation region

tGSDS

tGS

VvvVv

−<≥ and

tGSDS

tGS

VvvVv

−≥≥ and

oxnn CK µ='

Lecture 07 - 32ELE2110A © 2008

Ideal Square Law Model: ID vs VGS

MOS vs. BJT– Current is quadratic with voltage in MOS vs.– exponential relationship in BJT

Saturation mode of MOS corresponds to active mode of BJT

In saturation mode:

2)()(21 tGSoxnD Vv

LWCi −= µ

Lecture 07 - 33ELE2110A © 2008

Ideal Square-Law Model: ID vs VDS

NMOS

Lecture 07 - 34ELE2110A © 2008

Topics to cover …Common-Collector AmplifierMOS Field Effect Transistor– Physical Operation and I-V Characteristics of

n-channel devices– Non-ideal effects– P-channel devices and other types

Lecture 07 - 35ELE2110A © 2008

Non-ideal EffectsChannel length modulationBody effectTemperature influenceBreakdown

Lecture 07 - 36ELE2110A © 2008

where gate-to-channel voltage = VTN

Channel-Length Modulation

At vDS=vGS-VTN=VDSsat, – Channel pinch-off

As vDS increases beyond vDSsat, the pinch off point moves away from D towards S – The effective channel length L

is reduced by ∆L– ID increases– An effect similar to Early effect

in BJT

2

2

'⎟⎟⎠

⎞⎜⎜⎝

⎛ −= TNVGSvL

WnKDi

Lecture 07 - 37ELE2110A © 2008

Channel-Length ModulationThis effect is modeled by adding a term (1+λvDS) to the I-V equation:

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛ +−=DS

λvTNVGSvL

WnKDi 1

2

2

'

λ = channel length modulation parameter

Lecture 07 - 38ELE2110A © 2008

Body Effect

Channel-body can be regarded as a pn junction If channel-body junction is reverse-biased, – Depletion layer beneath the gate oxide becomes wider– Since the amount of negative charges in the ( channel +

depletion ) layer = amount of positive charges in the gate (Constant for a fixed gate-source voltage)

Channel depth is reduced– This is equivalent to an increase in the threshold voltage

Lecture 07 - 39ELE2110A © 2008

Body EffectNon-zero vSB changes threshold voltage:

where VTO= zero substrate bias for VTN (V)γ= body-effect parameter ( )2ΦF= surface potential parameter (V)

⎟⎟⎠

⎞⎜⎜⎝

⎛ −++= FFSBvTOVTNV φφγ 22

V

It follows that the body voltage controls iD.This phenomenon is known as the body effect.

(source-body voltage)

Lecture 07 - 40ELE2110A © 2008

Effects of TemperatureVt and mobility µ are sensitive to temperature:– Vt decreases by 2mV for every 1ºC rise in temperature– mobility µ decreases with temperature

Overall, increase in temperature results in lower drain currents

Lecture 07 - 41ELE2110A © 2008

Avalanche Breakdown

As VD is increased, the drain-body junction becomes reversed biased Breakdown occurs at voltages of 20 to 150V Rapid increase in the drain current

Normally, no permanent damage to the device

Lecture 07 - 42ELE2110A © 2008

Punch-through Breakdown

Whe VD is increased to a point, the depletion region surrounding D extends to the S Punch-through breakdown (about 20 V) Occurs in devices with short channelsNormally, no permanent damage to the device

Lecture 07 - 43ELE2110A © 2008

Gate Oxide Breakdown

When VGS exceeds about 30 V (or lower in modern IC technology)Gate oxide breaks down like in the case of a capacitor

Results in permanent damage to the device

Lecture 07 - 44ELE2110A © 2008

Input Protection

Since the MOSFET has a very small input capacitance and a very high input resistance, a small amount of static charges accumulating on the gate can cause the gate voltage to exceed the breakdown level– e.g., Electrostatic Discharge (ESD) from human body

Clamping diodes can be used in the I/O pins to protect the circuit from gate-oxide breakdown

to gatesInput Pin

Lecture 07 - 45ELE2110A © 2008

Topics to cover …Common-Collector AmplifierMOS Field Effect Transistor– Physical Operation and I-V Characteristics of

n-channel devices– Non-ideal effects– P-channel devices and other types

Lecture 07 - 46ELE2110A © 2008

P-channel MOSFET (PMOS)Similar to NMOS, but doping and voltages reversed– Body tied to highest voltage (Vdd) to prevent forward-biasing pn junctions– Source typically tied to Vdd too– Gate voltage high: transistor is OFF– Gate voltage low: transistor is ON when VGS < Vt (threshold voltage)

Inverted channel of positively charged holes– vGS and vDS are negative and Vt is also negative

Symbols

Lecture 07 - 47ELE2110A © 2008

PMOS I-V Characteristics|||| tGS Vv <Cutoff region

Triode region

Saturation region

||||and ||||

tGSDS

tGS

VvvVv

−<≥

|||| and ||||

tGSDS

tGS

VvvVv

−≥≥

Vt, vGS and vDS are negative.

oxpp CK µ=','L

WKK pp =where

SaturationTriode/LinearCutoff

2)(21

tGSpD VvKi −=⎥⎦⎤

⎢⎣⎡ −−= 2

21)( DSDStGSpD vvVvKi0=Di

µp is 2 or 3-times lower than µn

Lecture 07 - 48ELE2110A © 2008

Complementary MOS (CMOS) Technology

Complementary MOS or CMOS integrated-circuit technologies provide both NMOS and PMOS on a same IC

PMOS transistor is fabricated in the n well

Lecture 07 - 49ELE2110A © 2008

Depletion-mode MOSFETA depletion-type MOSFET has a built-in channel by fabrication– It is ON when no gate-source voltage is applied– Must apply a negative vGS to turn off device

Vt is negative for NMOS

enhancement

depletion

Lecture 07 - 50ELE2110A © 2008

MOSFET Circuit Symbols

(g) and(i) are the most commonly used symbols in VLSI logic design.

MOS devices are symmetric.

In NMOS, n+ region at higher voltage is the drain.

In PMOS p+ region at lower voltage is the drain