Wafer BondingJ. Electrochem. Soc., Vol. 145, No. 6, June 1998 The Electrochemical Society, Inc. 2199 using fast Fourier transform (FFT) methods reveals more information …

2198 J. Electrochem. Soc., Vol. 145, No. 6, June 1998 The Electrochemical Society, Inc.

Society Proceedings Series, Pennington, NJ (1981).112. J. W. Tester and H. S. Isaacs, J. Electrochem. Soc.,

122, 1438 (1975).113. G. T. Gaudet, W T. Mo, T. A. Hatton, J. W Tester, J.

Tilly, H. S. Isaacs, and R. C. Newman, AIChE J., 32,949 (1986).

114. U. Stemsmo and H. S. Isaacs, J. Electrochern. Soc.,140, 643 (1993).

115. G. S. Frankel, Corros. Sci., 30, 1203 (1990).

116. F. Hunkeler and H. Bohni, Corrosion, 37, 645 (1981).117. W K. Cheung, P. E. Francis, and A. Turnbull, Mater

Sci. For., 192-194, 185 (1995).118. G. S. Frankel, J. 0. Dukovic, B. M. Rush, V. Brusic,

and C. V. Jahnes, J. Electrochem. Soc., 139, 2196(1992).

119. G. S. Frankel, J. R. Scully, and C. V. Jahnes, J. Elec-trochem. Soc., 143, 1834 (1996).

120. H. W. Pickering, Corros. Sci., 29, 325 (1989).

Present and Future Role of Chemical Mechanical Polishing in

Wafer BondingC. Gui, M. Elwenspoek, J. G. E. Gardeniers, and P. V. Lambeck

MESA Research Institute, University of Twente, 2500 AE, Enschede, The Netherlands

ABSTRACT

Almost all direct wafer bonding has been conducted between chemical-mechanically polished substrates or betweenthin films that were present on top of the polished substrates. Introducing chemical mechanical polishing in the waferbonding will make a large range of materials suitable for direct wafer bonding, which has found and will find more, appli-cations in integrated circuits, integrated optics, sensors and actuators, and microelectromechanical systems.

IntroductionChemical mechanical polishing (CMP) is a technique

which is frequently used in the fabrication of high qualitylenses and mirrors and in the preparation of silicon wafersfor integrated circuits (IC) processes. Since the early 1990s,CMP is becoming a key process for planarizing interleveldielectrics (ILD) and/or planarizing metal layers in modemsubmicron (0.35 p.m) very large scale integrated (VLSI)circuits.1

However, we have also seen increasing applications ofCMP in direct wafer bonding (DWB) in the past few years.In this paper we are reviewing the role of CMP in DWB.

The adhesion phenomena between two solids have beenexplored for centuries.2 However, direct bonding of twosolids has not been applied on wafer scale until 1986. Thisprogress was mainly pulled by the market of silicon-on-insulators (SOl) wafers and pushed by the wafer polishingtechniques in IC industry, especially CMP From a techno-logical point of view, DWB would have been possible earli-er, since CMP was developed for wafer polishing well beforethe 1980s2,6

In this paper, the influence of surface morphology inDWB is reviewed first. Then the attainable wafer surfacesmoothness with the CMP processes is studied. In the thirdsection, present applications of CMP in wafer bonding forfabrication of novel sensors and actuators (S&A), inte-grated optical (10) devices, ICs, and microelectromechani-cal systems (MEMS) are surveyed. Finally, some specula-tions on the future role of CMP in DWB is addressed.

The Effects of Surface Morphology in DWBA typical DWB process includes three steps: wafer clean-

ing, room temperature bonding, and annealing. In order toachieve spontaneous, void-free room temperature bonding,wafer surfaces should be flat, clean, and extremely smooth.Among those surface topography parameters, the micro-roughness (or surface roughness in very small wavelength) isthe most important physical factor on DWB. Higher micro-roughness will result in voids that cannot be closed duringannealing processes,7 and cause higher stress in the bondinginterface.i Once the surface microroughness exceeds a criti-cal value, the wafer will no longer be bondable.

From the study of the wafer surface chemistry and theintermolecular or interatomic attraction mechanism dur-ing DWB, one can obtain preliminary impressions on therigid requirements of surface smoothness during wafer

bonding.912 In the case of hydrophilic silicon wafer bond-ing, during room temperature bonding, silicon wafers arebelieved to be mated together via hydrogen bonds betweenseveral (3 to 5) water clusters on top of the wafer surf aces.iSince the size of an OH group is about 1.0 A and the dis-tance between two hydrogen-bonded oxygen atoms in iceis 2.76 A, hydrophilic silicon surface separated up to 10 Acan be bridged together via three or more water clusters.10This analysis implies that the irregular protrusions on abondable surface should be smaller than 10 A. For hy-drophobic silicon wafer bonding, the requirement on thewafer surface smoothness will be more rigid. A cluster ofthree or more hydrogen-bonded HF molecules may bridgetwo surfaces separated up to 8 A.11 These studies revealedthe basic forces and binding energy in DWB. However, inorder to understand the role of surface morphology onDWB, surface contact mechanics must be used.

One of these studies is the gap closing theory. Con-sidering two contacted wafers that are separated by a gapof 2R long and 2h high, the condition for gap closing is13'5

h < 2.6(R5 /2)h/2I + if R << d + d2

R2h< if R>>d1+d2/ 2.4E1d1Ed&y(E1d + E2d.)

where Ay is the surface energy between the two contactedsurfaces, d1 and d2 are the thickness of the two wafers, Eand E2, are the Young's modules of the two materials.

The gap closing condition is very useful for studying theinfluence of particles, surface irregularities, and substratethickness on wafer bonding.1412 It can also be used as designrules of cavities formed by direct bonding of patterned orstructured wafers.1248 However this condition is less suit-able for predicting the bondability of a wafer surface.

Root mean square (rms) roughness and/or roughnessaverage (Ra) have been frequently used in characterizingthe bondability of a surface. This method, however, is limit-ed by the fact that both rms and Ra are strongly dependenton the scan length or area, while surface bondability hasbeen found to be not only dependent on the amplitude of thesurface topography but more importantly related to thewavelength of the surface scan. Analysis of the surfacetopography measured with atomic force microscopy (AFM)

[1]

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J. Electrochem. Soc., Vol. 145, No. 6, June 1998 The Electrochemical Society, Inc. 2199

using fast Fourier transform (FFT) methods reveals moreinformation on both the amplitude and the spatial frequen-cy of the wafer surface roughness. The most influential spa-tial frequency and its amplitude can be found by comparingthe power spectrum of a wafer surface with its DWB exper-imental performance.16'7 However, so far only an experi-mental model that describes the relation between theroughness spectrum and the bondability of silicon (100)wafer has been developed.'8

In order to derive a theoretical model that describes therelation between the adhesive ability of two surfaces, andthe surface morphology, surface adhesion force, and mate-rials properties, one can use the theory of the surface con-tact mechanics.'8 In this study, the elastic contact betweena nominally flat, rough surface and a nominally flat, per-fectly smooth surface is considered. The roughness of thenominally flat but rough surface is assumed to be a ran-dom series of asperities, which have spherical caps of thesame constant radius 13, with a Gaussian height distribu-tion. The adhesion parameters 1 /., which is defined as theratio of the standard deviation of the distribution ofasperity heights a to the extension which an asperity cansustain before the adhesion breaks, can be derived as'9

= 0.513——--131/3

where KE is the elastic constant defined by the Poissonratio, v, and v2, and the Young's modules, E, and E2, of thetwo materials

KE = .iT1_— + 1— vfl'1 E, E2

The relation between the relative pull-off force of thecontacted interface and the adhesion parameter has beenderived by Fuller and Tabor.'9 The relative pull-off forceneeded to separate the interface decreases by increasingthe adhesion parameter. Once l/..> 3, no force is neededto separate the interface.

If the material properties and surface adhesion force areknown, this model gives a necessary surface roughness con-dition for an unbondable surface. Since the material elasticproperties and the surface energy; together with the surfacetopography, are taken into account in evaluating waferbondability, this model is able to answer such questions aswhy a "soft" material, e.g., Si02, is bonded more easily thana "hard" material, e.g., SiN9, even though both of themhave the same surface roughness; or why hydrophobic bond-ing seems to be more sensitive to the surface microroughnessthan hydrophiic bonding.

As an example, we consider the bondability of a nomi-nally flat but rough single crystalline silicon (SCS) waferwhen bonded to a perfectly flat and smooth SCS wafer.Suppose that the rough SCS wafer surface topography hasa Gaussian distribution and the asperities have a meanradius of about 100 m. When conducting hydrophilicwafer bonding, the SCS wafer surface has a surface ener-gy of about 0.1 J m2. The two SCS wafer surfaces becomeadhesive when the standard deviation of the distributionof asperity heights is less then 2 nm.

Attainable Surface Smoothness with CMPCMPprocess and its principle—A schematic drawing of

the CMP setup is shown in Fig. 1. The polishing pad isplaced on top of the polishing plate, of which the temper-ature is adjustable. The wafer is held opposite to the poi-ishing pad by a chuck that is mounted onto the polishinghead. During polishing, the wafer is pressed onto the pol-ishing pad with adjustable pressure. Both the head andplate rotate and the head sweeps on the pad. At the sametime, the slurry is introduced onto the pad.

CMP makes use of both chemical etching and mechani-cal wearing, where the former ensures the atomic scaleremoval of the materials and the latter makes the overallwafer flatness possible.2022 The protrusions of different

Polishing Head

Fig. 1. Schematic of the CMP process.

[3]

[4]

heights on the wafer will experience different pressuresand subsequently different wearing and etching. This dif-ference in the removal rate will lead to smoothening of thesurface. Because the particles in the slurry are very smalland normally softer then the materials being polished,CMP can offer defect-free and mirror-like smooth sur-faces, having a rms roughness in subnanometer scale.

Attainable surface smoothness with CMP.—A completemodel of the CMP process is still not available.23 However,by studying the mechanics in CMP, one can obtain a prox-imal model on its kinetics. In this model, the contactsamong the polishing pad, abrasive particles, and the wafersurface being polished were considered as a two-bodywear problem,2° see Fig. 2. Considering one particle in con-tact with the wafer surface, the Hertzian penetration, R,,can be given by

2/3

= [5]

where 4) is the diameter of the abrasive particle, P is thepressure applied on all the particles, E is the Young's mod-ulus of the wafer being polished, and K is particle con-centration constant (unity for a fully filled close hexago-nal packing).

In the case of polishing of SCS wafers using colloidal sil-ica slurry and a polyurethane impregnated polishing pad, amaximum diameter of the spherical silica particles 4) = 100nm, an abrasive particle concentration constant K = 0.5,

pp

Particle ///

Fig. 2. Contact mechanics between particle and workpiece dur-ing polishing.


2200 J. Electrochem. Soc., Vol. 145, No. 6, June 1998 The Electrochemical Society, Inc.

and pressure P = 1.5 x 106 Pa, one gets a Hertzian pene-tration depth R, = 0.03 nm, which is 0.03% of the diameterof the abrasive particle. The penetration depth due to themechanical contact is so small that it can be neglected. Inpractice, no scratch can be found on the wafer surface afterCMP if the process is performed properly.

A comparison with other technologies.—In comparison,the ranges of average surface roughness produced by var-ious processing methods are listed in Table 1.24 From thistable, recalling the rigid surface flatness requirement inwafer bonding that was described in the previous section,one can conclude that CMP is the best, if not the only,technology for preparing smooth surfaces for DWB.

The Present Role of CMP in DWBAlmost all DWB so far has been done between prime

grade commercial silicon wafers or thin films that were pre-sent on such wafers. Recalling the manufacturing process ofcommercial silicon wafers, in which CMP is the last andmost important step in terms of the surface smoothness ofthe wafers, one will see the importance of CMP in waferbonding. Without CMP processes there will be no directbonding on wafer scale.

Different CMP processes for DWB.—Besides preparingcommercial prime grade silicon wafers by wafer manufac-turers, the CMP technology has also been used to performdifferent kinds of processes for DWB: surface preparationbefore bonding (including preconditioning, surface smooth-ening, planarization), and thinning the device wafer to thedesired thickness in fabricating SOl wafers.

Preconditioning.—Preconditioning using CMP is aprocess that activates wafer surfaces for DWB. CMP hasbeen used as a "soft polishing" step or a "fresh polishing"step.2327 Soft polishing refers to a process where wafers arepolished on a soft pad with only purified water, whilefresh polishing is a process in which a colloidal silica sus-pension is used for a few minutes. Instead of smootheningthe rough surfaces, both the soft polishing and fresh pol-ishing process expose "fresh" material by removing a fewnanometers of material, and therefore activates wafer sur-faces for direct bonding. The exact activation mechanismis still not clear. However there are suggestions to explainthe activation effect for preconditioning silicon. In thecase of CMP of silicon, wafer surfaces are predominantlyterminated by hydrogen after polishing.25 Other contami-nation is believed to be removed even with a very briefCMP step. After post-CMP cleaning (brushing, deionizedwater rinsing, followed by a RCA cleaning), the wafer sur-faces will be fully terminated with OH- groups which areinstrumental for hydrophilic bonding.

Smoothening.—Smoothening is a final polishing processthat makes generally flat but rough, unbondable surfaces tobe smooth and bondable. In this process, wafers are pol-ished on a soft pad with the final polishing slurries. Aftersmoothening, such rough or scratched wafer surfaces areflattened to defects-free, scratch-free smooth surfaces hav-ing a nns roughness in the subnanometer scale. Especially,final polishing provides surfaces with very low roughness ofsmall wavelength, which is essential for DWB. Smoothen-ing the rough surface is one of the primary functions ofCMP in DWB, which has been done since the early years ofDWB technology.29

The smoothening processes for different materials aresometimes very different. There is still a lot of work whichneeds to be done in order to optimize the CMP processes.For example, the CMP process for low pressure chemicalvapor deposition (LPCVD) polysilicon is quite differentfrom that for SCS. The removal rate of LPCVD polysiliconwas found to be more than five times higher than that ofSCS (100) wafer if the same process procedure is applied.30Improper polishing of LPCVD polysilicon will result insteps at the grain boundaries due to the different removalrates for various grain orientations.31 The removal ofLPCVD polysilicon does not have to be large; as soon as

Table I. Ranges of the average surface roughness produced byseveral polishing processes.

Note: U Average application, 0 Less frequent applicationa Data from Ref. 24.

the protruding particles on the LPCVD polysilicon surfaceare removed, the CMP process should be stopped. Longerpolishing will lead to the formation of pits on the polishedLPCVD polysilicon surface.

Planariration.—Planarization is a CMP process that flat-tens patterned or structured wafers with large topography(up to several micrometers). Stock removal pads and slur-ries are normally used in the planarization process. Afterplanarization, a smoothening, or final polishing process isnecessary before DWB can be applied. Planarization ofstructured wafer surfaces using CMP has been used fre-quently before and after bonding.32 Bonding of a stack ofstructured wafers, which has been used in manufacturingmicromechanical valves, was only possible with CMP33

Mechanical thinning of SOf.—Mechanical thinning, inwhich CMP is used as the last step after grinding and lap-ping, is the main fabrication technique for making SOlwafers having a device layer with a thickness above 1 jim.For details see Blackstone's review.34 It is worthwhile tomention that, during mechanical thinning, CMP is usednot only as planarization or smoothening process, but alsoas a tool to control the thickness and the uniformity of thedevice layer. The fact that different materials are polishedin different rates was used as the selective polishing orpolish stopper technique, with which a 60 nm thick top Silayer with a total thickness variation (TTV) of 8 nm acrossa 6 in. wafer has been made.35

ApplicationsGeneral bonding.—Bonding of materials other than sili-

con is stimulated by the applications of wafer bonding inIC, 10, S&A, and MEMS, where a wide spectrum of materi-als are used. In most situations, a CMP step is necessarybefore general bonding can be applied. Here, we should spe-cially mention Philips Research Laboratories. The bond-ability of a large range of materials that varies from metalsto semiconductors has been investigated using various pol-ishing techniques, including CMP.36 Recently, the bondabil-ity of several different silicon-based materials. e.g., P24 sili-con, KOH etched silicon, LPCVD polysilicon, LPCVDsilicon-rich nitride, PECVD silicon dioxide, has been stud-ied extensively,18 see also Fig. 3 and 4. Quartz-to-quartzdirect bonding has also been investigated using CMP33

Special SOf wafers—Several kinds of special SOlwafers have been realized using polished LPCVD polysili-con as an intermediate layer. Since LPCVD polysiliconafter CMP is smooth and bondable, it has been used fre-quently as a buffer layer to bond materials that are roughand difficult to polish.

Due to their low cost, 501 wafers using high temperaturechemical vapor deposition (HTCVD) polysilicon as a sub-strate material have been made by bonding of an oxidizedSi wafer to a polished LPCVD polysilicon layer which wasgrown on top of the HTCVD polysilicon substrate.36

1600 000 460 206 100 5 25 12 6 3

Roughness average (Ra), nm


J. tiecrrocnem. .OC., VOl. 14b, NO. b, ,iune niiti ) me Electrochemical Society, Inc. u1Silicon-on-diamond (SOD) wafers using diamond as the

insulating layer have been demonstrated using LPCVDpolysilicon as an intermediate bonding layer.39 The processof fabricating SOD wafers started with the deposition ofdiamond thin film on top of a device wafer. Then CVDpolysilicon was deposited on top of the diamond layer. Thepolysilicon layer was polished and bonded to an SCS han-dle wafer. Finally, the device layer of the SOD wafer wasthinned to the desired thickness.

Most recently, a novel process for fabricating SiC on in-sulator using wafer bonding has been demonstrated.Again, chemical-mechanically polished LPCVD polysiliconlayers were used as intermediate layers to transfer a singlecrystalline 3C-SiC film that grew on a silicon wafer to thetop of a SiO2 film that grew on top of a silicon wafer.4°

Laminated dielectric isolation (LDI) wafers.—Using anSCS-to-polysilicon direct bonding, Easter et al.32 andInoue et al.4' have demonstrated the fabrication of LDIwafers, which are useful substrates for power ICs. Com-pared with traditional dielectric isolation (DI) wafers, theLDI approach will reduce wafer warpage, increase wafersize, and decrease device surface area. Planarization ofpolysilicon for wafer bonding is a key step in fabricatingLDI wafers. As pointed out by Easter et al., achieving fullstrength SCS to polysilicon direct bonding at lower tem-perature, even at room temperature, will further realizethe benefits of LDI process. This will stimulate the studyof the polishing process for polysilicon, the role of polysil-icon surface roughness in bonding, and the stress compen-sation of polysilicon in bonding.

S&A MEMS.—Great freedom has been achieved in thedesign and fabrication of S&A, MEMS structures and de-vices in terms of fabrication processes and materials usedfor DWB using CMP.

Silicon-on-nitride (SON) wafers have been fabricatedfor making high-Tv superconductor bolometers.4243 AnLPCVD SiN9 insulating layer is used as a membrane thatprovides excellent thermal isolation because of its lowthermal conductivity. A thin SCS layer on top of theLPCVD SiN9 membrane is necessary for epitaxial growthof the superconducting layer. Only with CMP technology,SON wafers with thick LPCVD SiN9 insulating layers(from 200 up to 1200 nm) can be made by DWB. The larg-er thickness of the SiN9 enables the production of thebolometer on a larger membrane, thereby greatly improv-ing the bolometer performance. For instance, using CMPand DWB, SON wafers with a LPCVD SiN9 layer thickerthan 1 p.m have been made. A high-Ta superconductorbolometer has been made on a 4 mm2 Si,N9 membrane,with an effective area of 0.64 mm2. The measured electri-cal noise equivalent power (NEP) at 5 Hz is 3.7.10-12 WHz2. These values make this bolometer comparable tothe best high-T, superconductor bolometer reported sofar.44 Currently a membrane size of 16 mm2 is used.

For the fabrication of active pixel image sensors withhigh resolution and a high fill factor, a vertical intercon-nect technique has been developed using aligned waferbonding, where planarization of a tetraethylorthosilicate(TEOS) layer with high topography using CMP was a keystep in achieving a bondable surface.45

•i_ • ----. -.KOH etched Si surface before CMP

•J.•P Si surface before CMP

'II..h...

RMS3.6nm

LPCVD Si3N4 surface before CMP

PECVD Si02 surface before CMP

.1

Si surface after CMP

0.4 nm

LPCVD S13+XN4 surface after CMP

PECVD Si02 surface after CMP

Fig. 3. Surface roughness ofseveral silicon based materialsbefore and after CMP.

KOH etched Si surface after CMP

RMS=2.2 nni RMSO.2 nm


i. tiecrrocnem. ,oc., vol. I ', rio. o, june i o ' I ne pecirocnemicai ocIew, Inc.

Fig. 4. DWB interfaces be-tween several silicon basedmaterials.

The scanning system is the key component of the laserdisplay system. One new approach to make the scanningsystem is to fabricate silicon micromirror arrays. Planari-zation of CVD oxide together with DWB are key technolo-gies in fabricating such silicon micromirror arrays.46

Polishing and bonding of LPCVD polysilicon has beenused in making thin film microaccelerometers47 and mov-able micromechanical structures.3°

Integrated optics.—Recently CMP has been developedfor planarization of optical layers, in order to eliminatethe optical loss. However, together with DWB, the CMPtechnique also offers the possibility to freely combine dif-ferent optical materials. By doing so, novel 10 devices canbe realized, as well as optical loss-less interfaces.

For instance, CMP is used in bonding wafers with opti-cal materials for making nanomechanical 10 devices, suchas intensity modulators and phase modulators.48 These 10devices are based on the nanomechanical optical effects,where a movable mechanical element is placed on top of aplanar optical waveguide within the evanescent field. Bydoing so, the effective refractive index of a mode in thewaveguide can be modulated. The small gap between themechanical element and the optical waveguide can berealized by cavity etching and wafer bonding where CMPis the essential condition.

OullookAs more research groups become involved, it is expected

that CMP will play an increasing role in DWB. Using CMPin investigating the bondability of more materials rangingfrom metals, ceramics, to semiconductors, will be motivat-ed by their applications in S&A, MEMS, IC, and 10devices.

Polishing and bonding of metal substrates, such as tita-nium and stainless steel, is of interest for S&A and MEMSapplications. CMP has been successfully applied for Cu,Al, and W planarization for multilevel metallization in ICindustry. The knowledge obtained in metal planarizationin IC industry may be used for polishing a variety ofmetallic materials for wafer bonding.

Revealing the mechanism of CMP is particularly impor-tant for its applications in DWB, where much more typesof materials are involved than ever before. Because there isno satisfactory general model to describe the CMP process,

Si

l3ondiiig interfitce

Si3N4 IOnrn

Si

Bonding Interface

P [('V I)PoiSi

it is still a great challenge to characterize and optimize thepolishing processes for materials of different crystallo-graphic and compositional conditions that range frommonocrystalline, polycrystalline, amorphous, to composite.

CMP may be used to modify the wafer surfaces in orderto investigate the mechanical properties in the wafer bond-ing interface, such as bonding strength, microvoids, stress-es, and deformations. By doing so, more information re-garding the bonding mechanism may be revealed. In fact,such kind of research has already begun. In one of the mostrecent reports, CMP has been used as a tool to modify sili-con wafer surfaces in order to investigate the influence ofdifferent surface conditions on direct bonding.49

The lowest limit of substrate surface smoothness pre-pared with CMP process is not clear yet. It is not a diffi-cult task, however, for CMP to offer a surface having a rmsroughness at 1 A level nowadays. Even flat and smoothsurfaces may be achieved with further developed CMPtechniques, which will enable more atoms from both sur-faces being bonded to "meet" each other during precon-tact. This may find applications in full strength bonding ofmaterials at room temperature.

ConclusionsThe rigid requirement of the surface smoothness in

DWB makes CMP the best, and probably the only, processfor preparing wafer surfaces suitable for bonding. In fact,almost all DWB experiments so far were performed be-tween chemical-mechanically polished substrates or be-tween thin films on the polished substrates.

CMP has been developed as an on-site technology, allow-ing processes such as pre-conditioning, surface smoothen-ing, planarization, back thinning, and selective polishingfor wafer bonding. CMP makes a large range of materialssuitable for direct bonding. Therefore great freedoms havebeen achieved in designing and fabricating novel struc-tures or devices for IC, 10, S&A, and MEMS.

As an on-site process for wafer bonding, CMP is still atechnology under development. Since polishing of a largerange of materials is necessary, modeling and optimizingthe CMP process becomes much more complicated. Thismakes CMP more an art than a technology. Understandingthe polishing processes will stimulate more applications ofCMP in wafer bonding.

DWB between SCS and SCS after KOH etching and DWB between P' Si and LPCVD Si3N4 afterCMP CMP

DWB between Si02 and LPCVD Polysilicon after DWB between SCS and PECVD Si02 after CMPCMP


J. Electrochem. Soc., Vol. 145, No. 6, June 1998 The Electrochemical Society, Inc. 2203

It is expected that, in the near future, CMP will be usednot only as a technique for wafer bonding but also as atool for revealing the wafer bonding mechanism.

AcknowledgmentsS. Sanchez is acknowledged for critically reading this

manuscript. This research is sponsored by the DutchTechnology Foundation (STW).

Manuscript submitted September 22, 1997; revised man-uscript received February 10, 1998. This was Paper 2051presented at The Joint International Meeting of The Elec-trochemical Society and The International Society of Elec-trochemistry, Paris, France, August 31-September 5, 1997.

The University of Twente assisted in meeting the pub ii-cation costs of this article.

REFERENCES1. L. M. Cook and S. Leopard, in Proceedings of SEMI-

CON,'Korea Technical Symposium, p. 1 (1992).2. U. Gosele and H. Stenzel, in Proceedings of the 3rd

International Symposium on Semiconductor WaferBonding: Physics and Applications, C. E. Hunt, H.Baumgart, S. S. Iyer, T. Abe, and U. Gosele, Editors,PV 95-7, p. 33, The Electrochemical Society Proceed-ings Series, Pennington, NJ (1995).

3. J. B. Lasky, Appl. Phys. Lett., 48, 78 (1986).4. M. Shirobo, K. Furukawa, K. Fukuda, and K. Tanzawa,

J. Appl. Phys., 60, 2987 (1986).5. L. H. Blake and E. Mended, Solid State Technol., 13, 42

(1970).6. T. Karaki, S. Miyake, and J. Watanabe, Bull. Jpn. Soc.

Prec. Eng., 12, 207 (1978).7. T. Abe, A. Uchiyama, and Y. Nakazato, in Proceedings

of the 1st International Symposium on Semiconduc-tor Wafer Bonding: Science, Technology, and Appli-cations, U. Gosele, T. Abe, J. Haisma, and M. A.Schmidt, Editors, PV 92-7, p. 200, The Electrochem-ical Society Proceedings Series, Pennington, NJ(1992).

8. W. P. Maszara, B-L. Jiang, A. Yamada, G. A. Rozgonyi,H. Baumgart, and A. J. R. de Kock, J. Appl. Phys., 69,257 (1991).

9. R. Stengi, T. Tan, and U. Gosele, Jpn. J. Appl. Phys., 28,1735 (1989).

10. Q.-Y Thng and U. Gösele, J. Electrochem. Soc., 143,1773 (1996).

11. Q.-Y., Tong, T.-H. Lee, and U. Gösele, J. Elect rochem.Soc., 144, 384 (1997).

12. 0. Lichtenberger and J. Woltersdorf, Mater. Chem.Pliys., 44, 222 (1996).

13. Q.-Y Tong and U. Gbsele, Mater. Chem. Phys., 37, 101(1994).

14. U. Gösele and Q.-Y. Tong, in Proceedings of the 2ndInternational Symposium on Semiconductor WaferBonding: Science, Technology, and Applications, M.A. Schmidt. T. Abe, C. E. Hunt, and H. Baumgart,Editors, PV 93-29, p. 395, The Electrochemical Soci-ety Proceedings Series, Pennington, NJ (1992).

15. Q.-Y. Thng and U. Gosele, J. Electrochem. Soc., 142,3975 (1995).

16. M. Bergh, S. Bengtsson, and M. 0. Andersson, in Pro-ceedings of the 3rd International Symposium onSemiconductor Wafer Bonding: Physics and Appli-cations, C. E. Hunt, H. Baumgart, S. S. Iyer, T. Abe,and UI GOseIe, Editors, PV 95-7, p. 126, The Electro-chemical Society Proceedings Series, Pennington, NJ(1995).

17. B. Roberds and S. Farrens, in Proceedings of the 3rdInternational Symposium Semiconductor WaferBonding: Physics and Applications, C. E. Hunt, H.Baurngart, S. S. Iyer, T. Abe, and U. Gbsele, Editors,PV 95-7, p. 326, The Electrochemical Society Pro-ceedings Series, Pennington, NJ (1995).

18. C. Gui, H. Albers, J. G. E. Gardeniers, M. Elwenspoek,and P. V. Lambeck, Res. J. Micro Sys. Technol., 3, 122(1996).

19. K. N. G. Fuller and D. Tabor, Proc. R. Soc. London A,345, 327 (1975).

20. L. M. Cook, J. Non-Cryst. Solids, 120, 152 (1990).21. 5. Sivaram, R. Tolles, H. Bath, E. Lee, and R. Leggett,

Mater. Res. Soc. Symp. Proc., 260, 53 (1992).22. S. R. Runnels, J. Electrochem. Soc., 141, 1900 (1994).23. G. Nanz and L. E. Camilletti, IEEE Trans. Semicond.

Manuf act., SM-8, 382 (1995).24. Machinery's Handbook: A Reference Book for the

Mechanical Engineer Designei Manufacturing Engi-neer, Draftsman, Toolmakei and Machinist, ErikOberg and Robert E. Green, Editors, Industrial Press,New York (1992).

25. J. Haisma, G. A. C. M. Spierings, U. K. P. Biermann,and J. A. Pals, Jpn. J. Appl. Phys., 28, 1426 (1989).

26. G. A. C. M. Spierings and J. Haisma, in Proceedings ofthe 1st International Symposium on SemiconductorWafer Bonding: Science, Technology, and Applica-tions, U. Gösele, T. Abe, J. Haisma, and M. A.Schmidt, Editors, PV 92-7, p. 18, The Electrochemi-cal Society Proceedings Series, Pennington, NJ(1992).

27. E. E. King, D. H. Huang, P. Leonov, L. J. Palkuti, G. J.Campisi, H. L. Hughes, and D. J. Godbey, in Pro-ceedings of the 1st International Symposium onSemiconductor Wafer Bonding: Science, Technology,and Applications, U. Gbsele, T. Abe, J. Haisma, andM. A. Schmidt, Editors, PV 92-7, p. 467, The Electro-chemical Society Proceedings Series, Pennington, NJ(1992).

28. G. J. Pietsch, Y. J. Chabal, and G. S. Higashi, Surf. Sci.,331-333, 395 (1995).

29. Special Issue on Direct Bonding, Philips J. Res., 49, No.1-2, Elsevier, Amsterdam (1995).

30. C. Gui, H. Jansen, M. de Boer, J. W. Berenschot, J. G. E.Gardeniers, and M. Elwenspoek, in Proceedings ofTransducer '97, Chicago, June 16-19, p. 633, IEEE(1997).

31. B. L. Sopori, T. Nilsson, and M. McClure, J. Elec-trochem. Soc., 128, 215 (1981).

32. W. G. Easter, C. T. Jones, R. H. Shanaman, and C. A.Goodwin, in Proceedings of the 1st InternationalSymposium on Semiconductor Wafer Bonding: Sci-ence, Technology, and Applications, U. Gosele, T.Abe, J. Haisma, and M. A. Schmidt, Editors, PV 92-7,p. 223, The Electrochemical Society ProceedingsSeries, Pennington, NJ (1992).

33. M. A. Huff, M. S. Mettner, T. A. Lober, and M. A.Schmidt, in IEEE Solid-State Sensor and ActuatorWorkshop, Techn. Dig., Hilton Head, SC, p. 123,IEEE (1990).

34. S. Blackstone, in Proceedings of the 3rd InternationalSymposium on Semiconductor Wafer Bonding:Physics and Applications, C. E. Hunt, H. Baumgart,S. S. Iyer, T. Abe, and U. Gosele, Editors, PV 95-7,p. 56, The Electrochemical Society ProceedingsSeries, Pennington, NJ (1995).

35. Y. Arimoto, H. Hone, N. Higaki, M. Kojima, F. Sugima,F. Sugimoto, and T. Ito, J. Electrochem. Soc., 140,1138 (1993).

36. J. Haisma, B. A. C. M. Spienings, U. K. P Biermann,and A. A. van Gorkum, Appl. opt., 33, 1154 (1994).

37. P Rangsten, 0. Vallin, K. Ljungberg, and Y. Backlund,in Proceedings of the 4th International Symposiumon Semiconductor Wafer Bonding: Physics andApplications, U. Gösele, H. Baumgart, T. Abe, C.Hunt, and S. Iyer, Editors, PV 97-36, p. 187, TheElectrochemical Society Proceedings Series, Pen-nington, NJ (1998).

38. T. Abe, K. Ohki, K. Sunakawa, K. Yoshizawa, S. Tana-ka, andY. Nakazato, in Proceedings of the 2nd Inter-national Symposium on Semiconductor Wafer Bond-ing: Science, Technology, and Applications, M. A.Schmidt. T. Abe, C. E. Hunt, and H. Baumgart, Edi-tors, PV 93-29, p. 32, The Electrochemical SocietyProceedings Series, Pennington, NJ (1992).

39. M. Bergh, Private communications.40. K. N. Viond, C. A. Zorman, and M. Mehregany, in Pro-

ceedings of Transducer '97, p. 653, Chicago, IEEEElectron Devices Society (1997).

41. Y. Inoue, Y. Sugawara, and S. Kurita, IEEE Trans.Electron Devices, ED-42, 356 (1995).

42. C. A. Bang, J. P. Rice, M. I. Flik, D. A. Rudman, andM. A. Schmidt, J. Microelectromech. Sys., 2, 160(1993).

43. S. Sanchez, C. Gui, and M. Elwenspoek, in Proceedingsof MME 96, p. 16, Barcelona, IEEE Robotics andAutomation Society and ASME Dynamic Systemsand Control Division (1996).

44. S. Sanchez, M. Elwenspoek, C. Gui, M. J. M. E. de Niv-elle, R. de Vnies, P. A. J. de Korte, M. P Bruijn, J. J.Wijnbergen, W Michalke, E. SteinbeiB, T Heidenbiut,


2204 J. Electrochern. Soc., Vol. 145, No. 6, June 1998 The Electrochemical Society, Inc.

and B. Schwierzi, in Proceedings of MEMS '97, p. 506,Nagoya, IEEE Electron Devices Society and ASMEDynamic Systems and Control Division (1997).

45. C. Harendt, A. Schuhbauer, U. Apel, V Dudek, H.-G.Graf, B. Hofflinger, E. Penteker, in Proceedings of the4th International Symposium on SemiconductorWafer Bonding: Physics and Applications, U. Gosele,H. Baumgart, 1'. Abe, C. Hunt, and S. Iyer, Editors,PV 97-36, p. 501, The Electrochemical Society Pro-ceedings Series, Pennington, NJ (1998).

46. J. Kranert, C. Deter, Ti'. Gessner, and W. Dotzel, in Pro-ceedings of MEMS'98, p. 99, Heldelberg, IEEE Elec-tron Devices Society and ASME Dynamic Systemsand Control Division (1998).

47. V M. McNeil, M. J. Novack, and M. A. Schmidt, in

Technical Digest of the 7th International Conferenceon Solid-State Sensors and Actuators, p. 822, Yoko-hama (1993).

48. Gui, G. J. Veldhuis, '1'. M. Koster, P V Lambeck, J. W.Berenschot, J. G. E. Gardeniers, and M. Elwenspoek,in Proceedings of MEMS '98, p. 482, Heldelberg,IEEE Electron Devices Society and ASME DynamicSystems and Control Division (1998).

49. M. Bergh, S. Tiensuu, N. Keskitalo, and M. Forsberg,in Proceedings of the 4th International Symposiumon Semiconductor Wafer Bonding: Physics andApplications, U. Gosele, H. Baumgart, T. Abe, C.Hunt, and S. Iyer, Editors, Pv 97-36, p. 87, The Elec-trochemical Society Proceedings Series, Pennington,NJ (1998).


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Wafer BondingJ. Electrochem. Soc., Vol. 145, No. 6, June 1998 The Electrochemical Society, Inc. 2199 using fast Fourier transform (FFT) methods reveals more information …