$W$ -Band Amplifiers With 6-dB Noise Figure and Milliwatt-Level 170–200-GHz Doublers in 45-nm CMOS

692 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 3, MARCH 2012

-Band Amplifiers With 6-dB Noise Figure andMilliwatt-Level 170–200-GHz Doublers

in 45-nm CMOSBerke Cetinoneri, Student Member, IEEE, Yusuf A. Atesal, Student Member, IEEE, Andy Fung, Member, IEEE,

and Gabriel M. Rebeiz, Fellow, IEEE

Abstract—This paper presents low-noise -band amplifiersand milliwatt-level 170–200-GHz output doublers in 45-nm semi-conductor-on-insulator (SOI) CMOS technology. The transistorsare modeled using R/C extraction and full electromagnetic mod-eling. The measured of a 30 1- m transistor is 200–210 GHzat a bias current of 0.3–0.5 mA m. A three-stage -bandamplifier shows a record noise figure of 6.0 dB and a saturatedoutput power of 7.5–8.0 dBm with a power-added efficiency of9%, all at 95 GHz. The -band balanced doubler results in anoutput power of 1 mW at 180 GHz. A -band amplifier/ -banddoubler chip is also demonstrated, with a peak output powerof 0.5–1 mW at 170–195 GHz and a conversion gain from 2to 1 dB. This paper shows that 45-nm SOI CMOS, built fordigital and mixed-signal applications, results in state-of-the-artperformance at - and -band.

Index Terms—CMOS, frequency doubler, -band, low-noiseamplifiers, millimeter-wave integrated circuits, -band.

I. INTRODUCTION

M ILLIMETER-WAVE and terahertz applications ofSiGe and CMOS circuits have been an active research

topic over the past few years with applications in passive andactive imaging systems [1]–[3], short-distance high-data ratecommunications [4], and sensing. It is also possible to integratean efficient antenna in the SiGe and CMOS backend above100 GHz, thereby removing the need for transitions in and outof the wafer, which are very lossy. SiGe has led the way inthis area due to the high and more mature millimeter-waveback-end [5]–[7], and CMOS circuits are currently beingdemonstrated at 100–200 GHz [8]. Some essential components

Manuscript received May 09, 2011; revised July 31, 2011; accepted August09, 2011. Date of publication September 22, 2011; date of current versionMarch02, 2012. This work was supported by the C2S2 Focus Center, one of six re-search centers funded under the Focus Center Research Program (FCRP), aSemiconductor Research Corporation entity, and by the Director’s Research andDevelopment Fund under a contract with the National Aeronautics and SpaceAdministration (NASA).B. Cetinoneri and G. M. Rebeiz are with the Electrical and Computer Engi-

neering Department, University of California at San Diego, La Jolla, CA 92093USA (e-mail:[email protected]; [email protected]).Y. A. Atesal was with the Electrical and Computer Engineering Department,

University of California at San Diego, La Jolla, CA 92093 USA. He is now withthe Intel Corporation, Hillsboro, OR 97124 USA (e-mail:[email protected]).A. Fung is with the Jet Propulsion Laboratory (JPL), California Institute of

Technology, Pasadena, CA 91109 USA.Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TMTT.2011.2165964

Fig. 1. Block diagram of -to- -band multiplier chain.

are the low-noise amplifier for receive applications, and amedium power amplifier or a source that is capable of gener-ating milliwatt-level power in the 200-GHz range.CMOS amplifiers at 90–150 GHz have been demonstrated

using 90- and 65-nm technologies [9]–[11]. CMOS oscillatorswere also demonstrated at 200–600 GHz, but with very lowpower and poor phase noise [12], [13]. In fact, the phase noiseof fundamental and harmonic CMOS oscillators is not quotedin all published papers. We believe that a better way to obtainRF power at 200–400 GHz is to use a low phase-noise mil-limeter-wave oscillator with a high-performance phase-lockedloop (PLL) and an amplifier/multiplier chain (Fig. 1). Thefinal phase noise increases by , but it is still much lowerthan oscillators that are operating close to . Recently,45-nm semiconductor-on-insulator (SOI) CMOS, which wasdeveloped for digital and mixed-signal circuits with anof 485 GHz referenced to the transistor [14], was used toobtain low-noise amplifiers with a record noise figure (NF)of 3.3–5.7 dB at 45–85 GHz, respectively [15]. The 45-nmSOI CMOS technology therefore has a lot of potential for90–200-GHz applications, and this paper presents a low-noiseamplifier with record -band NF, and record output power at170–200 GHz using balanced doublers.

II. TECHNOLOGY

The IBM 45-nm SOI CMOS process cross section is shownin Fig. 2. The transistor body is partially depleted and containedinside a 225-nm-thick buried oxide, which isolates the transistorfrom the 13.5 cm silicon bulk. There are 11metal layers abovethe device layer built using copper, except the 2.2- m-thick alu-minum top metal LB. The shielded coplanar waveguide (CPW)transmission line is designed using LB for the signal line and B3for the ground plane, and the LB side grounds are connected toB3 using UA and UB metal layers. A signal linewidth of 8 mwith 9- m spacing to the side grounds results in a 50- trans-mission line at millimeter-wave frequencies.The floating-body -type field-effect transistor (NFET) de-

vices in the IBM model library are used in the amplifier and

0018-9480/$26.00 © 2011 IEEE

CETINONERI et al.: -BAND AMPLIFIERS WITH 6-dB NF AND MILLIWATT-LEVEL 170–200-GHz DOUBLERS 693

Fig. 2. 45-nm SOI CMOSprocess metal stack-up and 50- T-line cross section(not to scale). All metal layers are copper, except the aluminum top metal.

Fig. 3. Measured of a 30 1 m common-source transistor using a TRLcalibration.

doubler designs. The SOI process offers a superior performancecompared to the bulk CMOS technology due to reduced source/drain junction capacitances and improved device isolation. IBMreports a peak of 485 GHz with a relaxed poly-pitch layoutreferenced to a 30- m device at the polysilicon layer [14]. How-ever, the transistors in the available design kit have the min-imum poly-pitch layout, which increases the terminal capaci-tances and lowers the peak to 340 GHz. Furthermore, thetransitions from the transistor up to the top metal result in addedvia resistance and capacitance, which significantly deterioratethe transistor performance. A 30 1 m common-source tran-sistor test cell is shown in Fig. 3 and is measured using a thru-re-flect-line (TRL) calibration up to the reference planes. Thismea-surement includes the transitions and associated parasitics fromthe top metal down to the transistor, and the measured is 200GHz at 0.3-mA m current density.The physical layout of a 30 1 m transistor is shown in

Fig. 4. The transistors have dummy polysilicon gates at the outeredges for better device matching. The default transistor modelfrom the IBM library does not fully account for the metal resis-tances and metal–metal/metal–poly parasitic capacitances sincethe process is developed for digital and mixed-signal applica-tions. In particular, accurate modeling of the gate resistance iscritical for the transistor gain and stability. Therefore, all of themetal and polysilicon layers at the transistor gate and drain areextracted up to M2 using an R/C parasitic extraction tool (Cal-ibre [16]). The source is also extracted up to the surroundingM1ground plane. Since the source connections are not included inthe electromagnetic (EM) model and the parasitic inductances

Fig. 4. Modeling of transition from top metal down to transistor level and sim-plified layout of a 30 1 m transistor.

are not captured in the R/C extraction, extensive care is takenin the layout in order to establish a strong ground definition.Several blocks of stacked vias are used to connect the top levelgrounds (LB and B3 layers) to M1 and a wide M1 plane is usedclose to transistor source so as to minimize any undesired in-ductances that can degrade the device performance.The vertical transition between the LB and M2 metal layers

is 8.7 m, and both gate and drain sections are simulated to-gether to include the parasitic EM coupling between them usinga 2.5-D EM solver (Sonnet [17]). The metal layers from LBdown to B1 are modeled using the thick-metal model in Sonnetwith multiple number of sheets. More than two sheets are usedfor the top metal layers, LB in particular, where the verticalthickness is comparable to the trace width. The metal and via re-sistances are taken into account as specified in the IBM processdesign manual.The transition from the top metal LB to M2 can also be repre-

sented using a lumped-element equivalent circuit [see Fig. 5(a)].In this case, the RLC SPICE model is derived from the Sonnet-parameter simulations. The simulated insertion loss and iso-lation are shown in Fig. 5(b) and agree well with the full-wave-parameters at 80–120 GHz. The simulations also show thatthe coupling between the gate and drain becomes significantabove 100 GHz due to the parasitic capacitance and the mutualinductance between the vertical lines.Fig. 6 shows the effect of the parasitics on the transistor

and NF. The simulated peak of the IBM transistor modelis 300–340 GHz and decreases to 200–220 GHz at a bias cur-rent of 0.3–0.6 mA m when all transitions are modeled [seeFig. 6(a) and (b)]. The minimum NF ( ) also shows a sim-ilar trend when the parasitics are included and the lowestis achieved at 0.1–0.3 mA m current density [see Fig. 6(c)].The added parasitics slightly change away from thecircle on the Smith chart. As seen in Fig. 6(b), there is not muchimprovement in once the current density exceeds 0.3 mA m


Fig. 5. (a) Equivalent circuit of the transition. (b) Simulated insertion loss andisolation: -parameter model (solid) and lumped-element model (dashed).

Fig. 6. (a) Transistor-level modeling of interconnect parasitics. The effect ofparasitics (b) on and (c) on and (30 1 m transistor used).

so the transistor can be biased close to 0.3 mA m as a tradeoffbetween high and low NF. The measured of the 30 1 mcommon-source test cell at 0.2–0.5-mA m current density isconsistent with simulations.

Fig. 7. (a) Measured . (b) Effect of parasitics on the MAG at 90 GHz.

Fig. 8. Schematic of the -band amplifier.

is calculated from the measured unilateral powergain ( ) curve and is 200 5 GHz for a current density of0.2–0.5 mA m [18] [see Fig. 7(a)]. This is lower than theIBM model (referenced to the transistor itself), which predictsan of 460–480 GHz at this current density. The measuredmaximum available gain (MAG) and maximum stable gain(MSG) curves are also plotted showing that the transistor be-comes unconditionally stable above 90 GHz. Fig. 7(b) presentsthe effect of parasitics on the MAG of the same transistor. Themeasured peak MAG is 9 dB with 0.3-mA m current densityat 90 GHz, and agrees well with simulations.

III. -BAND AMPLIFIER

A. Design

The -band amplifier is shown in Fig. 8 and is based on athree-stage common-source design using floating-body transis-tors. The first two stages are designed with 30 1 m transis-tors and the device size is increased to 40 1 m at the thirdstage for high output power. The current density is set to be0.3 mA m for all stages under nominal bias conditions (dis-cussed in Section II).All transmission lines and stubs are implemented using the

9-8-9- m (50 ) grounded CPW lines with a loss of 1.1 dB/mmand a of 15 at 90–100 GHz according to Sonnet simulations.


Shunt 440-fF capacitors, which are close to self-resonance at90 GHz, are placed at the end of the matching stubs and pro-vide a low impedance to ground at 80–100 GHz. Widebandon-chip bypass networks, composed of a 4- polysilicon re-sistor in series with 0.3–2-pF-thick-oxide capacitor banks, areimplemented and connected to the power supply lines to pre-vent any oscillations due to interstage coupling. Also, 10- re-sistors are placed in series with the drain matching stubs to fur-ther improve the stability at an expense of 0.1 V at the drainnode. These resistors are used as a conservative design mea-sure since this was the first implementation of this process at90–200 GHz. The gate biasing is done by using a 3-k resistor,and a simple voltage divider is used at the bias pad to provide ahigh-impedance path to ground and also decrease the sensitivityto the applied voltage (not shown).A shorted stub is used at the source of the first-stage transistor

and acts as a degeneration inductor, which increases the real partof the impedance seen at the gate. This results in two beneficialeffects on the amplifier’s RF performance. First, a widebandinput impedance is achieved when combined with the low-matching sections at the input ( dB at 84–103 GHz).Second, at the input of the first stage moves toward the50- region on the Smith chart and results in a simultaneousgain and NF match after the input matching network.The high-pass interstage matching networks are composed of

transmission lines at the paths and interstage capacitors. Allof the capacitors are implemented using the vertical natural ca-pacitor (vncap) model found in the IBM design kit. The capac-itance is formed between the inter-digitated metal fingers com-posed of C1 to B3 metal layers. The lower metal layers are notused since they result in higher parasitic shunt capacitance per1 fF of series capacitance, which degrades the performance atmillimeter-wave frequencies.The simulated gain of the amplifier is 13.5 dB at 90 GHz with

a 3-dB bandwidth of 85–101 GHz. The input and output returnlosses are wideband due to low- matching networks (

dB at 82– 110 GHz). The simulated NF is 5.3–4.6 dBat 90–100 GHz. The simulated saturated output power ( )and compression point ( ) at 90 GHz are 8.0 and 5.5 dBm,respectively, with a peak power-added efficiency (PAE) of 12%and a 1.4-V supply.

B. Measurements

The chip microphotograph with an expanded view aroundthe transistors is shown in Fig. 9(a). The vertical dimen-sion is determined by the input and output 100- m pitchground–signal–ground (GSG) pads; hence, the transmissionlines and stubs are not meandered. The resulting chip size is0.58 0.55 mm including the pads.The small-signal measurements of the -band amplifier is

performed using an Agilent network analyzer (PNA E8361A)with 75–110-GHz frequency extenders and 1-mm coaxialcables. The calibration is done up to the probe tips using ashort-open-load-thru (SOLT) calibration substrate. The mea-sured -parameters with 1.4-V supply are shown in Fig. 9(b).The -band amplifier has 10.7-dB gain at 95 GHz and a 3-dBbandwidth of 89–107 GHz for three different samples. Bothinput and output return losses are 10 dB at 87–110 GHz

Fig. 9. (a) Microphotograph of the -band CMOS amplifier(0.58 0.55 mm ) and (b) measured -parameters on three different samples(only is shown for the three samples).

and the measured reverse isolation ( ) is 35 dB up to110 GHz (not shown).The NF is measured using an Agilent E4448A spectrum

analyzer with a -band noise source at the device-under-test(DUT) input, and a waveguide amplifier/mixer down-con-version setup at the output port. The measured NF is 6.0dB at 95 GHz, as shown in Fig. 10 with nominal biasing(0.3 mA m) and is 5.9–6.1 dB over a wide range of biascurrent. NF measurements at 100 GHz could not be done sincethe -band waveguide amplifier operated up to 96 GHz.The large-signal measurements are done with WR-10 wave-

guide components and a 1-mm coaxial setup. An AgilentE8257D signal generator was used with a tripler to generate a-band signal and a waveguide variable attenuator was used

at the input for power sweeps. The measured output andat 95 GHz are 5.2 and 7.5 dBm, respectively with a 1.4-V

supply and the measured peak PAE is 9.0% at 95 GHz (Fig. 11).At , the current is 15 mA in the last stage, which resultsin 0.15-V drop across the 10- resistor and a drain voltage of1.25 V.The measured versus frequency is shown in Fig. 12(a)

and is 6 dBm at 90–100 GHz with nominal bias conditions.was also measured by varying the supply voltage at 95 GHz

[see Fig. 12(b)] and it can be increased up to 8 dBmwith a 1.4-Vsupply by optimizing the gate bias points. Two other amplifiersfrom different dies were also measured and they yielded aabove 7.6 dBm with a 1.4-V supply at 95 GHz, showing that


Fig. 10. Measured NF of the amplifier versus frequency and current density.

Fig. 11. Measured output power and PAE versus input power at 95 GHz.

Fig. 12. Measured: (a) and versus frequency and (b) versussupply voltage.

the amplifier can generate high output power even with standardprocess variations.

IV. -TO- -BAND DOUBLER

A. Design

The doubler is an active balanced design, as shown inFig. 13. The single-ended input is converted to a differential

Fig. 13. Schematic of the -to- -band balanced doubler.

Fig. 14. Simulations showing: (a) output power and conversion gain of thedoubler versus finger width (30- m-wide transistors). (b) Effect of reflector onthe output power of the doubler. (c) Output power contours for different gatebias voltages and input power levels.

signal using a passive balun and fed into the balanced transistorpair. The drain nodes are connected together, which creates abroadband short circuit for the fundamental and odd harmonics,but the even harmonics are combined in phase. As the transistorsize is increased, the doubler can yield more power, but ahigher input power is required. The input power to the doubleris 6–7 dBm (see Section III) and a 30 1 m transistor issimulated to achieve maximum conversion gain at this inputpower. Although a smaller finger width can achieve slightlymore conversion gain, the finger width of 1 m is chosen dueto stability concerns [see Fig. 14(a)]. When the finger widthis chosen to be less than 1 m, the simulated andbecome positive over a wide bandwidth when the IBM modelis used (without R/C extraction and Sonnet transition model).The R/C extraction adds extra gate resistance and stabilizes thetransistor, but in this case, a conservative approach was taken


Fig. 15. 3-D view of the doubler input balun and simulated phase/amplitudeimbalance between the differential ports.

and the finger width is limited to 1 m since this was the firstdesign trial in the 45-nm process.Second harmonic reflectors are used at the transistor inputs

to further improve the doubler conversion gain [19], [20]. The220-fF capacitors at the reflector end operate close to self-res-onance, thus providing a very low impedance (0.6 ) for thesecond harmonic at 180 GHz. The position and length of thereflectors are adjusted using EM simulations (Sonnet) to en-sure a simultaneous short circuit for the second harmonic anda high impedance for the fundamental tone at 90 GHz. Simu-lations show that the reflectors result in a 2-dB increase in theoutput power at 170–185 GHz [see Fig. 14(b)].The transistor bias condition is crucial for doubler efficiency

since the conduction angle should be set correctly to maximizethe second harmonic tone at the output [21]. If the drain currentwaveform is assumed to be a rectified cosine pulse, it can berepresented by Fourier series expansion as

(1)

and the coefficients for are

(2)

where is the maximum drain current, is the duration ofthe pulse, and is the period of fundamental frequency. When(2) is solved to maximize , , which correspondsto a conduction angle of 125 . Therefore, the transistor gatesneed to be biased below the threshold voltage ( mV)for optimum doubler operation, and this is shown by the large-signal simulations in Fig. 14(c).The input balun is designed using Sonnet (Fig. 15). The mag-

netic coupling occurs vertically between the primary coil de-signed using the top metal LB and the secondary coil composedof stacked UB and UA metals. The distance to the ground planeis 20 m on each side and the trace width is 5 m. A 23-fF se-ries capacitor at the input, the balun, and a 16-fF capacitor atthe balun output form a multistage matching network and pro-vide a wideband match at the doubler input ( dBat 84–100 GHz). The simulated phase and amplitude imbal-ance between the differential ports is 5 and 1.5 dB at80–100 GHz, respectively.All the transmission lines and interconnects at the input

and output of the doubler are modeled using Sonnet. Due tomaximum metal density requirement for the lower metals,

Fig. 16. (a) CPW transmission line with ground plane meshing. (b) Measured(solid) and simulated (dashed) line loss/mm for a 50- T-line. A 600- m lineand GSG thru pads are used for line-loss measurements.

the B3 ground plane under the transmission lines needs to beextensively meshed. Fig. 16(a) shows a shielded CPW linewith a ground plane mesh designed for 75% maximum metaldensity. This effect can be captured in EM simulations andresults in 0.1-dB increase in line loss per millimeter and adrop of 10% at 180 GHz. A 600- m-long line was measured at160–200 GHz, and the effect of the pads and the CPW transitionwere de-embedded using a GSG thru section. The measuredline loss is 2.2 dB/mm at 180 GHz, which is 0.7 dB higherthan simulations (1.5 dB/mm) [see Fig. 16(b)]. The increase inline loss over simulations has been measured by several groups[10], [22] and is perhaps due to the thin Ta and W adhesionlayers used in the fabrication process [23].

B. Measurements

The chip microphotograph is shown in Fig. 17(a) and the dcbias for the gate and drain nodes is supplied using the top pads.The input and output pads are compatible with both 100- and80- m-pitch GSG probes. The section after the input balun isdesigned symmetrically to maintain balanced operation and thetransistors in the doubler core are placed in close proximity toeach other so as to minimize the distance to the common drainnode. The second harmonic reflectors are meandered to reducethe chip area and the total size is 0.69 0.49 mm including thepads.The -parameter measurements of the doubler requires two

different setups since the input and output are at different fre-quencies. The input return loss is measured with the same setupas the -band amplifier and is 10 dB at 86–108 GHz. Theoutput return loss is measured using a 140–220 GHz ( -band)frequency extension setup and is 10 dB at 153–175 GHz [seeFig. 17(b)].The large-signal characterization is performed using a com-

plete waveguide setup with WR-10 and WR-5 sections at theinput and output, respectively (Fig. 18). All measurements arereferenced to the GSG input and output pads. A mechanicallytuned Gunn-diode oscillator is used at the input and is followedby a variable attenuator for controlling the input power. Theinput power is monitored using a 10-dB coupler and an Agilent


Fig. 17. (a) Microphotograph of the doubler (0.69 0.49 mm ). (b) measured-parameters.

Fig. 18. Measurement setup for doubler output power and gain characteriza-tion. An all-waveguide setup is used for accurate power measurements.

E4417A power meter, and the output port is connected directlyto an Erickson power meter1 using a WR-5 probe and a WR-5to WR-10 taper. The loss of the WR-10 and WR-5 GSG probeswere measured using a thru line on CS-15 calibration substrate.The input WR-10 probe has a measured loss of 1.25–1.40 dB at85–100GHz and the outputWR-5 probe has a loss of 2.3–3.0 dBat 170–200 GHz. TheWR-5 toWR-10 transition has ameasuredloss of 0.2 dB. These losses are calibrated out of the measure-ments to obtain the conversion gain referenced to the GSG padson the 45-nm doubler chip.The measured peak output power is 0.8 dBm at an input

power of 6–7 dBm with 8.0-dB conversion gain at 180 GHzwith a constant gate bias ( ) of 0.24 V for all input power levels[see Fig. 19(a)]. Fig. 19(b) presents the measured output powerat 170–190GHz at two gate bias points. As the input power is in-creased, the gate bias needs to be reduced to maintain optimum

1Erickson Power Meter, PM4, Virginia Diodes Inc., Charlottesville, VA,2009.

Fig. 19. Measured: (a) output power and gain of the doubler versus input powerat 180 GHz, (b) output power versus frequency, and (c) dc current versus inputpower.

Fig. 20. Measured peak output power of the -band doubler versus frequencyfor different doubler designs.

conduction angle that maximizes the second harmonic genera-tion ( 125 ). The output power can be increased to 0 dBm bydecreasing the gate bias to 0 V at 180 GHz with 3.0% drain effi-ciency. The dc current of the doubler is also monitored and is ingood agreement with the simulations up to 7-dBm input power[see Fig. 19(c)]. Note that the 10- resistor in Fig. 13 results in0.2–0.3-V drop for dBm, and the drain voltage is1.1 V at the peak output power.Apart from this doubler, two other doubler versions were de-

signed and measured in order to verify the effect of finger widthand the second harmonic reflector. Fig. 20 shows the measuredpeak output power versus frequency for the three different de-signs. The main doubler design, which has 30 1 m transis-tors and an input reflector, yields the highest output power. Thesecond version has 15 2 m transistors and results in 2.5-dBless output power due to increased gate resistance. The thirdversion also uses 15 2 m transistors, but without the second


Fig. 21. (a) Microphotograph of the amplifier/doubler (1.0 0.56 mm ).(b) Measured output return loss.

Fig. 22. Down-converted 180-GHz signal at the output of the amplifier/doublermeasured using a spectrum analyzer.

harmonic reflector. As predicted, the input reflector improvesthe output power by dB.

V. -BAND DOUBLER WITH INTEGRATED -BAND DRIVER

The amplifier/doubler is a cascade of the same amplifierand doubler designs discussed in the previous sections. Thechip microphotograph is shown in Fig. 21(a) and the totalsize is 1.0 0.56 mm including the pads. A single anda single ground is used for the entire chip. The -parametermeasurement setup is the same as in the case of the doubler. Theinput return loss is wideband and is the same as the amplifier

[see Fig. 9(b)]. The output return loss is well matched at160–185 GHz [see Fig. 21(b)], and shows a better performancethan the doubler [see Fig. 17(b)]. The -band amplifier hasan effect on the doubler output impedance since it is not awideband 50- load.The same measurement setup of Fig. 18 is used for large-

signal amplifier/doubler measurements. The mixer down-con-version setup is also used for verifying the results obtained by

Fig. 23. Measured conversion gain and output power of the amplifier/doublerat 180 and 190 GHz. Standalone doubler output power is also plotted for com-parison.

Fig. 24. (a) Measured peak output power and (b) conversion gain of the am-plifier/doubler versus frequency. Measurements done using a power meter anda mixer down-conversion setup.

the power meter. The down-converted 180-GHz signal is shownin Fig. 22 with an output spectrum up to 12 GHz. The measuredoutput power is 1.4 dBm after de-embedding the losses dueto output probe, mixer, and output cable. The highest undesiredtone is 46 dB lower with respect to the output signal and isdue to the subharmonic mixer setup.Fig. 23 presents the measured conversion gain and output

power of the amplifier/doubler versus input power at 180 and190 GHz ( V). The peak conversion gain is 2–3 dBwhen the input power is at 7 2 dBm and drops as the inputpower is increased. The amplifier/doubler saturates at an inputpower of 2 dBm since the -band amplifier is saturated. As a


TABLE IPERFORMANCE SUMMARY OF -BAND CMOS AMPLIFIERS

TABLE IIPERFORMANCE SUMMARY OF DOUBLERS 130 GHz

comparison, the output power of the standalone doubler is alsoshown in Fig. 23. The standalone doubler saturates at a higherinput power and the difference between the doubler and ampli-fier/doubler curves at low input powers is equal to the amplifiergain. The maximum output power generated by both the dou-bler and amplifier/doubler is nearly identical, indicating that the-band amplifier is providing at least 6–7 dBm and saturating

the doubler sufficiently.The output power is also measured versus frequency from

170 to 200 GHz with the power meter and mixer setups [seeFig. 24(a)]. The measured peak output power is from 0.0 to1.2 dBm at 180–190 GHz when V. Fig. 24(b) shows

the measured conversion gain versus frequency at differentinput power levels. A peak conversion gain of 3.4–5.0 dBwith 8-dBm input power is achieved at 190 GHz due to thegain response of the driver amplifier. As the input power is in-creased, the amplifier saturates and the overall conversion gaindecreases. At an input power of 0 dBm, the conversion gaindrops from 2 to 1 dB at 180–190 GHz. The amplifier/dou-bler results in 0.5–1 mW of output power at 170–195 GHz andshows, to our knowledge, the highest power achieved from aCMOS source above 150 GHz.Table I presents a summary of -band CMOS amplifiers.

It is seen that the 45-nm SOI CMOS technology results inthe lowest NF and with high values. Table II presentsa summary of doublers above 130 GHz. It is seen that the170–200-GHz CMOS doubler is competitive with the bestSiGe results.

VI. CONCLUSION

This paper has demonstrated the first use of 45-nm SOICMOS at - and -band. A significant finding is the reduc-tion of the transistor from 340 to 200 GHz when all theinterconnect parasitics are taken into account. Still, 45-nm

CMOS is an excellent candidate for millimeter-wave low-noiseamplifiers and submillimeter-wave sources. The technologyallows for efficient antennas due to its thick back-end metallayers, and a higher output power can be obtained, both at-band and at 200 GHz, using free-space combining tech-

niques, as demonstrated in [5].

ACKNOWLEDGMENT

The authors thankO. Inac andM. Uzunkol, both with the Uni-versity of California at San Diego, La Jolla, for technical discus-sions and for helping in the measurements. The authors thankProf. S. Weinreb, California Institute of Technology, Pasadena,for his advice on 100-GHz amplifier design.Access to the IBM 45-nm 12SOI process was provided by

theDefense Advanced Research Projects Agency (DARPA)Mi-crosystems Technology Office (MTO) Leading Edge AccessProgram (LEAP).This research was carried out in part at the Jet Propulsion

Laboratory, California Institute of Technology, Pasadena.

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Berke Cetinoneri (S’04) received the B.S. degree inmicroelectronics from Sabanci University, Istanbul,Turkey, in 2006, the M.S. degree in electrical en-gineering from the University of California at SanDiego (UCSD), La Jolla, in 2008, and is currentlyworking toward the Ph.D. degree in electrical engi-neering at UCSD. His doctoral research concerns RFand millimeter-wave integrated circuits in silicontechnologies.

Yusuf A. Atesal (S’04) received the B.S. degree inmicroelectronics from Sabanci University, Istanbul,Turkey, in 2006, and the M.S. and Ph.D. degrees inelectrical engineering from the University of Cali-fornia at San Diego (UCSD), La Jolla, in 2008 and2011.He is currently with the Intel Corporation, Hills-

boro, OR, where he is involved in RF circuit design.His research interests are RF and millimeter-wave in-tegrated circuits in silicon technologies.

Andy Fung (S’97–M’99) received the B.E.E., M.S.E.E., and Ph.D. degreesin electrical engineering from the University of Minnesota at Minneapolis–St.Paul, in 1993, 1995 and 1999, respectively.In 1999, he joined the Jet Propulsion Laboratory (JPL), California Institute of

Technology, Pasadena. His research activities have concerned the developmentof InP HBTs and GaAs Schottky diodes for millimeter- to submillimeter-waveapplications. His current efforts are in the area of high-frequency test methods.

Gabriel M. Rebeiz (S’86–M’88–SM’93–F’97) re-ceived the Ph.D. degree from the California Instituteof Technology, Pasadena.He is currently a Professor of electrical and com-

puter engineering with the University of Californiaat San Diego (UCSD), La Jolla. Prior to this appoint-ment, he was with The University of Michigan atAnn Arbor, from 1988 to 2004. He has contributedto planar millimeter-wave and terahertz antennasand imaging arrays from 1988 to 1996, and his grouphas optimized the dielectric-lens antennas, which is

the most widely used antenna at millimeter-wave and terahertz frequencies.His group also developed 6–18- and 40–50-GHz eight- and 16-element phasedarrays on a single silicon chip, and the first millimeter-wave silicon passiveimager chip at 85–105 GHz. His group also demonstrated high- RF micro-electromechanical systems (RF-MEMS) tunable filters at 1–6 GHzand the new angular-based RF-MEMS capacitive and metal-contact switches.As a consultant, he helped develop the USM/ViaSat 24-GHz single-chipSiGe automotive radar, phased arrays operating at -, -, and -bandfor defense and commercial applications, the RFMD RF-MEMS switch,and the Agilent RF-MEMS switch. He has graduated 42 Ph.D. students. Heis the Director of the UCSD/Defense Advanced Research Projects Agency(DARPA) Center on RF MEMS Reliability and Design Fundamentals. Hecurrently leads a group of 20 Ph.D. students and three Post-Doctoral Fellowsin the area of millimeter-wave RF integrated circuits (RFICs), microwavescircuits, RF-MEMS, planar millimeter-wave antennas, and terahertz systems.He authored RF MEMS: Theory, Design and Technology (Wiley, 2003).Prof. Rebeiz has been an associate editor for the IEEE TRANSACTIONS ON

MICROWAVE THEORY AND TECHNIQUES. He has been a Distinguished Lecturerfor the IEEEMicrowave Theory and Techniques Society (IEEEMTT-S) and theIEEE Antennas and Propagation Society (IEEE AP-S). He is a National Sci-ence Foundation (NSF) Presidential Young Investigator, an URSI Koga GoldMedal Recipient, the 2003 IEEE MTT-S Distinguished Young Engineer, the2000 IEEEMTT-S Microwave Prize, the 2010 IEEEMTT-S Distinguished Ed-ucator Award, the 2011 IEEE AP-S John D. Kraus Award, the 1998 Eta KappaNu Professor of the Year Award, the 1998 Amoco Teaching Award given to thebest undergraduate teacher at The University of Michigan at Ann Arbor, and the2008 Teacher of the Year Award of the Jacobs School of Engineering, UCSD.His students have also been the recipients of a total of 19 Best Paper Awards ofIEEE MTT-S, RFIC, and AP-S conferences.

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$W$ -Band Amplifiers With 6-dB Noise Figure and Milliwatt-Level 170–200-GHz Doublers in 45-nm CMOS