Volume

1-the idea of the program is to increase , decrease the volume.

2-the program does the following: A-PF8:decrease the volume B-Pf9:increase

the volume C-PF10: mute

First, I tried to figure out how to get the gain and to do the calculation.

if (*pFIO_FLAG_C == 0x0100) { // confirm PF8 interrupt handling *pFIO_FLAG_C = 0x0100; //PF8 : Volume Down if (g != 0) { g--; }

} if (*pFIO_FLAG_C== 0x0200) { *pFIO_FLAG_C= 0x0200; // confirm PF9 interrupt handling //PF9: Volume Up if (g < 6) { g++; } }

EZ-Kit Lite contains AD1836 Audio Codec

The AD1836 audio codec provides three channels of stereo audio output and two channels of multi-channel/stereo 96 kHz input. The SPORT0 interface of the processor links with the stereo audio data input

and output pins of the AD1836 codec.

The processor is capable of transferring data to the audio codec in time-division multiplexed (TDM) or two-wire interface (TWI) mode.

The TDM mode can operate at a maximum of 48 kHz sample rate but allows simultaneous use of all input and output channels.

The TWI mode allows the codec to operate at a 96 kHz sample rate but limits the output channels to two.

SW9 Positions 1 through 4: Disconnects the drivers associated with the push buttons from

the PF pins of the processor. Positions 5 and 6: Used to connect the transmit and receive frame syncs and

clocks of SPORT0. This is important when the AD1836 audio/video decoder and the

processor are communicating in I2S mode. SW12 When is set to OFF, SW12 disconnects SPORT0 from the

audio codec. The default is the ON position.

Each SPORT is a full duplex device, capable of simultaneous data transfer in both directions. The SPORTs can be programmed by writing to memory-mapped registers for

bit rate, frame sync, and number of bits per word

void Init_EBIU(void) { *pEBIU_AMBCTL0 = 0x7bb07bb0; *pEBIU_AMBCTL1 = 0x7bb07bb0; *pEBIU_AMGCTL = 0x000f; }

The EBIU asynchronous memory controller has two Asynchronous Memory Bank Control registers:EBIU_AMBCTL0 and

EBIU_AMBCTL1.

They contain bits for counters for: setup, strobe, and hold time; bits to determine memory type and size; and bits to configure use of ARDY.

EBIU_SDGCTL Register Memory Global Control register (EBIU_SDGCTL) includes all programmable parameters associated with the SDRAM access timing and configuration.

void Init_Flash(void) { *pFlashA_PortA_Dir = 0x1;Direction

Configuration *pFlashA_PortB_Dir = 0x3f; }The Direction register controls IO pins direction.

This is a 8-bit read-write register. When a bit is 0, a corresponding pin functions as an input. When the bit is 1, a corresponding pin is an output.

The TIMOD field is used to specify the action that initiates transfers to/from the receive/transmit buffers.

When set to 00, a SPI port transaction is begun when the receive buffer is read. Data from the first read will need to be discarded since the read is needed to initiate the first SPI port transaction.

When set to 01, the transaction is initiated when the transmit buffer is written.

A value of 10 selects DMA Receive Mode and the first transaction is initiated by enabling the SPI for DMA Receive mode. Subsequent individual transactions are initiated by a DMA read of the SPI_RDBR.

A value of 11 selects DMA Transmit Mode and the transaction is initiated by a DMA write of the SPI_TDBR.

The SPI Control register (SPI_CTL) is used to configure and enable the SPI system.

This register is used to enable the SPI interface, select the device as a master or slave, and determine the data transfer format and word size.

SPI is a four-wire interface consisting of two data pins (IN & OUT), a device select pin (SPISS), and a clock (CLK) pin.

SPI is a full-duplex synchronous serial interface, supporting master modes, slave modes, and multimaster environments.

The SPI compatible peripheral implementation also supports programmable baud rate and clock phase/polarities. The SPI has two interrupt output signals: a data interrupt and an error interrupt

The SPI is an industry-standard synchronous serial link that supports communication with multiple SPI compatible devices. The SPI peripheral is a synchronous, four-wire interface consisting of

two data pins: Master Out Slave In (MOSI) and Master In Slave Out (MISO) one device select pin Serial Peripheral Interface Slave Select (SPISS) Input Signal, and a gated clock pin Serial Peripheral Interface Clock (SCK) Signal. With the two data pins, it allows for full-duplex operation to other SPI

compatible devices.

The SPI also includes programmable baud rates, clock phase, and clock polarity.

Two registers are used for buffering receive and transmit data: SPI_RDBR and SPI_TDBR

The SCK signal is the SPI clock signal. This control signal is driven by the master and controls the rate at which data is transferred. The master may transmit data at a variety of baud rates.

The SCK signal cycles once for each bit transmitted.

Each SPORT has its own set of control registers and data buffers.

The SPORTs use frame sync pulses to indicate the beginning of each word or packet, and the bit clock marks the beginning of each data bit.

The Blackfin C/C++ compiler provides support for interrupts and other events used by the Blackfin processor architecture (see Table 1-25 of VisualDSP++ 4.5 C/C++ Compiler and Library Manual for Blackfin Processors).

The Blackfin system has several different classes of events, not all of which are supported by the ccblkfn compiler. Handlers for these events are called Interrupt Service Routines (ISRs).

The compiler provides facilities for defining an ISR function, registering it as an event handler, and for obtaining the saved processor context.

To define a function as an ISR, the sys/exception.h header must be included and the function must be declared and defined using macros defined within this header file.

Where is this file included in the LED Lab #1 example?

There is a macro for each of the three kinds of events the compiler supports:

EX_INTERRUPT_HANDLER EX_EXCEPTION_HANDLER EX_NMI_HANDLER