Voltage Stabilization of VSI SMES Capacitors and Voltage

1

Voltage Stabilization of VSI SMES Capacitors and Voltage Sag Compensation by SMES Using Novel and Optimized Switching Strategies

M.R. Alizadeh Pahlavani1, H. A. Mohammadpour1, and A. Shoulaie1,

1 Department of Electrical Engineering, Iran University of Science and Technology (IUST), Tehran, Iran

Keywords : Voltage stabilization, voltage sag compensation, optimized switching strategy, three-level Neutral point clamped voltage source inverter, two-quadrant three-level chopper

Abstract : This paper presents a novel and optimized

switching strategy and control approach for a three-level two-quadrant chopper in a three-level Neutral point clamped (NPC) voltage source inverter (VSI) superconducting magnetic energy storage (SMES). Using the proposed switching strategy, the voltage of the inverter capacitors in SMES can be independently controlled. Also, the minimum power and switching losses as well as the pro-per convection can be achieved using this switching strategy. The simulation results indicate that the proposed switching strategy along with a proportional-integral (PI) control approach can be easily implemented in the power networks, and it can balance and stabilize the capacitors’ voltage level of the multi level inverters while satisfying the IEEE standard specifications. To investigate the effectiveness and reliability of the proposed approach in stabilizing the capacitors’ voltage, the performance of SMES using the presented approach is compared with that of SMES when the capacitors of the three-level

inverter are replaced with equal and ideal voltage sources. This comparison is carried out from the power quality point of view and is shown that the proposed switching strategy with a PI controller is highly reliable. Con-sidering the fact that the Space Vector Pulse Width Modulation (SVPWM) is highly effective in decreasing the low order harm-onics, in this article, this type of modulation combined with the most optimized switching strategy is utilized.

In addition, in this study, a new algorithm is presented for SMES to compensate the voltage sag in the power networks. Simulation results show that the VSI SMES combined with the proposed algorithm is able to compensate the voltage sag and phase voltage in less than one cycle. 1. Introduction

Superconductivity Magnetic Energy Storage (SMES) systems are classified into two groups namely, the voltage source inverter (VSI) and the current source inverter (CSI) SMES [1]-[3]. The VSI SMES studied

09-E-PQA-0110

Voltage Stabilization of VSI SMES Capacitors and Voltage Sag Compensation by SMES Using Novel and …

24th International Power System Conference

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in this paper is shown in Fig. 1. As depicted in this figure, this type is composed of a mag-netic energy storage coil, AC/DC filters, a multi-level chopper, a capacitor bank, and a multi-level converter (i.e. an inverter or a rectifier).

Fig.1. The VSI SMES

The converter is an interface between the

power network and the capacitor bank and controls the electrical energy exchange between them. Also, the chopper is an interface between the magnetic energy storage coil and the capacitor bank and controls electrical energy exchange between them. To store the electrical energy in the capacitor bank and the magnetic energy storage coil in the range of mega joules, it is necessary to employ the high power rating converters. To overcome the limitations due to the current and voltage range of the semiconductors, multi-level converters are used. The advantag-es of using such converters include reducing voltage on switches, harmonic order correction, eliminating or decreasing lateral equipment, decreasing switching frequency, decreasing total harmonic distortion (THD), decreasing switching losses, and decreasing the output current ripple. Using multi-level converters, on the other hand, have some disadvantages.

Among them are the complexity of the control systems, increasing the number of power electronic devices, and increasing the asymmetry of the capacitor voltages during charge and discharge [4]-[8]. However, the current increasing trend in the speed of elect-ronic processors and the steady decrease in the cost of power electronic device on one hand, and the ability to implement advanced modulation methods such as the SVPWM on the other hand, encourage engineers to neglect

the disadvantages of multi-level converters [9]-[12].

With respect to the fact that an appropriate choice of switching strategy for SVPWM effectively reduces the low order harmonics, in this work an optimized switching strategy for SVPWM has been employed to mitigate some low order harmonics in the three-level neutral point clamped (NPC) voltage source inverter.

Power quality is involved with a wide range of electromagnetic phenomena such as transient state, short-term and long-term variations, voltage imbalance and variations, wave distortion, and frequency oscillations in power systems. In fact, the magnitude of variations in voltage, current, and frequency in power systems determines the power quality. In recent years, the voltage quality has been introduced as the most important index of the power quality. Among voltage quality indicators, voltage sag has been shown to be especially important.

Voltage sag is defined as the short-term duration, temporary voltage drop with duration between 0.5 and 30 cycles, while ha-ving a typical magnitude of 0.1 to 0.9 per unit range [13]-[14].One way to compensate voltage sag is to use SMES.

Depending on its application, a SMES device is controlled in two ways [15]. In the first approach, the transmitted active and reactive power to the network is controlled using a NPC voltage source inverter, and the level of the capacitor voltage is stabilized using a chopper. In the second approach, the NPC voltage source inverter controls the transmitted reactive power to the network and also stabilizes the level of the capacitors volt-age, and the chopper controls the transmitted active power to the network. It should be noted that if the voltage of the capacitors is stabilized during all switching operations, smaller capacitors can be used in the SMES system resulting in the lower cost of config-uration. Also, any imbalance due to the asym-metry in the SMES circuit and its operation can be easily corrected by keeping the voltage of the capacitor at a constant level [15].



3

This paper is focused on two objectives: 1- To stabilize the voltage of the capacitors of the three-level NPC voltage source inverter. To achieve this goal, a novel switching strategy for the two-quadrant three-level chopper is presented. In this switching strategy, several objective functions such as minimizing switching and power losses are satisfied. PI controllers are utilized to determine the real-time duty cycles of the three- level chopper in different operation modes [16]. On the other hand, to meet the power quality requirements, the most approp-riate switching strategy for the SVPWM in the three-level NPC inverter is applied [9],[10]. 2- To implement a new algorithm to compensate the voltage sag using SMES. It is shown that using this algorithm, the SMES can quickly generate and control the transmitted active and reactive powers to the power networks with high efficiency. Hence, using the proposed algorithm, the SMES can be used as a series or parallel Flexible AC Transmission Systems (FACTs) device in the power networks. 2. Switching Strategies of The Three-level NPC Inverter

Fig. 2 shows a case study in which a three-level NPC inverter supplies the three phase power network. A filter is used between the inverter and the power network to eliminate the high order harmonics. It is noted that part of the low order harmonics are mitigated by applying SVPWM. Different switching states of the three-level NPC inverter are shown in Table I. In this table, 1 and 0 indicate the on/off states of the switches, respectively. As seen in this table, in order to prevent capacitor leg short-circuit, all switches in a leg are never turned on simultaneously.

Table I. Different switching states of the three-level inverter.

1iS ′ 2iS ′ 2iS 1iS iC 0 0 1 1 1 0 1 1 0 0 1 1 0 0 -1

From Fig. 2 and Table I:

cbaiVCV dciio ,,2/ == (1) Assuming that the inverter output voltage is

balanced and symmetrical: noioin VVV −= (2)

0=++ cnbnan VVV (3) Replacing (2) in (3) results:

3/)( coboaono VVVV ++= (4) Also substituting (1) and (4) in (2) gives:

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

−−−−−−

=⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

co

bo

ao

cn

bn

an

VVV

VVV

3/23/13/13/13/23/13/13/13/2 (5)

If )0( =wt , Park’s transformation gives:

3/22 ,)(32 πj

cnbnanqdref eaVaaVVjVVV =++=+=r (6)

)(6

2cba

dcref CaaCCVV ++=r (7)

Using (7) and the values of ),,( cba CCC which are given in Table I, 27 space vectors are obtained. The corresponding space vector plan is shown in Fig. 3. This space vector plan shows that the vectors ,, 714 VV and 0V will short circuit the load. In fact, these vectors are zero voltage vectors in the space vector plan; the other space vectors are active vectors. The active vectors 21V to 26V with the magnitude of

6/2 dcV shape a large hexagon; the active vectors 15V to 20V with a magnitude of 2/dcV form a medium hexagon, while the active vectors with the magnitude of 6/dcV draw a small hexagon in the space vector plan. As seen in Fig. 3, each hexagon is divided into six sectors. Moreover, each sector in the large hexagon is divided into four triangles. So there are 24 triangles in the large hexagon. The vector refV

r at any instant is located inside one of the 24 triangles. The average value of the output voltage )( refV

r is computed from the linear composition of the vectors of the trian-gle in which refV

r is located as shown in Fig. 4.



4

dtVdtVdtVdtVba

a

S

ba

aS TT

T

T

TTcb

T

a

T

ref ∫ ∫∫∫+

+

++=rrrr

00

(8)

ccbbaarefS VTVTVTVTrrrr

++=

(9)

Fig. 2. A. The three-level three-phase Inverter, B. The power

Network (Load) and the LC Filter.

)110(2V

)000(0Vaxisd)111(7V

)111(14 −−−V

)010(3V

)101(6V)101(12 −−V

)011(4V

)101(20 −V

)110(17 −V )110(15 −V

)111(21 −−V)111(24 −V

)101(18 −V

)111(25 −−V )111(26 −V)110(19 −V

)111(23 −−V )101(16 −V)111(22 −V

)100(1V)110(8 −−V

)100(9 −V)110(10 −−V

)100(11 −V

)001(5V )100(13 −V

axisq

aTbT

cT

aT bT

cT

aT bT

cT

aT

bTcTrefV

αI

IV

IIIII

Fig.3. The space vector plan.

0Vaxisd

7V14V

axisq aT

bTcT refV

r

aαbαα

cα

aVr

bVr

cVr

Fig. 4. Operation time calculation of each triangle vector.

The projection of the vectors in (9) on the d-q axis and composing the obtained vectors gives:

cccbbbaaa

refs

VTVTVT

VT

ααα

α

coscoscos

cosrrr

r

++

= (10)

cccbbbaaa

refs

VTVTVT

VT

ααα

α

sinsinsin

sinrrr

r

++

= (11)

απϕω ==+=++

=

fttTTTT

VVm

inv

Scba

dcrefa

2,

),6

2/(r

(12)

where am is the modulation index, ST is the switching period (the inverse of the switching frequency )( Sf ), invϕ is the inverter phase, and f is the frequency of the inverter output voltage. Assuming that the switching period and the phase and the magnitude of the vectors

,,, baref VVVrrr and cV

r are known, solving equations (10), (11), and (12) gives ,, ba TT and cT . These times, shown in each triangle in Fig. 3, determine the operation time of the triangle vectors. Note that by knowing the value of

invt ϕω + at any time, the number of the space sector in which refV

r is located can be determined. The above equations can be exte-nded to all sectors of the large hexagon by ch-anging α to )3/)1(( πα −− n where 6,...,1=n is the sector number. In Table II, the operation times of the vectors of 4 triangles created in the thn sector are given.

Table II. The operation times of the vectors of 4 triangles of the

nth sector. cbaiTi ,,= triangles’

number

cbsa TTTT −−=

I dcSrefb VnSinTVT /)3/(22 πα +−=

dcSrefc VnSinTVT /)3/)1((22 πα −−=

cbsa TTTT −−= II dcSrefb VnSinTVT /)3/(22 πα +−=

dcSrefc VSinTVT /22 α=

cbsa TTTT −−= III dcSrefsb VnCosTVTT /)6/)21((22 πα −++−=

dcSrefsc VnSinTVTT /)3/(22 πα +−−=

cbsa TTTT −−= IV dcSrefb VnSinTVT /)3/(22 πα +−=

dcSrefsc VnSinTVTT /)3/)1((22 πα −−+−=

(A)

(B)



5

Depending on the number of space vectors in each sector and the operation time of each space vector to generate ,refV

r many different switching strategies can be presented. The authors of the present work showed that in order to minimize THD in the inverter output voltage, when possible, the zero vectors should be distributed at the beginning, at the middle, and at the end of the switching periods in each sector [9]-[10].

Also to minimize the switching losses, this distribution should be performed in such a way that the minimum number of displ-acements in the switching states in each switching period of each sector is occurred. The switching strategy of the space vector pulse width modulation is shown in Table III. This strategy is based on the 24 triangles generated in the large hexagon as indicated before. This switching strategy is implement-ed in a way that both the minimum THD and the minimum switching losses are realized.

Table III. The implemented switching strategy in the three-level NPC

inverter with Space Vector Pulse Width Modulation. aT5.0

52cC

32cC

bT cT

52bC52aC

32bC32aC12cC12bC12aC

aT cT bT aT5.0

aT5.0

64cC

44cC

cT bT

64bC64aC


aT bT cT aT5.0

aT5.0

54cC

34cC

bT cT

54bC54aC


aT cT bT aT5.0

aT5.0

53cC

33cC

cT5.0 bT

53bC53aC


aT5.0 cT aT5.0 bT cT5.0 aT5.0

cT5.0

63cC

43cC

aT5.0 bT

63bC63aC


cT5.0 aT cT5.0 bT aT5.0 cT5.0

Continuation of Table III.



6

Continuation of Table III. aT5.0

62cC

42cC

cT bT

62bC62aC


aT bT cT aT5.0

Note that aijC in this table indicates the

switching states in the inverter leg-a at the thi sector in the thj triangle. It should be noted

that the operation time of the vectors of each triangle in this switching strategy is determined from the times indicated in each triangle shown in Fig. 3. Because of the following reasons, the switching strategy shown in Table III is the most appropriate strategy among the other switching strategies of the SVPWM [9]: • Minimizing the THD in the line voltage; • Having the minimum THD in the phase

voltage in the 60% of the modulation index interval;

• Creating the minimum number of the harmonic orders in the line and the phase voltage resulting in the minimum distortion power losses;

• Having the minimum percent of harmonic orders to the fundamental order ratio;

• Having the minimum switching losses to the switching frequency ratio;

• Low dependency of the THD on the high harmonic orders in the high modulation index.

• Reducing the size of the inductance of the filter )( fL . This is because the order of the low order harmonic (LOH) is increased;

• Creating the minimum power and switching losses in the 50% and %100 modulation index interval, respectively;

• Producing the maximum number of levels in the line or the phase voltage;

• Quick damping of the distortion factor (DF) of the line and the phase voltage versus the switching frequency. Because

of the rapid damping, DF is approximately independent of the switching frequency;

• Reducing the transient time to one cycle period to obtain a sinusoidal voltage and load current;

3. A novel switching strategy for the two-quadrant three-level chopper

In previously discussed the SMES control methods stabilizing capacitors voltage depends upon the power networks. In the first control approach, the transmitted active and reactive power to the network is controlled by a NPC voltage source inverter, while the level of the capacitor voltage is stabilized using a chopper. In this article, to investigate the interaction between the SMES and the power networks the first control approach is used. This control approach is easily implemented if an optimized and appropriate switching strategy for the chopper is defined. Fig. 5 shows a two-quadrant three-level chopper st-udied in this work.

Fig. 5. A. The two-quadrant three-level chopper, B. The load (DC

filter and SMES coil).

(A)

(B)



7

In Table IV, all possible switching states in the three-level chopper as well as the SMES coil current path are given. One of the main requirements in the switching strategy of the multilevel choppers is to minimize both the switching losses and the frequency in order to eliminate the need for the high frequency electronic switches. Moreover, the minimization of the power loss is obtained by minimizing the number of on-switches with the minimum on-time in each switching period. So, the switching states in which each chopper switching period creates the minimum number of displacements in the switching states is selected as the best states for the SMES coil charge and the discharge modes. The optimum switching states are highlighted in Table IV. The other switching states not satisfying the aforementioned conditions are not used [16].

Another requirement in the switching strategy of the multi-level choppers is the independent action of the capacitors’ voltage controllers. The switching strategy satisfying the two cited requirements is given in Table V. The charge and discharge modes (CM and DM) in Table V are obtained from the proper states in Table IV assuming that the chopper switching period is chT2 .

Note that oT and uT are, respectively, the operation times that the voltage of the upper and the lower capacitors are connected to the positive and the negative polarities of the load during the charge and the discharge modes. Also, zT is the chopper operation time when the load is short circuit; this occurs at both the charge and discharge modes. Hence, the duty cycles of the chopper can be defined as follows:

chzuochuuchoo TTTTTTdTTd 2,2/,2/ =++== (13) From (13) it is realized that ,, uo dd and zd

vary in the range [0, 1]. Also from Table V, it is seen that in the charge and the discharge modes, uo dd + is always less than one. This means that the required time for compensating the capacitors voltage to the reference voltage is less than a single switching period of the chopper.

Table IV. Switching states in a two-quadrant three-level chopper Mode Current path ),,,( 2121 dddd SSSS ′′ loadV FCM

2121 ,,, dddd SSSS ′′ )1111(21 CC VV +

CM

221 ,,, dddd SDSS ′′ )0111(2CV

21 ,,, dddd SDDS ′′ )0110(0

211 ,,, dddd SSDS ′′ )1110(1CV

FDM ee DD ′, )0000(

21 CC VV −−

DM

edd DDS ′′′ ,,1 )0010(

2CV−

21 ,,, dddd SDDS ′′ )0110(0

2,, dde SDD )0100(1CV−

Unu

sabl

e

21,, dde SSD )1100(0

21,, dde SSD )1101(0

edd DSS ′′′ ,, 21 )1011(0

edd DSS ′′′ ,, 21 )0011(0

2,, dde SDD )0101(1CV−

ee DD ′, )1010(21 CC VV −−

ee DD ′, )1001(21 CC VV −−

ee DD ′, )1000(21 CC VV −−

ee DD ′, )0001(21 CC VV −−

Table V. The implemented switching strategy in the two-quadrant

three-level chopper.

In other words if uo dd + is larger than one, the required time for the compensation of the capacitors voltage to the reference voltage will be more than a single switching period of the chopper. In this case, the compensation of the capacitors voltage to the reference voltage should be performed simultaneously. The fast charge and discharge (FCM and FDM) modes have been considered for this case. Note that in changing from the fast charge mode to the



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charge mode or from the fast discharge mode to the discharge mode and vice versa, the mi-nimum number of displacements in switches of each chopper switching period is occurred resulting in the minimum switching losses. This is one of the advantages of the proposed switching strategy. 4. Chopper duty cycle controller design

In this section, a block diagram for generating the duty cycle of CM and FCM is presented (Fig. 6).

Fig. 6. The chopper duty cycle controller

To enhance the system dynamic response in balancing the voltage of the capacitors, it is necessary to ensure that the voltages of the capacitors are equal before connecting the inverter to the power network. To achieve this, the voltages of the upper and the lower capacitors are compared with the reference voltage, which is assumed to be dcV5.0 as seen in Fig. 6. Subsequently, the difference in the voltage is passed through the limiters with [0 0.5] interval. These limiters work in such a way that each capacitor is charged for just 50% of the switching period. In fact, the outputs of these limiters can only produce the charge mode (CM). After connecting the inverter to the power network, the PI controllers come into operation and the vol-

tage errors are fed to these controllers. Using the signal holders, the outputs of the PI controllers are sampled every chT2 period. The signal holders with chT2 sampling time are us-ed to avoid abrupt variations in the duty cycles. Note that if the duty cycles vary abruptly, the turn on/off times of the switches should be zero that is practically impossible. The outputs of the signal holders are passed through the limiters with [0 1] interval. These limiters can produce both the charge and the fast charge modes (CM, FCM).

With the availability of ,, uo dd chT and by using Embedded MATLAB Functions shown in Fig. 6, the different modes of the chopper (CM, FCM, DM, and FDM) can be determined. Finally using these modes, the corresponding switching strategies are applied to the chopper switches based on Table V. 5. simulation results of the switching strategy of the three-level chopper

In this section, the strategies presented in sections II to IV are simulated using MATLAB® software. The power network to which the SMES is connected is shown in Fig. 7. The power network was modeled using M-file in MATLAB®. The power network and the SMES parameters are given in appen-dix I.

Fig. 7. The power network.

In Fig. 8, the performance of the SMES

using the developed approaches is compared with that of the SMES when the capacitors of the three-level NPC inverter are replaced with equal and ideal voltage sources (SMES with

(A)

(B)



9

ideal VSI). These comparisons are from the view point of the THD and the DF of the inv-erter output line voltage. As seen in this figure, the performance of the SMES using the chopper duty cycle controller is the same as that of the SMES having an ideal VSI.

Fig. 8. THD and DF variation of the inverter output line voltage.

Fig. 9 shows the voltage variation of the capacitors versus the modulation index. This figure indicates that the proposed schemes are capable of stabilizing the voltage of the capa-citors to the reference voltage (with less than %0.5 error in the worst case scenario). The smallest voltage variation (with %0.0625 error) is obtained when the modulation index is 0.65 as shown in Fig. 9. This is because PI controllers have been regulated for this modulation index. In other words, the variati-on of the capacitors voltage depends on both the modulation index and the parameters of the PI controllers. As a result to obtain the best results, it is recommended that the parameters of the PI controllers are deregulated for each modulation index.

Fig. 9. The capacitors voltage variation versus index modulation

Fig. 10 shows the voltage and the current of

the SMES coil and the current of the load. From this figure, it is noticed that the current of the SMES coil is decreasing, or in other words, the stored energy in the coil is discharging. The discharged energy is transmitted to the chopper in the active power form, because in this transmission, the current of the load and the voltage of the SMES coil remain constant.

In Fig. 11 the variation of the chopper duty cycle and the voltage of the DC filter capacitor are depicted. Note that in this figure the inverter is connected to the power network at

[sec]08.0=t . It is concluded from this figure that before

[sec]08.0=t , the CM mode and after this time both the CM and the FCM modes have been selected by the Embedded MATLAB function as expected. Also, as observed in Fig. 11 (A), the voltage of the fdcC is important in stabilizing the voltage of the SMES coil. Fig. 11(B) shows that in steady state condition, only the CM mode occurs for this power network.

Fig. 10. The current and the voltage of the SMES coil and the

current of the load.



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Fig. 11. A. The voltage of the capacitor

fdcC and the chopper duty

cycle percent B. Steady state duty cycle percent.

Fig. 12 shows the voltage variation of the capacitors. The initial voltages of the capacitors 1C and 2C were ][9800 V and ][9500 V , respectively. As noticed in Fig. 12, the proposed switching strategy properly stabilizes the voltage of the capacitors before and after connecting the inverter to the power net-work. In Fig. 12, the voltage variations of the capacitors in the steady state condition, as can be verified in Fig. 9, is less than

][25.6 V ).0625.0(% This value, in comparison with the values defined in the IEEE standard specifications and obtained in [15] (i.e. %1), has been reduced about fifteen times.

Fig. 12. Variation of the voltage of the capacitors

1C and2C .

The parameters of the PI controllers, as

seen in appendix I, should be independently tuned for the upper and the lower capacitors. This is because of using the SVPWM, the upper and the lower capacitors are not discharged at the same rate. Consequently, the number of the PI controllers should be equal to that of the level of the inverters, and the parameters of each PI controller should be independently tuned. In fact, using this app-roach, the voltage of the inverter capacitors can be stabilized even when the power network is asymmetry and unbalanced. To verify the simulation results obtained by the proposed switching strategy given in Tables III and IV, a part of the implemented switching strategy in the inverter and in the three-level chopper are shown in Figs. 13 and 14, respectively.

These figures show that the carrier waves of the chopper and the inverter are triangular, and the period of these carrier waves for the inverter and the chopper are [sec]001.02 =ST and

[sec]001.02 =chT and their magnitudes are ST and chT , respectively.

Fig. 13. Part of the proposed switching strategy for the inverter

using the SVPWM.

(A)

(B)



11

Fig. 14. Part of the proposed switching strategy for the three-level

chopper. In Fig. 15, the steady state line voltage and

the current of the loads no.2 and no. 3 are shown. In Fig. 16 the steady state line voltage and the current of the inverter before filtering are depicted. Comparisons of Figs. 15 and 16 shows that the AC passive filter has successfully filtered out the current and the voltage harmonics produced by the inverter at the load terminals.

0.35 0.355 0.36 0.365 0.37 0.375 0.38 0.385 0.39 0.395 0.4-2

-1

0

1

2

Vlin

e [KV

]

Modulation index = 0.65 & Number of Load = 2

0.35 0.355 0.36 0.365 0.37 0.375 0.38 0.385 0.39 0.395 0.4-2

-1

0

1

2

I line [K

A]

Time [sec]

0.35 0.355 0.36 0.365 0.37 0.375 0.38 0.385 0.39 0.395 0.4

-2

-1

0

1

2

Vlin

e [KV

]

Modulation index = 0.65 & Number of Load = 3

0.35 0.355 0.36 0.365 0.37 0.375 0.38 0.385 0.39 0.395 0.4-3

-2

-1

0

1

2

3

I line [K

A]

Time [sec] Fig. 15. Steady state line voltage and the current of the loads: a)

No.2, b) No.3.

0.35 0.355 0.36 0.365 0.37 0.375 0.38 0.385 0.39 0.395 0.4-30

-20

-10

0

10

20

30

Vlin

e [KV

]

Modulation index = 0.65 & voltage and current of inverter

0.35 0.355 0.36 0.365 0.37 0.375 0.38 0.385 0.39 0.395 0.4-4

-2

0

2

4

I line [K

A]

Time [sec] Fig. 16. The steady state output voltage and the current of the

inverter. 6. Voltage sag compensation algorithm

In this section, a new algorithm is presented to compensate the sag voltage in a R-L load using SMES. Fig. 17 shows the configuration of the studied power network, the R-L loads, and the SMES.

To compensate the voltage sag using SMES, it is necessary that the proper values of am and invϕ are calculated and applied to the inverter. If the phasor voltage of the R-L load no.2, resulting only from the generator, before and after the voltage sag are respectively shown by pv

r and nvr , and the phasor voltage

of this R-L load, resulting only from connecting the SMES to the power network, after the voltage sag is shown by ,smesv

r then the phasor diagram of the R-L load voltage can be shown as given in Fig. 18. Using Fig. 18, the following equations can be obtained:

)coscossinsin

(tan 1

nnpp

nnppsmes vv

vvg

ϕϕϕϕ

ϕ−

−= − (14)

smesnnppsmes vvv ϕϕϕ cos/)coscos( −= (15)By calculating smesϕ and smesv from (14),

(15), and using the power flow that considers only the effect of the SMES system, the values of the am and invϕ for applying to the three-level NPC inverter are calculated.

Fig. 17. Configuration of the R-L load, the SMES, and the power

network.



12

Fig. 18. The phasor diagram of the voltage sag compensation in

the R-L load. 7. Simulation Results and Discussion

In this section, the performance of the three-level VSI in the voltage sag compensation using the proposed switching strategy presented in section II and the algorithm presented in section VI is investigated. The power network shown in Fig. 17 was simulated in MATLAB software. The parameters used in this figure are the same as those defined in Fig. 7. The parame-ters used for the generators are given in appendix I. The sag compensation of the voltage of the load no.2 using the SMES is shown in Fig. 19. In this study, the voltage of the generator drops to .].[5.0 up . Note that in Fig. 19(A), at 5.0=t [sec] the voltage immediately decreases from its full value to the sag value in essentially zero time while in Fig. 19(B) the same observation noticed during one cycle in ramp rate. In Figs. 19(A) and (B), the Compensator starts sampling the magnitude and the phase of the voltage of the load no.2 after one cycle and three cycles of voltage sag, respectively. As seen in this figure, the SMES using the proposed algorithm successfully compensates the load voltage in less than one cycle. Performance comparison shows that the dynamic response time of the SMES using the proposed algorithm in compensating the voltage sag is five times faster than that presented in [17], and is equal to the responses obtained by the current source inverter (CSI) SMES presented in [18]-[20].

To study the active and the reactive powers at steady state, in all other figures that are presented in this section, the Compensator is regulated to start measuring and compensatin-g after three cycles of the voltage sag occurrence.

Fig. 19. The voltage sag compensation of the load No. 2.

Fig. 20 shows the compensation of the

phase and the magnitude of the voltage of the load no. 2. As seen in this figure, the SMES using the presented algorithm has successfully compensated both the magnitude and the phase of the load voltage and returned them to their initial values. In Fig. 20, the voltage variation of the load in steady state condition is about ).0365.0(%][1559.1 V This value is 136 times less than the IEEE-519 standard )5(% .

Fig. 20. Compensation of the phase and magnitude of the voltage

of the load No. 2.

(B)

(A)



13

Fig. 21 depicts the active and the reactive power variation of the load no. 2, the generator, and the SMES. The active and the reactive power of SMES is measured from the output of the AC filter. As seen in Fig. 21, after the occurrence of voltage sag, the active and reactive power of the generator is decrea-sed. However, the developed algorithm has quickly compensated and returned the active and the reactive power of the load to their initial values.

Fig. 21. The active and the reactive power variation of the load

No. 2, generator, and the SMES.

In fact the required active and reactive power for compensation is provided by the SMES as seen in Fig. 21. From the above discussion, it is concluded that the SMES before the fault (the voltage sag) stores energy in the reactive power form, and after the fault by producing both the reactive and the active powers, compensates the reactive and the active power of the load. These examples clearly show that the SMES using the proposed algorithm can be used as a FACTS device to compensate both the active and the reactive powers in the power networks. 8. Conclusion

In this study an appropriate switching strategy for the NPC VSI with several advantages for the SMES with the ability to improve the performance of this device was presented. Some advantages of using the desire switching strategy for the NPC VSI presented in this paper are given below: • Optimizing the power quality by

implementing a proper switching strategy in SVPWM for VSI SMES;

• Better stabilizing of the voltage of the capacitors’ of the VSI SMES than that of the IEEE standard;

• Implementing the fast charge and fast discharge modes instead of the charge and discharge modes for increasing the dynamic response time in stabilizing the capacitors voltage of the VSI SMES;

• Independent control of the capacitors voltage in the VSI SMES for compensating asymmetry and unbalanc-ed loads;

• Minimizing the switching and power losses resulting in easy and reliable convection from multi-level converter’s switches;

• Using the proposed switching strategies, the power quality becomes equal with the case in which the capacitors of the inverter are replaced with the ideal and equivalent voltage source (SMES with ideal VSI);

• Effective and highly reliable performance of the presented strategy when used with a PI control approach;



14

• Compensating capacitors’ voltage of the VSI SMES before connecting the SMES to the power network (stand by mode).

Furthermore, an algorithm was presented for the VSI SMES to compensate the voltage sag. Some advantages of the proposed algorithm are as follows: • Compensating the voltage sag and the

voltage phase of the load in less than one cycle;

• Compensating the active and the reactive power in less than four cycles;

• Load voltage stabilizing in good agreement with the IEEE-519 standard.

APPENDIX I The parameters of the PI controllers:

03.0,04.0,1.0,1.0 ==== UUOO KIKPKIKP

Specifications of the transmission line:

][3],[30],[5.1

],[15],[5.1],[15

332

211

Ω=Ω=Ω=

Ω=Ω=Ω=

LLL

LLL

RXR

XRX

Specifications of the synchronous generator:

][50],[20.],.[015.0.],.[15.0

MVASKVVupRupX

GG

GG

====

Specifications of the transformers:

][2.13/132],[50.],.[01.0

.],.[1.0],[20/132],[30

.],.[01.0.],.[1.0],[132/20

],[30.],.[01.0.],.[1.0

333

312

221

111

KVVMVASupR

upXKVVMVAS

upRupXKVV

MVASupRupX

TTT

TTT

TTT

TTT

===

===

===

===

Specifications of the R-L loads:

][2.13],[50],[5.0

],[2.0],[18],[30

],[5.0],[2.0],[18

],[30],[5],[2

133

322

221

111

KVVMVASR

mHLKVVMVAS

RmHLKVV

MVASRmHL

RLRLRL

RLRLRL

RLRLRL

RLRLRL

==Ω=

===

Ω===

=Ω==

Specifications of the NPC VSI and the SMES:

][400],[2],[20],[05.0],[1.1],[75.0,:

FCKHzfKVVWPVVmRMSEMIKRONSKIGBT

fchdcS

FOIGBT

μ=====Ω=

][200],[2],[2],[700][200],[2],[10],[50

,65.0],[20],[1],[800

1

2

mFCKHzfrFCmFCRHLHzf

MmRmHLHL

sfdcfdc

SMESSMES

fdcfdcf

==Ω===Ω===

=Ω===

μμ

μ

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