1

Voltage-mode Digital Pulse Skipping Control of aDC-DC Converter with Stable Periodic Behavior

and Improved Light-load EfficiencySantanu Kapat,Member, IEEE, Bipin Chandra Mandi, and Amit Patra,Member, IEEE

Abstract—A pulse skipping modulation (PSM) technique im-proves the light load efficiency in a DC-DC converter byselectively skipping a few clock pulses. However, in existing PSMschemes, the number of charge and/or skipped cycles cannotbe pre-defined. Therefore it is difficult to predict the rippleparameters and ensure a stable periodic behavior. Further itbecomes difficult to further minimize power losses under lightload conditions. This paper proposes a voltage-mode digital pulseskipping modulator which uses a digital pulse-width-modulator(PWM) as a building block, thus making it easy to operate thesystem in both PWM and PSM modes. Unlike in existing PSMschemes, the sequence and the count of charge and skip cyclescanbe fully pre-specified in the proposed scheme, with the number ofskip cycles optimally chosen to maximize the efficiency. Stabilityanalysis is carried out using discrete-time modeling, whichprovides guidelines to ensure a stable periodic operation withpredictable ripple parameters. Small-signal modeling anddesignof the proposed PSM scheme are discussed. A prototype buckconverter was fabricated and tested. The proposed control schemeis implemented using an FPGA device, and the experimentalresults fully support the analytical predictions.

Index Terms—DC-DC converter, light load efficiency, digital-pulse-width-modulator, pulse skipping control, stability.

I. I NTRODUCTION

A n ever-increasing demand for improving battery-life inportable electronic devices makes it necessary to save

battery energy under light load conditions, particularly duringa sleep or a standby mode. The well-known pulse width mod-ulation (PWM) technique offers several benefits in a DC-DCconverter, such as constant switching frequency operation[1].However, efficiency under light load conditions significantlydegrades with the load current. Thus switching events need tobe minimized for reduction in gate driver losses using special-ized control strategies [2]– [4]. A pulse frequency modulation(PFM) technique reduces switching and gate drive losses of aDC-DC converter by decreasing the switching frequency withthe load current [2]. There exist numerous PFM techniques,such as variable-frequency current-mode control [5], constant-on-time control (COT) [6], adaptive on-time control [7], andhysteretic control [8]. However, variable switching frequencyoperation in PFM schemes causes difficulty in designing aninput filter [9]. This may lead to problems of conducted EMIand voltage regulation, along with the possibility of instability.

This work was carried out at the Embedded Power Management Lab.,Department of Electrical Engineering, Indian Institute ofTechnology (IIT)Kharagpur, West Bengal-721302, India (e-mail: santanu.kapat@ieee.org,bipin0087@gmail.com, and amit.patra@ieee.org).

Pulse train (PT) control considers high and low pulses withdiscrete frequencies [10]. On-state time durations for highand low pulses are set using either predefined values [11],generated using peak current mode control [12] or digitalcontrol [13]. However, existing PT control schemes result inunpredictable high periodic behavior [13].

A pulse skipping modulation (PSM) scheme improves lightload efficiency in a DC-DC converter by skipping a fewclock pulses [14]– [17]. A classical PSM scheme in [14]suffers from (i) reduction in efficiency, (ii) increase in ripplemagnitude with the load resistance and/or the input voltage,and (iii) non-monotonic spectral composition [15]. Even avoltage controlled PSM [16] cannot ensure monotonic spectralcomposition over a wide parameter range [18]. A burst-modetechnique [19], [20] considers multiple charging cycles inthecontext of PSM.

A multi-mode PWM/PFM technique improves light loadefficiency and also utilizes fixed-frequency operation of PWMcontrol [21]. Such techniques have been gaining increasedpopularity in digitally controlled DC-DC converters [22]–[29].However, a smooth PFM/PWM transition is difficult to achievebecause of their structural difference and a variable frequencyoperation in PFM causes EMI problems. Control objectives ina digitally controlled DC-DC converter are (i) improving lightload efficiency, (ii) developing multi-mode controllers withfast response and seamless transition across various modes,(iii) regulating the output voltage within a permissible ripplelimit, and (iv) achieving a stable periodic behaviour over awide operating region.

This paper proposes a voltage-mode digital pulse skippingmodulator (VDPSM) that allows one to fully customize theoccurrence and the count of charge and skip cycles. Thisis helpful to minimize power loss and to achieve a stableperiodic behaviour with predictable ripple parameters. Small-signal modeling and controller design steps for the proposedVDPSM are discussed. The proposed VDPSM achieves seam-less PSM/PWM transition. A prototype buck converter isfabricated, and the proposed controller is implemented usingan FPGA device.

This paper is organized as follows. Section II introduces theproposed VDPSM. Discrete-time modeling and stability anal-ysis are discussed in Section III. Section IV presents small-signal modeling and design guidelines. Section V discusseshardware implementation and establishes the performanceimprovement with test results. Section VI concludes the paper.

This is the author’s version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.The final version of record is available athttp://dx.doi.org/10.1109/TPEL.2015.2455553

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II. T HE PROPOSEDVOLTAGE-MODE DIGITAL PSM

A. Working principle of the proposed scheme:

Fig. 1. The proposed pulse skipping modulation in a buck converter:ve andu are the error voltage and the gate signal;Fs andFclk indicate switchingclock and (digital) controller clock:N indicates the number of skipped pulses.

Fig. 2. The proposed voltage-mode digital pulse skipping modulator: uC

is the output of the voltage-mode DPWM controller;Fcon can be logic 1 orlogic 0 and accordinglyuPSM will generate a charge pulse or a skip pulseat the rising edge ofFs; vr[k] is the discrete-time ramp signal.

Figure 1 shows the schematic of a buck converter usingthe proposed PSM scheme. This primarily consists of (i) a‘voltage-mode digital pulse skipping modulator (VDPSM)’and (ii) a ‘real-time skip cycle adaptation’ block. The formergenerates a periodic sequence of one charge cycle followedby N number of skipped cycles, while the latter updatesNin real-time for improving the efficiency without exceedingagiven ripple voltage limit. Based on requirements, the numberof charge cycles can be further increased. The VDPSM blockin Fig. 2 consists of a counter-based digital-pulse-width-modulator (DPWM), in which a free-running counter getsincremented at every rising edge of the controller clockFclk

with time period tclk. The counter is reset when the countvalue exceeds the upper limitNup; thus it generates a fixed-frequency switching clockFs with time period(Nup + 1) tclk.

The outputvc[n] of the DPWM voltage controller [Gc(z)] iscompared with the digitally generated ramp signalvr[k] [30],[31]. The comparator output is latched using an edge-triggeredD flip-flop to generateuC. This is logically ‘ANDed’ with theoutput of a multiplexer (MUX) in which ‘PSMEnable’ actsas a select line. If ‘PSMEnable=1’, the MUX output enables

a PSM operation; otherwise, the system operates completelyunder the DPWM. The control signal ‘Fcon’ (in Fig. 2) canbe set to either logic 1 or logic 0, and accordinglyuPSM willgenerate a charge pulse or a skip pulse at the rising edge ofFs. A logic state ofFcon is programmable and can be fullycustomized.

Fig. 3 shows various waveforms of a buck converter usingthe proposed PSM for a case study example of a periodicwaveform. This consists of one charge cycle followed byNskip cycles. For this periodic sequence, the DPWM controllerGc(z) is active only during a charge cycle, which is disabledduring skipped cycles for additional power saving. Thus thecontroller computation takes place only once throughout theperiodic interval. The controller inputve[n] is obtained bydown sampling the A/D converter output by a factor of(N + 1) as shown in Fig. 1. IfuPSM = 1, the systemundergoes a charge pulse; otherwise, the current switchingcycle is skipped. The DPWM controller generates the desiredclosed-loop duty ratio such that the injected energy duringacharge cycle is exactly balanced during skipped cycles. Unlikethe existing PSM schemes where the sequence and the countof charge/skipped cycles can vary arbitrarily with the systemand controller parameters as well as with the operating point[18], the proposed PSM provides the flexibility to configurein real-time. This helps toachieve a stable periodic behaviorand to further improve efficiencywith a predictable voltageripple.

Based on the load current, a PSM operation can be initiatedby setting ‘PSMEnable=1’ (in Fig. 2); otherwise, the DPWMblock controls the converter. The MUX output is ‘ANDed’with the DPWM outputuC. Thus a smooth PSM-to-PWMtransition can be achieved by simply setting ‘PSMEnable’=0.

B. Real-time skip cycle adaptation:

From the capacitor currentiC and output voltagevo wave-forms in Fig. 3, the voltage ripple∆v is expected to increasewith the skip cycle countN . Thus the ‘real-time skip cycleadaptation’ block in Fig. 1 is intended to maintain the outputvoltage ripple within a specified limit,vH. This uses thesampled error voltageve[k] (which is sampled at every risingedge of the switching clockFs) and adjustsN in real-timeuntil the ripple voltage meets the specification∆v ≤ vH.

C. Reconfigurability of the proposed scheme:

Using design parameters, such astclk, ∆vH, samplingfrequency, etc., the proposed PSM (in Fig. 1) can be configuredto realize a variety of control schemes.

1) Adaptive hysteretic and PFM control:The ripple (volt-age) limitvH can be used as a hysteresis band for the samplederror voltageve[k] in Fig. 1. The hysteresis band can beoptimized with the operating point to minimize power losses,which can be computed off-line and stored using a look-up-table (LUT). A further adaptation can closely resembleadaptive on-time PFM control.

2) Pulse train control: The proposed control can be con-figured to PT control by using bi-frequency DPWM. On-timecan be adjusted either by using peak current mode control [12]or by using predefined values [10].

This is the author’s version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.The final version of record is available athttp://dx.doi.org/10.1109/TPEL.2015.2455553

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3

Fig. 3. Key waveforms of a DCM buck converter under the proposed scheme.

3) Existing PSM and burst-mode schemes:The proposedcontrol resembles a voltage controlled PSM [16] and a clas-sical PSM, in which the MSB of the sampled error voltagedecides whether to generate a charge pulse or a skipped pulse.The latter uses a fixedvc to generate the (open-loop) on-time during a charge pulse. This can be further extended toburst-mode control by incorporating a hysteresis band andcomparing with the sampled error voltage.

III. M ODELING AND ANALYSIS OF THE PROPOSEDPSM

Consider the proposed PSM (in Fig. 1) with uniform voltagesampling. For a predefined sequence of one charge pulse fol-lowed byN skipped pulses as shown in Fig. 2, this resemblesa Discontinuous conduction Mode (DCM) operation with aneffective time period(1 +N)T and an upper limit on on-timeas ton ≤ T . Given an arbitrary value ofN , the objectives inthis section are to ensure (i) output voltage regulation and(ii)fast-scale stability. The former can be addressed by suitablydesigningGc(z) for sufficient closed-loop DC gain using a PIcontroller or more generally a lag-lead compensator [1]. Thefinal task is to ensure fast-scale stability in order to avoidthepossibility of sub-harmonic oscillations.

A. Discrete-time modeling

In a buck converter during theON time of the MOSFET,the inductor currentiL ramps up and the system is said to bein Mode 1. During theOFF interval, i.e., during Mode 2,iLfalls until it reaches zero. IfiL continues to remain at zeroduring any time of a clock period, the system is said to bein Mode 3. State-space models of these three modes can be

written as•

x = A0x + (A1x +Bvin)u+A1x (1− u) , vo = Cox, (1)

where x =

[iLvC

]

; A0 =

[0 00 −Rn/RC

]

;

A1 =

[− (rL +RnrC) /L −Rn/L

Rn/C −Rn/RC

]

; B =

[1/L0

]

;

Co =[RnrC Rn

]; Rn = R/ (R + rC) ,

where the control inputu = 1 for Mode 1 andu = 0 forMode 2; to indicates the initial time of an active mode. AsiL = 0 in Mode 3, the state-vectorx reduces tovC, a scalarvariable, and the state-space equation will take the form as

dvC/dt = −vC/ [(R+ rC)C] , vo = vCR/ (R + rC) . (2)

Let the inductor current and the output voltage at the startof the nth clock pulse bein andvn, and those at the end ofthe clock period bein+1 and vn+1, respectively. For a buckconverter, operating under DCM, a discrete-time map can bederived using solutions of state-space equations in (1) and(2)using their individual intervals of operation as given in [32].A second-order discrete-time model of a DCM buck converterwill be reduced to a first-order model within+1 = in = 0.For a DCM operation consisting of one charge pulse followedby N skipped pulses as considered in Fig. 2, a discrete-timemap can be derived by applying Taylor series approximationand considering terms up to the2nd order, which is written as

vn+1 = αvn +βt2onvin (vin − vn)

vn, where ton ≤ T,

α = exp

[− (N + 1)T

(R+ rC)C

]

, β =R

2 (R+ rC)LC.

(3)

B. Stability analysis

4 5 6 7 8 9 10

3.3

3.3

3.3

Input Voltage (V)

Sam

pled

Out

put

Vol

tage

(V

)

0.05 0.1 0.15 0.2 0.25 0.3

3.2

3.3

3.4

Load Current (A)

Sam

pled

Out

put

Vol

tage

(V

)

Fig. 4. Bifurcation diagrams of a DCM buck converter under the proposedcontrol with kp = 50, ki = 50, and (a)R = 100 Ω and (b)vin = 8 V.

Consider a discrete-time proportional-integral (PI) controlleras follows

vc[n] = kpve[n] + uI[n], (4)

whereuI[n] = uI[n−1]+kive[n], ve[n] = (vref − vn); kp andki indicate proportional and integral gains in discrete domain.Referring to Fig. 3, on-timeton can be derived as

ton = [kp (vref − vn) + uI[n]] /mr. (5)

This is the author’s version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.The final version of record is available athttp://dx.doi.org/10.1109/TPEL.2015.2455553

Copyright (c) 2015 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.

4

0 200 400 600 800 1000

3

3.5

Integral Gain (ki)

Sam

pled

Out

put

Vol

tage

(V

)

5 10 15 20 25 30 35 40 45

3.25

3.3

3.35

Number of Skipped Cycles (N)

Sam

pled

Out

put

Vol

tage

(V

)

Fig. 5. Bifurcation diagrams of a DCM buck converter under the proposedcontrol using the nominal parameter set and (a)N =5 and (b)ki=50.

Substituting (5) into (3), the closed-loop discrete-time mapunder the proposed VDPSM can be derived. The objective isto justify stability of a periodic orbit of time period(N + 1)T .Using a proportional voltage controller, i.e.,uI[n] = 0, theclosed-loop discrete-time map can be linearized around thereference voltagevref using Taylor series as follows

∂vn+1

∂vn= α+

∂f (vn)

∂vn

∣∣∣∣vn=vref

= α, where

f (vn) =

[

βk2pvin (vref − vn)2(vin − vn)

vnm2rT

2

]

.

(6)

It can be shown that0 < α < 1; thus the closed-loop converterusing a proportional controller is stable, irrespective ofthecontroller gain. An analytical stability condition is difficultto derive using a PI controller because of the presence ofthe memory element. However, bifurcation diagrams can benumerically obtained using the discrete-time map in (3) alongwith (5) for justifying stability of the closed-loop converter. Ina switching converter, a bifurcation diagram gives a panoramicview of stability status of a periodic orbit for a smoothvariation in parameter(s) [34], in which stroboscopic samplingis considered at the rate of the switching frequency. For astable periodic behavior using this proposed PSM with aperiodicity(N + 1)T , the discrete-time map in (3) eventuallyconverges to a fixed-pointvn+1 = vn = v∗ in successiveiterations. The diagrams in Fig. 4 demonstrate stable periodicbehavior in a DCM buck converter using the proposed schemeover a wide range of input voltage and load current. Thediagrams in Fig. 5 clearly show that the closed-loop buckconverter under the proposed PSM remains stable for a widerange of integral gain and the number of skipped cycles.

It is reasonable to consider a PI controller in a DC-DC con-verter under light load conditions. However, a PID controlleror more generally a discrete-time lag/lead compensator willbe needed to improve the dynamic performance under highload current conditions, where the converter operates undercontinuous conduction mode (CCM). The DPWM voltage con-troller provides the complete flexibility of real-time controllerreconfiguration as well as online auto-tuning [30], [31].

C. Effects due to finite duty ratio resolution:

In a digitally controlled converter, a ramp signal is generatedusing a counter which gets incremented at the rising edge ofthe controller clocktclk. This staircase effect in a ramp signal(in Fig. 2) results in finite duty ratio resolution∆dn = tclk/T .For the voltage loop with uniform sampling, the on-time in (5)of the proposed digitally controlled VDPSM is modified as

t∗on = ∆dnT × ceil (ton/T∆dn) = tclk× ceil (ton/tclk) . (7)

For the proposed scheme, duty ratio resolution becomes∆dn = 0.002 or 0.2 % fortclk = 10 ns andT = 5 µs. Hencefinite duty resolution seems to have an insignificant impacton the closed-loop stability as well as steady-state regulation.Hence its effect is neglected throughout the rest of this paper.

IV. D ESIGN OF THEPROPOSEDPSM

A. Small signal modeling and discrete-time compensation

Following a methodology similar to the one presentedin [16] (in Sec. IV), the piecewise linear models for theinductor current and the output voltage can be obtained. Fora full period of the waveform comprising one charging pulsefollowed byN skipped pulses, the averaged dynamics of theinductor currentiL and the output voltagevo can be derivedas

diLdt

=vind1ML

−2iLvo

d1T (vin − vo),

dvodt

=T

MLC

[2MLiL

T−

vind21

2−

2M2L2iL2vo

d21T2 (vin − vo)

2 + d21vo

]

−voRC

, (8)

whered1 indicates the duty ratio related to on-timeton duringa charge pulse, i.e.,d1 = ton/ [(N + 1)T ]. Please referSec. IV in [16] for further details about the derivation in (8),whereM denotes the number of clock cycles in a full period ofthe waveform, i.e.,M = (N + 1). This consists of one chargecycle followed byN skipped cycles as shown in Fig. 2.

1) DC Analysis: Incorporating small perturbationsiL, vo, d1, and vin around their steady state valuesIL, Vo, D1, andVIN respectively, the dc operating point canbe determined by substituting in (8) the steady values of thevariables under consideration. The equations for calculatingthe dc operating point can be expressed as

D1VIN

ML−

2ILVo

D1T (VIN−Vo)= 0, 2IL

C−

T

MLC

[VIND

2

1

2 +2M2

L2I2

LVo

D2

1T 2(VIN−Vo)

2 −D21Vo

]

−Vo

RC= 0,

(9)

2) Linear Small Signal Model:Perturbed (linear) smallsignal model can be derived using Taylor approximation as

diLdtdvodt

=

[a11 a12a21 a22

]

︸ ︷︷ ︸

Abuck

[

iLvo

]

+

[b11 b12b21 b22

]

︸ ︷︷ ︸

Bbuck

[

d1vin

]

,

(10)

This is the author’s version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.The final version of record is available athttp://dx.doi.org/10.1109/TPEL.2015.2455553

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5

Fig. 6. Block diagram representation of the proposed PSM.

where a11 = −2Vo

D1T (VIN−Vo), a21 = −4MLILVo

D2

1TC(VIN−Vo)

2 + 2C,

a12 = −2ILVo

D1T (VIN−Vo)2 −

2ILD1T (VIN−Vo)

,

a22 = −1

RC−

2MLI2

L(VIN+Vo)

D2

1TC(VIN−Vo)

3 +D

2

1T

MLC,

b11 = 2ILVo

D2

1T (VIN−Vo)

+ VIN

ML, b12 = 2ILVo

D1T (VIN−Vo)2 + D1

ML,

b21 = (2Vo−VIN)D1T

MLC+

4MLI2

LVo

D3

1TC(VIN−Vo)

2 ,

b22 = T

MLC

[4M2

L2I2

LVo

D2

1T 2(VIN−Vo)

3 −D

2

1

2

]

.

Thus the control-to-output transfer functionGvd(s) becomes

vo(s)

d1(s)=

b21s+ (a21b11 − a11b21)

s2 − (a11 + a22) s+ (a11a22 − a12a21). (11)

Figure 6 represents a mixed-signal block diagram related tothe proposed PSM, in which a discrete-time voltage controllerGc(z) is considered. Using Fig. 2, the gain of the DPWMFm can be derived asFm = qT/tclk, whereq represents theDPWM voltage resolution. A zero-order-hold (ZOH) effectinherently exists as the error voltage is sampled at the samerate as the switching frequencyFs. Using an equivalentZOH concept [33], a discrete-time control-to-output transferfunction can be derived asGvd(z) =

(1− z−1

)Z [Gvd(s)/s].

Thereafter, the discrete-time compensator can be directlyde-signed in the digital domain and standard design approachescan be applied based on time domain (using root-locus) orfrequency-domain specifications (using the Bode and Nyquistplots). In this paper, a digital PI controller in (4) is consideredwith kp = 50 andki = 0.1. In direct digital domain, equivalentgain and phase margins are found to be 40 dB and 42 degrees,respectively.

B. Steady-state ripple characterization

Using capacitor charge balance, different timing parametersin Fig. 3 can be derived ast1 = LVref/ (Vin − Vref), t2 =2VrefLC/ (Vin − Vref), t3 =

√

2LC (Vin − Vref) /Vin, t4 =L/R, t5 = (2C/R)− [LVin/2R (Vin − Vref)], and on-time

ton =√

[2v2refL (1 +N)T ] / [(vin − vref) vinR]. (12)

Steady-state (output) voltage ripple for the desired periodicbehavior using thevcon in Fig. 2 can be formulated as

∆v =(vin − vref)

L

ton −Lvref

(vin − vref)R

×

[vin

2vrefC

ton −Lvref

(vin − vref)R

+ rC

]

.(13)

For a given operating point, duration of on-time in (12)increases with the number of skipped cyclesN , which also

46

810

00.1

0.20.3

0

20

40

60

80

Input Voltage (V)Load Current (A)

Out

put V

olta

ge r

ippl

e (m

V)

Fig. 7. Ripple voltage variation using the proposed PSM withN = 5.

increases the output voltage ripple in (13). However, forton ≥ T , the number of charge pulses needs to be increased;otherwise, the amount of the injected energy during a chargepulse may not be sufficient to regulate the output voltage.For a fixedN , for exampleN = 10, Fig. 7 shows that theoutput voltage ripple∆v increases almost linearly with theload current; however,∆v changes only slightly with the inputvoltage.

V. HARDWARE IMPLEMENTATION

A buck converter prototype is developed and the controlleris implemented using an FPGA device. A nominal parameterset is considered as:T = 5 µs, L = 10 µH, C = 470 µF,io ∈ [10 mA, 4A], vin ∈ [4, 8] V, a voltage ripple limitvH =50 mV, andvref = 3.3 V. For the prototype signal conditioningcircuits, an 8-bit pipeline ADC (AD9280) is considered tosample the output voltage. The PI controller parameters in (4)are taken to bekp = 50 andki = 0.1, and the frequency ofthe controller clock is 100 MHz.

A. Steady-state periodic behavior

Figure 8 indicates steady-state operations using existingPSM techniques and the proposed PSM forvin = 8 V andR = 100 Ω. A classical PSM in Fig. 8(a) exhibits aperiodicbehavior with a large ripple magnitude. Even the spectralcomposition for the voltage controlled PSM [16] has aperiodiccharacteristics [shown in Fig. 8(b)].

Fig. 10. Light-load efficiency in a buck converter under the proposed PSMscheme with the skipped cycle variation forvin = 5 V and vref = 3.3 V.

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Fig. 8. A buck converter using (a) classical PSM with 50% dutyratio (time scale 0.1 ms/div),(b) voltage controlled PSM in[16] and (c) the proposedPSM : From the top, FFT channel (20 dB/div and 125 kHz/div) shows the Fourier Transform ofiL; Ch 1 (0.5 A/div), Ch 2 (1 V/div), Ch 3 (5 V/div), andCh 4 (10 V/div) indicateiL, vo, u, andFs, respectively.

Fig. 9. A buck converter using the proposed PSM under different operating conditions each with time scale 8µs/div and number of skipped cyclesN = 5:Ch. 1, Ch. 2, Ch. 3, and Ch. 4 indicate inductor current, AC coupled output voltage, gate signal, and input current, respectively.

Fig. 12. Load transient response of a buck converter with PSM-to-PWM mode transition: Ch 1 (2 A/div), Ch 2 (1 V/div), Ch 3 (5V/div), and Ch 4 (5 V/div)indicate iL, vo, (inverted) load step command, andFs, respectively with time scales (a) 0.1 ms/div and (b) 20µs/div.

Fig. 8(c) shows that the proposed PSM technique achievesa stable periodic operation for a sequence of one chargecycle followed by five skip cycles, i.e., forN = 5. Thisrepresents a period DCM operation with an effective timeperiod (N + 1) × T = 6T . The FFT trace shows that thefundamental periodic component is located at 1/6th of thenominal switching frequency, i.e., at200/6 ≈ 33 kHz, andother harmonic components are located subsequently. Similarstable periodic behavior can be achieved for other case studysequences; thus stable periodic behavior can be ensured usingthe proposed scheme. This is generally not possible using the

existing PSM techniques.

B. Steady-state ripple characteristics

Fig. 9 shows steady-state output voltage ripple of the buckconverter using the proposed scheme under different operatingconditions forN = 5. Figures 9 (a) and (b) demonstrate that anincrease in load resistance from 33Ω to 100Ω (or a reductionin load current from 100 mA to 33 mA), the (output) voltageripple increases from 50 mV to 70 mV. However, a reduction ininput voltage from 8 V to 5 V does not significantly affect the

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7

voltage ripple as shown in Figs. 9 (b) and (c). Moreover, rippleparameters are more or less consistent with their estimatedvalues as shown in Fig. 7.

C. Measured efficiency and impact on skip cycle variation

Figure 10 presents the study comparing the effects of skipcycle variation (using the proposed PSM technique) on themeasured efficiency in a DCM buck converter. ForN = 0the proposed PSM scheme in Fig. 2 resembles a conventionalvoltage-mode PWM scheme. The PSM operation can beinitiated again simply by considering the skip cycle count tobeN > 0. Fig. 10 shows that the light-load efficiency signifi-cantly degrades using the fixed-frequency DPWM scheme. Anincrease in the skipped cycle count improves the efficiency;however, a fixedN is not enough to further improve theefficiency as the load current decreases. Thus it is importantto updateN using the ‘real-time skip cycle adaptation’ block,as discussed in Sec. II-B, in order to keep the ripple voltageless thanvH. This achieves the optimal PSM under the rippleconstraint. Further Fig. 11 shows that the optimal PSM closelyretained the improved efficiency of an optimal PFM scheme,while the latter results in continuous switching frequencyvariation with the load current. It is also clear that a fixedNis clearly not enough to retain the improved efficiency over awide (light) load current conditions. Thus the custom periodicsequence using the proposed PSM can achieve high energyefficiency in a DC-DC converter under light load.

D. Smooth PSM/PWM transition

For an 8-bit ADC with a 2 V span (which maps to the max-imum input voltagevmax = 10 V ), a change in the2nd LSBof the error voltageve[n] of nearly 80 mV deviation in outputvoltage is enough to detect a large transient. Fig. 12 demon-strates transient performance using the proposed controller fora step change in load current from 30 mA to 3 A. This willcause a change in the2nd or higher LSB ofve[n]; thus alarge transient is detected and a PSM-to-PWM mode transitiontakes place. Because of uniform error voltage sampling andslower voltage dynamics, a transient detection is delayed byone clock periodT as shown Fig. 12 (b). Thereafter,uPSM

Fig. 11. Improvement in light-load efficiency in a buck converter using theproposed PSM scheme forvin = 5 V and vref = 3.3 V.

is set to logic 1, and the closed-loop control is taken overby the conventional DPWM. AlsouPSM continues to remainhigh until the converter enters deep into DCM. Because ofsharing the voltage controllerGc(z), a smooth PSM-to-PWMtransition is achieved with an output voltage undershoot of450 mV and a settling time of 36µs.

E. Summary of design guidelines

Design steps of the proposed PSM are summarized below:(a) Choose a suitable voltage ripple bandvH based on designspecifications. The ‘real-time skip cycle adaptation’ block inFig. 2 automatically adjustsN to maintain the voltage ripplewithin vH in order to achieve improved light load efficiency.(b) Using small-signal models in Sec. IV-A2, design thevoltage controllerGc(z) following standard design steps in[1] as in a CCM operation. Either the same controller canbe used orGc(z) can be reconfigured to be a PI controllerduring light load, ensuring the stability of the proposed PSM.

VI. CONCLUSIONS

This paper proposed a voltage-mode digital PSM techniquethat would allow one to customize the sequence and the countof charge and skipped pulses in real-time. Thus the power losscould be fully optimized by appropriate choice of the numberof skip cycles. The proposed PSM uses a voltage-modeDPWM controller to generate the gate signal during a chargecycle, which can achieve a seamless transition to a PWMscheme when the load current increases. Stability analysiswascarried out using discrete-time models, which would be usefulto achieve stable periodic behavior with predictable rippleparameters. Small-signal modeling and design of the proposedPSM scheme were discussed. A prototype buck converter hasbeen developed and tested in the laboratory. The voltage-mode digital PSM scheme was implemented using an FPGAdevice. The experimental results fully establish the theory andthe analytical predictions made in this paper. The proposedPSM reduces hardware resources and improves light loadefficiency with a stable operation. This will be an excellentmulti-mode digital controller for low power high frequencyDC-DC converters operating in a wide load current range.

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This is the author’s version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.The final version of record is available athttp://dx.doi.org/10.1109/TPEL.2015.2455553

Copyright (c) 2015 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.

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Santanu Kapat (M’10) received his M. Tech andPh.D. degrees in electrical engineering from the IITKharagpur, in 2006 and 2010, respectively.

He was a visiting scholar in the ECE Department,UIUC, and a research engineer at GE Global Re-search Bangalore. Presently he is an Assistant Pro-fessor in the Electrical Engineering department, IITKharagpur. His research interests include analysisand design of digital and nonlinear control in DC-DC converters, and applications to DVS, enveloptracking RFPA, LED drivers, and DC nano-grid.

Bipin Chandra Mandi received the B.E in elec-tronics and tele-communication engineering fromBengal Engineering and Science University, Shibpur,India in 2009 and M.E in electronics and tele-communication engineering from Jadavpur Univer-sity, Kolkata, India in 2011. Currently, he is pursuingPh. D in the electrical engineering dept., IIT Kharag-pur, India. His research interests include modeling,analysis and digital control of DC-DC converters.

Amit Patra (M’89) is a Professor at the Departmentof Electrical Engineering, Indian Institute of Tech-nology, Kharagpur. His current research interestsinclude power management circuits, mixed-signalVLSI design and embedded control systems.

He has guided about 20 doctorates and publishedmore than 200 research papers in various Journalsand Conferences. He is the co-author of two re-search monographs and carried out about 50 researchprojects with various Organizations.

This is the author’s version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.The final version of record is available athttp://dx.doi.org/10.1109/TPEL.2015.2455553

Copyright (c) 2015 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.