Voltage Control of Three-Stage Hybrid Multilevel

8/7/2019 Voltage Control of Three-Stage Hybrid Multilevel

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 10, OCTOBER 2010 2599

Voltage Control of Three-Stage Hybrid MultilevelInverter Using Vector Transformation

Saad Mekhilef, Member, IEEE, and Mohamad N. Abdul Kadir

AbstractThis paper presents a three-stage 18-level inverter de-sign with a novel control method. The inverter consists of a series-connected main high-voltage, medium-voltage, and low-voltagestages. The high-voltage stage is made of a three-phase, six-switchconventional inverter. The medium- and low-voltage stages aremade of three-level inverters constructed by H-bridge units. Theproposed control strategy assumes a reference-input voltage vec-tor and aims to operate the inverter in one state per sampling timeto produce the nearest vector to that reference. The control con-cept is based on representing the reference voltage in 60-spacedtwo-axis coordinate system. In this system, the inverter vectors di-mensions are integer multiples of the inverters dc voltage, and theexpression of the inverters vectors in terms of its switching vari-

ables is straightforward. Consequently, the switching signals canbe obtained by simple fixed-point calculations. The approach ofthe proposed control strategy has been presented, the transformedinverter vectors and their relation to the switching variables havebeen defined, and the implementation process has been described.The test results verify the effectiveness of the proposed strategy interms of computational efficiency as well as the capability of theinverter to produce very low distorted voltage with low-switchinglosses.

Index TermsConverters, DSP control, multilevel inverters(MLIs), pulsewidth modulation (PWM).

I. INTRODUCTION

MULTILEVEL inverter (MLI) refers to the class of in-

verters of output points that have more than two voltage

levels with respect to the negative terminal of the input sup-

ply [1]. The essential virtue of MLIs over the conventional

inverters are the capacity to have an output voltage and current

levels higher than those of the switching devices ratings; hence,

MLIs have been classified as high-power inverters [2]. Increas-

ing the number of levels of the MLI provides more steps for

approximating the desired output waveform and reduced har-

monic distortion and dv/dt stress. The main drawbacks of MLI

are: its circuit complexity, high cost due to application of more

components, and it is more difficult to control. Despite this, re-cent studies recommended MLI topologies for medium-voltage

applications [3].

Manuscript received October 25, 2009; revised May 4, 2010; accepted May13, 2010. Date of current version September 17, 2010. Recommended for pub-lication by Associate Editor F. Blaabjerg.

The authors are with the Department of Electrical Engineering, Univer-sity of Malaya, 50603 Kuala Lumpur, Malaysia (e-mail: [email protected];[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2010.2051040

A. Review of Hybrid MLI Topologies

The basic MLI circuits have equal or equally divided input

dc voltages, and its number of levels is linearly related to the

number of switching devices [4]. The maximum number of

levels that can be achieved with basic MLI topologies is limited

due to cost, size, and reliability considerations. On the other

hand, increasing the number of levels enhances the MLI merits.

The approach of asymmetrical MLI based on supplying the

inverter with unequal input voltages has been found to have

the capability of producing higher number of levels for the

same number of components compared to the basic MLI [5].With asymmetrical MLI, the highest voltage stage operates at

lowest frequency; therefore, switch utilization can be improved

by selecting the switch characterized by low-conducting losses

for high-voltage stage, and that of fast-switching speed for the

high-frequency stage [6].

The MLI design can further be optimized by hybridization,

i.e., to create an MLI by cascading smaller dissimilar inverter

circuits [4]. Constructing the inverter with cascaded stages of

different topologies leads to considerable reduction in the num-

ber of dc sources required. This has been done in various ways,

such as connecting H-bridge three-level stage(s) in series with

neutral-point-clamped three-level stage [7], [8] or to six-switch

two-level stage [9].

B. Review of Hybrid MLI Control

Many studies have reported the control of the MLI. Both

high- and low-frequency switching approaches have been con-

sidered. Multicarrier pulsewidth modulation (PWM) strategy

has been reported [10]. The space-vector modulation (SVM)

control has been introduced and implemented [11][13]. And

the carrier-based SVM has been developed for MLIs with any

number of levels [14]. The three approaches are examples of

high-switching-frequency strategies.

Fundamental frequency switching with selected harmonics

elimination has been implemented, exploiting the high number

of levels provided by asymmetrical MLI to reduce the switching

losses [15]. Switching-angles control methods, however, require

precalculated switching-angles lookup table [16]. Fundamental

frequency SVM has been applied in [17]. The method is shown

to be reasonable due to high number of levels provided by the

four-stage asymmetrical inverter.

C. Cascaded H-bridge MLI

One of the basic MLI topologies is the cascaded H-bridge

cells. This topology has the advantage of modular structure

where the inverter consists of small identical cells. The main

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2600 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 10, OCTOBER 2010

drawback of this topology is the requirement for high number

of isolated dc sources. The k-cell per arm inverter has (2k + 1)levels and requires 3kisolated dc sources.

Thenumber of levels can be greatly increased when asymmet-

rical sourcing is adopted [17]. In asymmetric cascaded inverter,

individual cellsdc voltages differ causing differentvoltage steps,

and therefore, higher number of levels for the same circuit topol-

ogy. It has been reported by many researchers that the maximum

number of uniform steps is achieved when the dc voltages of

the arm cells form a ratio of three geometric sequence [18].

Study of the appropriate voltage ratio shows that the mod-

ulation condition required to avoid high-frequency operation

at high-voltage stage is satisfied if any two adjacent voltage

levels can be achieved by switching the lowest voltage cells

only [18][20]. This condition is not satisfied with ratio of three

related dc sources, and hence, this selection is not appropriate

for PWM control. Yet, this ratio has been followed by some

designs that do not apply PWM control [17], [22][24].

D. Scope of This Paper

This paper aims to overcome the two main drawbacks of the

cascaded H-bridge MLI, which are the requirement of large

number of isolated dc supplies and high-switching frequency

of the high-voltage stage. The presented circuit saves the cost

of the dc supplies by reducing the number of the high-voltage-

stage sources to one. Avoiding high-switching frequency at the

high-voltage stage is insured by the suggested control strategy.

The contribution of this paper is to determine the switching state

based on overall inverter state rather than the arm-voltage level,

thus providing the advantage of the capability to avoid high-

switching frequency even with high-frequency PWM control of

the low-voltage stage.

A hybrid MLI with cascaded stages of two- and three-levels

inverters is presented in this paper. The inverter circuit and its

switchingvariables definition aregiven in Section II. Thecontrol

concept is introduced in Section III. DSP implementation is

described in Section IV. In Section V, selected test results of the

developed inverter and the control strategy are presented.

II. INVERTER TOPOLOGY AND SWITCHING STATES

A. Inverter Topology

The inverter circuit shown Fig. 1 consists of the main high-

voltage six-switch inverter with each output line in series totwo cascaded single-phase full-bridge inverters. The main and

H-bridge cells are fed by isolated dc sources of 9Vs , 3Vs , and

Vs , as shown in Fig. 1.

Compared to the asymmetricalMLI [17], the three main-stage

dc supplies have been replaced by one supply. Furthermore, in

the asymmetrical MLI, bidirectional current capability is re-

quired for the three high-voltage-stage supplies unless the load

power factor is always close to 1. While in this design, the bidi-

rectional current capability is not needed as long as the load is

not required to be operated in regenerative mode. The medium-

and low-voltage stages supplies are identical to those of the

asymmetrical MLI. However, due to the lower voltage levels,

Fig. 1. Eighteen-level inverter topology.

the cost of these supplies is much lower than that of the high-

voltage-stage supply. Therefore, considerable reduction in the

dc-source cost can be achieved with this topology.

In order to determine the number of levels of the inverter

circuit shown in Fig. 1, consider the voltage of any output point

(A, B, or C) with respect to the negative terminal of the 9Vsdc source. Output points voltages range between maximum of

(9 + 3 + 1)Vs = 13Vs , and minimum of (0 3 1)Vs =4Vs , with uniform step ofVs . Therefore, the cascaded inverterof Fig. 1 forms an 18-level inverter.

B. Voltage Vectors and Inverter States

The switching variables of the inverter are denoted by

{(xab c), (yab c), (zab c)}, where x is a binary digit (x [0,1]),while y and z are trinary digits (y,z [0,2]). The states of thehigh-, medium-, and low-voltage stages are determined by xab c ,

yab c , and zab c , respectively. The output voltage vector can be

represents in terms of the switching state, as shown in the fol-

lowing equation. Line voltages are represented in terms of the

switching variables in (1)

vabvbcvca

= 9Vsxa

xb

xb xcxc xa

+ 3Vsya

yb

yb ycyc ya

+ Vsza

zb

zb zczc za

.(1)

Phase voltages of the Y-connected load can be represented as

follows:

vanvbnvcn

= 1

3

vabvcavbc vabvca vbc

=Vs

3

2 1 11 2 1

1

1 2

9xa + 3ya + za9xb + 3yb + zb9x

c+ 3y

c+ z

c

. (2)


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MEKHILEF AND KADIR: VOLTAGE CONTROL OF THREE-STAGE HYBRID MULTILEVEL INVERTER USING VECTOR TRANSFORMATION 2601

Fig. 2. Voltagevectorsof the18-levelinverter as thesum of thethreecascadedinverters vectors.

The voltage vector is achieved by Parks transformation given

in (3)

vDvQ

=

1 0.5 0.5

0

3

2

3

2

van

vbn

vcn

. (3)

Substituting (2) into (3) gives

vDvQ

= Vs

1 0.5

0.5

03

23

2

9xa + 3ya + za

9xb + 3yb + zb

9xc + 3yc + zc

. (4)

Using (4), the voltage vector of any inverter state can be

achieved. Alternatively, the voltage-vector diagram of the three-

stage inverter is drawn by two superposition steps. First, the

vector diagram of the three-level medium-voltage-stage inverter

(composed of 19 vectors) is drawn at the end of each of the

sevenvectorsof thehigh-voltagestage. Then, thevector diagram

corresponding to low-voltage stage has been superimposed at

the ends of resultant vectors, as shown in Fig. 2.

The modulation condition has not been met by this design,

i.e., when controlling the inverter by carrier-comparison PWMstrategy, the medium- and high-voltage stages will be subjected

to high-switching frequency. However, the resolution of the 18-

level inverter provides sufficiently low distorted voltage without

including high-switching-frequency PWM.

C. Voltage Vectors in gh Axis System

The 60-spaced gh coordinate system, shown in Fig. 3, willbe used to represent the voltage vector in the proposed control

algorithm. This system allows simpler and faster calculations

as it is tightly related to the inverter states voltage vectors.

Fig. 4 shows that the voltage vectors of the high-voltage-stage

inverter have gh coordinates, which are integer multiples of the

Fig. 3. gh-axis coordinate system used to represent the voltage vector.

Fig. 4. Voltage vectors corresponding to high-voltage stage and their gh di-mensions.

Fig. 5. Voltage vectors of a three-level inverter and their gh dimensions, Vmis the dc-supply voltage.

high-voltage dc source. This also applies also to the three-level

medium- and low-voltage-stage inverters, as shown in Fig. 5.The

integer coordinates of the inverter vectors allow the inverter

control by simple fixed-point calculations.

D. High and Medium States Domains

Each of the 18-level inverter vectors can be represented by

the addition of three vectors, one has a norm of 9Vs or 0 de-

termined by xab c , the second has a norm of 6, 33, 3, or 0Vs


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Fig. 6. Shaded seven hexagons represent the domains of the high-voltage-

stagevectors. The rightmost small hexagonrepresents the domain of themediumstate [100,200].

determined by yab c , and the third has a norm of 2,

3, 1, or

0Vs determined by zab c . With the exception of the outmost vec-

tors, most of the 18-level inverter vectors can be represented

by more than one combination of the three-stages voltage vec-

tors. For example, vector V1, shown in Fig. 2, is represented as

Vh1 + Vm1 + Vl1 and as Vh1 + Vm1 + Vl1, where Vh , Vm ,

and Vl are the voltage vectors corresponding to high-, medium-,

and low-voltage stages, respectively.

It is highly desirable for the switching frequency of the high-voltage stage to be reduced. The control algorithm explained in

the next section aims to hold the high-voltage vector as long as

the reference vector can be represented by adding other medium

and low vectors to this high-voltage vector. We shall refer to

the hexagonal area marked by the vectors reachable through a

given high-state vector by its domain. The seven domains of

the high-voltage stage vectors are shown in Fig. 6.

Dividing the space-vectors area into domains is extended to

the middle-stage vectors. Nineteen hexagons, each represents

the area covered by low-voltage-stage vector diagram, can be

drawn within each of the seven high-state domains at the tips

of the 19 medium voltage vectors. For illustration, one of the

middle-state domains hexagons is shown in Fig. 6. With xab c =100 and yab c = 200, the low-voltage-stage selection will coverthe small hexagon marked at the rightmost side of Fig. 6, we

shall refer to it as the domain of state [100,200].

As shown in Fig. 6, within the grand hexagon, some of the

regions are covered by exactly one high-state domain without

overlap. If the reference vector is located in such area, the con-

troller should select the corresponding high state. Other areas

are covered by two or three high-state domains, in this case,

there is more than one option in the selection ofxab c . We have

exploited this to minimize the switching actions at the higher

voltage stages. The medium-state domains also overlap and this

will be utilized in similar way.

Fig. 7. Flowchart of the 18-level inverter control algorithm with state of persampling interval.

III. CONTROL STRATEGY

A. Control Algorithm

The controller generates the switching signals{xab c , yab c , zab c} in order to produce the best approxi-mation of the input reference-voltage vector during the

following switching interval. The calculated state ensures the

minimum switching actions and the inverter operates with one

switching state during the entire sampling interval.

Thenextswitching state is determined, as illustrated in control

algorithm flow diagram shown in Fig. 7. This process is carried

out in three consecutive stages: the high, medium, and low

stages. Each stage considersits previous outputin thecalculation

of its new state. The previous output is provided by the memory

blocks (Z1 ), where the previous state is needed to achieve

minimum switching actions.


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Thereferencevoltage of the medium (and low) voltage stages,

denoted in Fig. 7 by medium (low) reference, is determined by

subtracting the voltage vector of the next high (medium) voltage

stage state from the reference vector. The next-state voltage

vector has been obtained from the simple relationship between

the switching state and the gh components of the voltage vector

that can be deduced from Figs. 4 and 5 as follows:

VgVh

= Vdc

1 1 00 1 1

abc

(5)

where is the switching variable that has been denoted by x,

y, and z for the high-, medium-, and low-voltage stages, respec-

tively, and Vdc is the corresponding-stage dc voltage. Equation

(5) is represented by the GH(x) and GH(y) blocks in Fig. 7.

B. High-Voltage State Determination

Following the notation given in Fig. 3, the reference vector

gh components are calculated as follows:

gre f = |Vre f|

cos re f sin re f3

hre f = |Vre f|

2sin re f3

. (6)

The calculation ofxab c begins by the determination, if the

reference vector is located in the domain of the current high-

voltage state. If so, then xab c holds its value during the next

switching interval. Otherwise, the nearest high-voltage state is

determined by comparing the reference to the seven high-state

domains. If the reference is located in more than one domain,

the controller selects xab c , which is nearer to the initial value.

C. Medium-Voltage State Determination

The middle reference is calculated by subtracting the voltage

vector corresponding to the next xab c from the input reference-

voltage vector. The medium stage holds its state if the medium

reference voltage is located within its domain.

If the reference vector is not within the current state domain,

the medium switching state will be changed to the nearest state,

where each of the medium state vectors is compared to the

medium reference to determine if the medium reference is lo-

cated within its domain. If the reference is located within more

than one domain, the states associated with these domains arecompared to the initial medium state and the one reachable with

minimum transition is taken as the next state.

D. Low-Voltage State Determination

The reference voltage for the low-voltage stage is determined

by subtracting the vector corresponding to the calculated yab cfrom the medium-stage reference vector, as shown in Fig. 7.

Applying (5) for the low-voltage stage, we have

Vg ,LVh,L

= Vs

1 1 00 1

1

zazb

zc

(7)Fig. 8. Load phase voltage measured with different values of reference ampli-tude and the corresponding frequency spectrum. The reference-voltage fre-quency is 50 Hz. (a) Reference-voltage amplitude is (a) 100%, (b) 80%,

(c) 60%, (d) 40%, and (e) 20%.


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Fig. 9. Fundamental voltage amplitude and THD variation with the referenceamplitude.

which gives

zazbzc

= 1

3Vs

2 11 11 2

Vg re f,low

Vh re f,low

. (8)

In (8), the three switching variables zab c are determined from

the two equations expressed in (7) in the matrix form. The third

equation needed to find the specific solution assumes the three

variables add up zero. The solution of (8) is treated as a linear

space of solution from which one or two specific solutions can

be obtained by adding a constant to zab c that sets the minimum

z to 0 or the maximum z to 2. When two solutions obtained theone nearer to the initial state is selected.

IV. DSP IMPLEMENTATION

The control algorithm has been implemented using DSP con-

troller board eZdsp F2812. The 150 MHz, fixed-point, low-cost

CPU, executed the algorithm with a sampling frequency exceed-

ing 45 kHz and using the on-chip memory only, this reflects the

computational efficiency of the proposed algorithm.

A 16-bit input port has been allocated for the reference in-

put. The 8 MSBs have been assigned as the reference-voltage

amplitude, where the step dc voltage (Vs) is assumed to be

equivalent to (10)h . The subscript (h) indicated that the num-ber is represented in the hexadecimal system with this scaling,

the maximum reference amplitude (FF)h corresponds to refer-

ence amplitude, which is approximately equals to 15.94Vs . This

limit is justified by the fact that the maximum norm of refer-

ence vector located within the hexagon formed by the 18-level

inverter vectors is 14.72Vs or according to our scaling (EB)h .

This value is taken as base or 100% of the normalized reference.

Thereference-vector angle is represented by theeight LSBs of

the input port. The resolution of this representation is 1.406/bitcompared to 2.83; the minimum angle between any two adja-cent voltage vectors of the 18-level inverter, there is no loss of

resolution by this representation.

Fig. 10. Measurements of input and output currents with 80% reference volt-age at 50 Hz and 0.8 PF (power factor) load. (a) Load phase voltage and loadphase current. (b) Load phase voltage and high-voltage-stage dc-supply current.(c) Load phase voltage and medium-voltage-stage dc-supply current. (d) Load

phase voltage and low-voltage-stage dc-supply current.


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A 16-bit port has been allocated for the output. Each arm of

the two- and three-level sub-inverters is driven by 1 bit. External

logic circuit has been used to decode the switching signals and

insert blanking time.

V. EXPERIMENTAL RESULTS

A prototype of the proposed inverter has been constructed.The low- and medium-voltage stages have been supplied by a

lead acid 12 V5.5 Ah batteries. Three series-connected unitsare used for the medium-voltage stage to supply 36 V. The high-

voltage stage has been fed by the laboratory dc-power supply.

For high- and medium-voltage stages, insulated-gate bipolar

transistors (IGBTs) are used, while MOSFETs have been used

for the low-voltage stage. A 1-kW motor has been supplied by

the inverter to act as a load.

Fig. 8 shows the measured phase-voltage waveforms for dif-

ferent values of the reference amplitude. Fig. 9 shows the varia-

tion of the phase-voltage fundamental amplitude and total har-

monic distortion (THD) against the reference amplitude. Theinverter voltage quality is affected at very low reference am-

plitude due to the reduction in the number of steps. However,

with a reference input of 40% or higher, the output voltage THD

is less than 5%. Compared to previous studies that applied the

high-frequency PWM technique, the harmonic distortion has

been considerably reduced. For example, in [12], the five- and

seven-level SVM-controlled inverters have a THD higher than

10% when operated with 0.9 modulation index. This improve-

ment in the voltage quality is mainly due to the high number of

levels.

With 80% amplitude, 50 Hz frequency reference voltage,

and load power factor close to 0.8, various measurements have

been taken and shown in Fig. 10. The load phase voltage and

current are shown in Fig. 10(a). The current is very close to

pure sine wave. The three stages dc currents are also given. The

main dc-source current, shown in Fig. 10(b), confirms that the

high-voltage stage is operating in the square-wave mode and

most of the real load power is supplied by the main dc source.

The currents of the medium and low stages batteries are shown

in Fig. 10(c) and (d), respectively. These currents are highly

reactive. Fig. 10(c) and (d) reveals that the medium and low

stages switching frequency are three and fifteen times that of

the main stage, respectively.

VI. CONCLUSION

A three-stage, 18-level inverter and its innovated control strat-

egy have been presented. The inverter consists of three stages

of two- and three-level inverters. The topology saves the cost

of the dc source. Asymmetrical dc-supplies ratio maximizes the

number of levels.

The suggested strategy exploits the inverters high resolution

to approximate any reference vector by one inverter vectors.

With the integer calculations allowed by the introduced vector

transformation, the control algorithm has been tested using low-

memory fixed-point low-cost processor. This processor runs the

control algorithm with speed that is satisfactory for most appli-

cations.

The experimental results show that the output voltage wave-

form has very small harmonic distortion for wide range of refer-

ence magnitude. The current measurements show that the main

dc-supply current has low ripple, while the medium and low

stages dc currents are highly reactive.

The high-voltage-stage inverter operates in the square-wave

mode. The highest switching frequency associated with low-

voltage stage is considerably lower than that of the PWM-

controlled MLI.

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Saad Mekhilef (M07) received the B.Eng. degreein electrical engineering from the University of Setif,

Setif, Algeria, in 1995, and the M.Eng. Sc. and Ph.D.degrees in electrical engineering from the Universityof Malaya, Kuala Lumpur, Malaysia, in 1998 and2003, respectively.

He is currently an Associate Professor in theDepartment of Electrical Engineering, University ofMalaya. He has been actively involved in industrialconsultancy, for major corporations in thepower elec-tronics projects.He isthe author andcoauthor ofmore

than 100 publications in international journals and proceedings. His researchinterest includes power-conversion techniques, control of power converters, re-newable energy, and energy efficiency.

Mohamad N. Abdul Kadir was born in Mosul,Iraq, in 1967. He received the B.S. and M.S. degreesin electrical engineering from the University of theMosul, Mosul, in 1988 and 1992, respectively. Since2007, he has been working toward the Ph.D. degreefrom the Department of Electrical Engineering, Uni-versity of Malaya, where he has been involved in theresearch in areas of power electronics and electricaldrives.

Since 1992, he has been a Lecturer at several aca-demic institutes in Iraq and Malaysia. His current

research interests include areas of power electronics and electrical drives.

Documents

Voltage Control of Three-Stage Hybrid Multilevel