VLSI+LABREPORT1

C M R

INSTITUTE OF TECHNOLOGY

VLSI LAB REPORT

By

NAME :

REG NO. :

DATE : 04-11-2010

Department of Electronics and Communication CMRIT

C M R

INSTITUTE OF TECHNOLOGY

This is to certify that has satisfactorily completed the course of experiments in practical VLSI LAB prescribed by the Visveswaraiah Technological University B.E Course in the laboratory of this college in the year 2010-2011 .

Signature of the teacher in charge of the batch

Date 04-11-2010

Head of the Department

Name of the Candidate :

Registration No. : 1CR07EC118

Date of Practical Exam : 04-11-2010

INDEX


Sl no. CONTENTS Page no.1. DIGITAL DESIGN

INSTRUCTIONS2. STEPS TO COMPILE AND SIMULATE THE VERILOG 3. STEPS FOR SYNTHESIS

4. PROGRAMS1. Write a Verilog code and Test bench for an inverter, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

5. 2. Write Verilog code and Test bench for a buffer, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

6. 3. Write Verilog code and test bench for a Transmission Gate, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

7. 4. Write Verilog code and test bench for a Basic/Universal gates, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

8. 5a. Write Verilog code and test bench for an SR flip-flop, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

9. 5b. Write Verilog code and test bench for a D flip-flop, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

10. 5c. Write Verilog code and test bench for a JK flip-flop, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

11. 5d. Write Verilog code and test bench for an MS-JK flip-flop, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

12. 5e. Write Verilog code and test bench for a T flip-flop, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

13. 6a. Write Verilog code and test bench for a Serial Adder, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

14. 6b. Write Verilog code and test bench for a Parallel Adder, observe the waveform and synthesise the code with technological


library with given constraints. Do the initial timing verification with gate level simulation?

15. 7a. Write Verilog code and test bench for a Synchronous 4-bit counter, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

16. 7b. Write Verilog code and test bench for a Asynchronous 4-bit counter, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

17. ANALOG DESIGNSTEPS FOR THE ANALOG LAB

18. BUILDING THE TEST DESIGN FOR THE CELL19. STEP TO SIMULATE20. STEPS FOR LAYOUT21. 1.Design an Inverter with given specifications, completing the

design flow mentioned below:a. Draw the schematic and verify the following

i. DC Analysisii. Transient Analysis

b. Draw the Layout and verify the DRC, ERCc. Check for LVSd. Extract RC and back annotate the same and verify the Designe. Verify & Optimise for Time, Power and Area to the given constraint.

22. 2.Design the following circuits with given specifications, completing the design flow mentioned below: a. Draw the schematic and verify the following


b. Draw the Layout and verify the DRC, ERCc. Check for LVSd. Extract RC and back annotate the same and verify the Design

i. A Single Stage differential amplifierii. Common source and Common Drain amplifier

23. 3. Design an op-amp with given specifications, using given differential amplifier Common source and Common Drain amplifier in library and completing the design flow mentioned below: a. Draw the schematic and verify the following


b. Draw the Layout and verify the DRC, ERCc. Check for LVS

d. Extract RC and back annotate the same and verify the Design.DIGITAL DESIGN

ASIC-DIGITAL DESIGN FLOW:


INSTRUCTIONS

Login with the respective login name as provided in the lab Right click on the screen and select Open Terminal to open the command prompt

To enter into csh shell type csh in the command line

To source the cadence tools type source cshrc.main in the command line


Get into the VLSI_LAB directory by typing cd VLSI_LAB in the command line

STEPS TO COMPILE AND SIMULATE THE VERILOG CODES


The verilog code should be written inside the rtl directory and test bench code in the test_bench directory and simulation to be done in the simulation directory.

Enter into the rtl directory to write the verilog code by typing cd rtl in command line

To write the verilog code open the editor by typing vi <filename.extension>Eg: vi inverter.v


To type the code in the vi editor press I, which will get into the insert mode.


After writing the code press esc to exit from the insert modeo To save the file type :wo To exit the editor type :q!o Or to save and exit type :wq


To exit from the current directory type cd ../ in the command line.

Enter into the test_bench directory to write the test bench code by typing cd test_bench in command line


To write the verilog code open the editor by typing vi <filename.extension>Eg: vi inverter_test.v

To type the code in the vi editor press i, which will get into the insert mode.

After writing the code press esc to exit from the insert modeo To save the file type :wo To exit the editor type :q!o Or to save and exit type :wq

To exit from the current directory type cd ../ in the command line.


To simulate the program enter into the simulation directory by typing cd simulation in command line

To verify and run the verilog code in the cadence tool typeirun <path of verilog code> <path of test bench code> -access +rwc –gui eg:

irun ../rtl/inverter.v ../test_bench/inverter_test -access +rwc –gui



Now the tool will verify the codes one by one and open a simulation window if there is no error. Here you can check your respective waveforms.


Now press the play button to get the waveform.


STEPS FOR SYNTHESIS

To synthesize the code, first go to the rclabs directory using the command below: cd rclabs.

Inside rclabs go to work directory. Inside work directory type vi constraints_{name}.g

E.g.: vi constraints_inverter_not.g



Further, type cd work to get inside the work directory.

It is this location where the synthesis is to be carried out Type rc –gui in command prompt which will open a RTL compiler window, and the

command prompt changes to rc command prompt illustrated below:rc:/>


Set the paths for library and hdl files by giving command below:set_attr lib_search_path <location of library>set_attr hdl_search_path <location of verilog code>


eg:set_attr lib_search_path ../libset_attr hdl_search_path ~/VLSI_LAB/rtl


Set the library to slow_highvt.lib by typing the commandset_attr library slow_highvt.lib

In order to perform synthesis we must first read that hdl file using following command:read_hdl {<hdl file>}

eg: read_hdl {ms_d.v dl.v}


To elaborate the design type the command:elaborate


To synthesis the design type the commandsynthesize –to_mapped –effort medium.

To get the required timing and area typerc:/> report timing

rc:/> report area &

for power type

rc:/>report power





PROGRAMS

1. Write a Verilog code and Test bench for an inverter, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

Verilog:

`timescale 1ns/1nsmodule invt(a, y); input a; output y;

y= ~(a);endmodule

TESTBENCH:

`timescale 1ns/1nsmodule invt_tb_v;reg a;wire y; invt uut (.a(a), .y(y));

initial begin

a = 0; #100;

a=1; #100; a=0; #100; a=1; #100; a=0;

end initial$monitor($time,"o/p=%d",y);

endmodule

CONSTRAINTS: set_input_delay -max 1.0 [get_ports "a"]set_output_delay -max 1.0 [get_ports "y"]


LAYOUT:

RESULT:

WAVEFORMS:

REPORT



2. Write Verilog code and Test bench for a buffer, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

Verilog

`timescale 1ns/1nsmodule buffer(in,out);input in;output out;wire q1;inverter inst0(in,q1);inverter inst1(q1,out);endmodule

Testbench:

`timescale 1ns/1nsmodule buffer_tb;reg in;wire out;buffer uut(.in(in),.out(out));task display;begin$display("time=%d",$time,"input=",in,"output=",out);endendtask;initialbegin#100;in=0;display;#100;in=1;display;endendmodule

CONSTRAINTS:

set_input_delay -max 1.0 [get_ports "in"]set_output_delay -max 1.0 [get_ports "out"]


LAYOUT:

RESULT:

WAVEFORMS:

REPORT :



3. Write Verilog code and test bench for a Transmission Gate, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

Verilog:

`timescale 1ns/1nsmodule trans (o,i,cntrl1,cntrl2);input i,cntrl1,cntrl2;output o;reg o;always@(i or cntrl1 or cntrl2)beginif(cntrl1==cntrl2) o=i;else if(cntrl1==0 & cntrl2==1) o=i;else if(cntrl1==1 & cntrl2==0) o=1'bz;end endmodule

Testbench:

`timescale 1ns/1nsmodule trans_tb;wire o;reg i,cntrl1,cntrl2;trans t1(o,i,cntrl1,cntrl2);task display;begin$display("time=%d",$time,"ns","input=",i,"output=",o,"control1=",cntrl1,"control2=",cntrl2);endendtaskinitialbegini=1'b0;cntrl1=1'b0;cntrl2=1'b1;#10;display;i=1'b0;cntrl1=1'b1;cntrl2=1'b0;#10;display;i=1'b1;cntrl1=1'b0;cntrl2=1'b1;#10;display;i=1'b1;cntrl1=1'b1;cntrl2=1'b0;#10;display;i=1'b1;cntrl1=1'b1;cntrl2=1'b1;#10;display;i=1'b1;cntrl1=1'b0;cntrl2=1'b0;#10;display;i=1'b0;cntrl1=1'b1;cntrl2=1'b1;#10;display;i=1'b0;cntrl1=1'b0;cntrl2=1'b0;#10;display;end endmodule


CONSTRAINTS:

set_input_delay -max 1.0 [get_ports "i"]set_input_delay -max 1.0 [get_ports "cntrl1"]set_input_delay -max 1.0 [get_ports "cntrl2"]set_output_delay -max 1.0 [get_ports "o"]

LAYOUT:

RESULT:

WAVEFORMS:


REPORT:


4. Write Verilog code and test bench for a Basic/Universal gates, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

Verilog:

`timescale 1ns/1nsmodule allgates(a,b,and1,or2,xor3,nand4,nor5,xnor6,not7);input a,b;output and1,or2,xor3,nand4,nor5,xnor6,not7;reg and1,or2,xor3,nand4,nor5,xnor6,not7;always@(a or b )beginand1=a&b;or2=a|b;xor3=a^b;nand4=~(a&b);nor5=~(a|b);xnor6=~(a^b);not7=~(a);end endmodule

Testbench:

`timescale 1ns/1nsmodule allgates_tb;reg a,b;wire and1,or2,xor3,nand4,nor5,xnor6,not7;allgates uut(a,b, and1,or2,xor3,nand4,nor5,xnor6,not7);task display;begin$display("time=%d",$time,"input=",a,b,"output=",and1,or2,xor3,nand4,nor5,xnor6,not7);end endtaskinitialbegina=0;b=0;#30;display;a=0;b=1;#30;display;a=1;b=0;#30;display;a=1;b=1;#30;display;end endmodule


CONSTRAINTS:

set_input_delay -max 1.0 [get_ports "a"]set_input_delay -max 1.0 [get_ports "b"]set_output_delay -max 1.0 [get_ports "and1"]set_output_delay -max 1.0 [get_ports "or2"]set_output_delay -max 1.0 [get_ports "xor3"]set_output_delay -max 1.0 [get_ports "nand4"]set_output_delay -max 1.0 [get_ports "nor5"]set_output_delay -max 1.0 [get_ports "xnor6"]set_output_delay -max 1.0 [get_ports "not7"]

LAYOUT:

RESULT:

WAVEFORMS:


REPORT:


5a. Write Verilog code and test bench for an SR flip-flop, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

Verilog:

`timescale 1ns/1nsmodule srff(clk,s,r,q,qbar);input clk;input s,r;output q,qbar;reg q,qbar;always@(posedge clk)beginif(s==1'b0 && r==1'b0)beginq<=q;qbar<=qbar;endelse if(s==1'b0 && r==1'b1)beginq<=1'b0;qbar<=1'b1;endelse if(s==1'b1 && r==1'b0)beginq<=1'b1;qbar<=1'b0;endelse beginq<=1'bx;qbar<=1'bx;endend endmodule

Testbench:

`timescale 1ns/1nsmodule srff1_tb;reg clk,s,r;wire q,qbar;wire s1,r1,clk1;srff uut(clk,s,r,q,qbar);

assign s1=s;assign r1=r;assign clk1=clk;


initialclk=1'b0;always#10clk=~clk;initialbegins=1'b0;r=1'b0;#30 s=1'b1;#29 s=1'b0;#1 r=1'b1;#30 s=1'b1;#30 r=1'b0;#20 s=1'b0;#19 s=1'b1;#200 s=1'b1;r=1'b1;#50 s=1'b0;r=1'b0;#50 s=1'b1;r=1'b0;end always#5 $display($time,"clk=%b s=%b r=%b",clk,s,r);initial#500 $finish;specify$setup(s1,posedge clk1,2);$setup(r1,posedge clk1,2);$hold(posedge clk1,s1,2);$hold(posedge clk1,r1,2);endspecifyendmodule

CONSTRAINTS:create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]set_clock_transition -rise 0.1 [get_clocks "clk"]set_clock_transition -fall 0.1 [get_clocks "clk"]set_input_delay -max 1.0 [get_ports "s"] -clock [get_clocks "clk"]set_input_delay -max 1.0 [get_ports "r"] -clock [get_clocks "clk"]set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"]set_output_delay -max 1.0 [get_ports "qbar"] -clock [get_clocks "clk"]


LAYOUT:

RESULT:

WAVEFORMS:


REPORT:



5b. Write Verilog code and test bench for a D flip-flop, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

Verilog:

`timescale 1ns/1nsmodule dff(q,clk,rst,din);input clk,din,rst;output q;reg q;always@(posedge clk)beginif(rst)q<=1'b0;elseq<=din;end endmodule

Testbench:

`timescale 1ns/1nsmodule dff1_tb;reg clk,din,rst;wire q,d1,clk1;dff1 d3(q,clk,rst,din);assign d1=din;assign clk1=clk;initialclk=1'b0;always#10 clk=~clk;initialbegindin=1'b0;rst=1'b1;#20 rst=1'b0;#10 din=1'b1;#20 rst=1'b1;#18 din=1'b0;#20 rst=1'b0;#1 din=1'b1;#20 din=1'b0;endalways#5 $display($time,"clk=%d din=%d q=%d",clk,din,q);


initial#1000 $finish;specify$setup(d1,posedge clk1,2);$hold(posedge clk1,d1,2);$width(negedge d1,2);endspecifyendmodule

CONSTRAINTS:

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]set_clock_transition -rise 0.1 [get_clocks "clk"]set_clock_transition -fall 0.1 [get_clocks "clk"]set_input_delay -max 1.0 [get_ports "din"] -clock [get_clocks "clk"]set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"]set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"]

LAYOUT:


RESULT:

WAVEFORMS:

REPORT:



5c. Write Verilog code and test bench for a JK flip-flop, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

Verilog:

`timescale 1ns/1nsmodule jkff(clk,reset,j,k,q,qbar);output q,qbar;input clk,j,k,reset;reg q,qbar;always@(posedge clk or posedge reset)beginif(reset)beginq<=1'b0;qbar<=1'b0;endelse if(j==0 && k==0)beginq<=q;qbar<=qbar;endelse if(j==1'b0 && k==1'b1)beginq<=1'b0;qbar<=1'b1;endelse if(j==1'b0 && k==1'b1)beginq<=1'b1;qbar<=1'b0;endelsebeginq<=~q;qbar<=~qbar;endendendmodule

Testbench:

`timescale 1ns/1nsmodule jkff_tb;reg clk,j,k,rst;wire q,qbar;wire clk1,j1,k1;


jkff uut(j,k,clk,q,qbar,rst);assign clk1=clk;assign j1=j;assign k1=k;initialclk=1'b0;always #10 clk=~clk;initialbeginj=1'b0;k=1'b0;rst=1'b0;#29 j=1'b1;k=1'b0;#1 j=1'b0;k=1'b1;#29 j=1'b1;k=1'b1;#40 j=1'b1;k=1'b0;#5 j=1'b0;#20 j=1'b1;#50 rst=1'b0;#10;end always#5 $display($time ,"clk=%b j=%b k=%b",clk,j,k);initial#300 $finish;specify$setup(j1,posedge clk1,2);$setup(k1,posedge clk1,2);$hold(posedge clk1,j1,2);$hold(posedge clk1,k1,2);endspecifyendmodule

CONSTRAINTS:

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]set_clock_transition -rise 0.1 [get_clocks "clk"]set_clock_transition -fall 0.1 [get_clocks "clk"]set_input_delay -max 1.0 [get_ports "j"] -clock [get_clocks "clk"]set_input_delay -max 1.0 [get_ports "k"] -clock [get_clocks "clk"]set_input_delay -max 1.0 [get_ports "reset"] -clock [get_clocks "clk"]set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"]set_output_delay -max 1.0 [get_ports "qbar"] -clock [get_clocks "clk"]


LAYOUT:

RESULT:

WAVEFORMS:


REPORT :


5d. Write Verilog code and test bench for an MS-JK flip-flop, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

Verilog:

`timescale 1ns/1nsmodule msjkff(clk,reset,j,k,q,qbar);output q,qbar;input clk,j,k,reset;wire q1,qbar1;jkff inst0(clk,reset,j,k,q1,qbar1);jkff inst1(!clk,reset,q1,qbar1,q,qbar);endmodule

Testbench:

`timescale 1ns/1nsmodule msjkff_tb;reg clk,j,k;wire q,qbar;wire clk2,j2,k2;msjkff inst(q,qbar,clk,j,k);assign clk2=clk;assign j2=j;assign k2=k;initialclk=1'b0;always #10clk=~clk;initialbeginj=1'b0;k=1'b0;#60 j=1'b0;k=1'b1;#40 j=1'b1;k=1'b0;#20 j=1'b1;k=1'b1;#40 j=1'b1;k=1'b0;#60 j=1'b0;#20 j=1'b1;#10;endalways#5 $display($time,"clk=%b j=%b k=%b",clk,j,k);initial#200 $finish;specify$setup(j2,posedge clk2,2);$setup(k2,posedge clk2,2);$hold(posedge clk2,j2,2);$hold(posedge clk2,k2,2);


endspecifyendmodule

CONSTRAINTS:

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]set_clock_transition -rise 0.1 [get_clocks "clk"]set_clock_transition -fall 0.1 [get_clocks "clk"]set_input_delay -max 1.0 [get_ports "j"] -clock [get_clocks "clk"]set_input_delay -max 1.0 [get_ports "k"] -clock [get_clocks "clk"]set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"]set_output_delay -max 1.0 [get_ports "qbar"] -clock [get_clocks "clk"]

LAYOUT:

RESULT:

WAVEFORMS:


REPORT :


5e. Write Verilog code and test bench for a T flip-flop, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

Verilog:

`timescale 1ns/1nsmodule tff(clk,t,rst,q,qb);input clk,t,rst;output q,qb;reg tq;always@(posedge clk or negedge rst)beginif(!rst)tq<=1'b0;elsebeginif(t)tq<=~tq;end endassign q=tq;assign qb=~q;endmodule

Testbench:

`timescale 1ns/1nsmodule tff_tb;reg clk,t,rst;wire q,qb;tff uut(clk,t,rst,q,qb);initialclk=1'b0;always#10 clk=~clk;initialbeginrst=1'b1;#30 rst=1'b0;t=1'b0;#10 t=1'b1;#10 t=1'b0;#10 t=1'b1;#10 t=1'b0;#10 rst=1'b1;

#10;endinitial


#200 $finish;endmodule

CONSTRAINTS:

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]set_clock_transition -rise 0.1 [get_clocks "clk"]set_clock_transition -fall 0.1 [get_clocks "clk"]set_input_delay -max 1.0 [get_ports "t"] -clock [get_clocks "clk"]set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"]set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"]set_output_delay -max 1.0 [get_ports "qb"] -clock [get_clocks "clk"]

LAYOUT:

RESULT:

WAVEFORMS:


REPORT :


6a. Write Verilog code and test bench for a Serial Adder, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

Veilog:

`timescale 1ns/1nsmodule serial_adder(a,b,reset,clock,sum);input[7:0]a,b;input reset,clock;output[7:0]sum;reg[3:0]count;reg s,y,Y;wire[7:0] qa,qb,sum;wire run;parameter G=0,H=1;shiftrne shift_a(a,reset,1'b1,1'b0,clock,qa);shiftrne shift_b(b,reset,1'b1,1'b0,clock,qb);shiftrne shift_sum(8'b0,reset,run,s,clock,sum);always@(qa or qb or y)case(y)G:begins=qa[0]^qb[0];if(qa[0]&qb[0])Y=H;elseY=G;endH:begins=qa[0]~^qb[0];if(~qa[0]&~qb[0])Y=G;elseY=H;enddefault:Y=G;endcasealways@(posedge clock)if(reset)Y<=G;elsey<=Y;always@(posedge clock)if(reset)count=8;else if(run)count=count-1;assign run=1 count;endmodule


Shift registermodule shiftrne ( R,L,E,w,clock,q);parameter n=8;

input [n-1:0] R;input L,E,w,clock;output [n-1:0] q;reg [n-1:0] q;integer k;

always @(posedge clock) if (L) q <= R; else if (E) begin for (k=n-1;k>0;k=k-1) q[k-1] <= q[k]; q[n-1] <= w; endendmodule

Testbench:module serial_adder_t ;reg [7:0] A,B;reg reset,clock;wire [7:0] sum ;

initial clock = 1'b0;always #5 clock =~clock;serial_adder s1 (A,B,reset,clock,sum);initial

begin reset = 1'b0;

A = 8'b10101010; B = 8'b11111111;

#20 reset = 1'b1;#20 reset = 1'b0;#150 reset = 1'b1; A = 8'b11110000 ; B = 8'b11110011;

#20 reset = 1'b0;#200 $finish;

endinitial

$monitor ($time, " SUM = %d ", sum);endmodule


CONSTRAINTS:create_clock -name clk -period 10 -waveform {0 5} [get_ports "clock"]set_clock_transition -rise 0.1 [get_clocks "clock"]set_clock_transition -fall 0.1 [get_clocks "clock"]set_clock_uncertainty 1.0 [get_ports "clock"]set_input_delay -max 1.0 [get_ports "A"] -clock [get_clocks "clock"]set_input_delay -max 1.0 [get_ports "B"] -clock [get_clocks "clock"]set_input_delay -max 1.0 [get_ports "reset"] -clock [get_clocks "clock"]set_output_delay -max 1.0 [get_ports "sum"] -clock [get_clocks "clock"]

RESULT:

WAVEFORMS:

REPORT POWER:Cells Leakage Power(nW) Dynamic

power(nW)Total power(nW)

58 451.071 43895.957 44347.028

REPORT AREA:

Cells Cell Area Net Area Wire load58 576 0 None


6b. Write Verilog code and test bench for a Parallel Adder, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

Verilog:

`timescale 1ns/1nsmodule para(carryin,x,y,sum,carryout);input carryin;input [3:0]x,y;output [3:0]sum;output carryout;fulladd stage0(carryin,x[0],y[0],sum[0],c1);fulladd stage1(c1,x[1],y[1],sum[1],c2);fulladd stage2(c2,x[2],y[2],sum[2],c3);fulladd stage3(c3,x[3],y[3],sum[3],carryout);endmodulemodule fulladd(cin,x,y,s,cout);input cin,x,y;output s,cout;assign s=x^y^cin;assign cout=(x&y)|(x&cin|(y&cin));endmodule

Testbench:

`timescale 1ns/1nsmodule para_tb;reg [3:0]x,y;reg carryin;wire [3:0]sum;wire carryout;para a1(carryin,x,y,sum,carryout);initialbegin$monitor($time,"sum=%d",sum);x=4'b0000;y=4'b0000;carryin=1'b0;#20 x=4'b1111;y=4'b1010;#50 x=4'b0111;y=4'b1111;#60 $finish;endendmodule


CONSTRAINTS:

set_input_delay -max 1.0 [get_ports "carryin"]set_input_delay -max 1.0 [get_ports "x"]set_input_delay -max 1.0 [get_ports "y"]set_output_delay -max 1.0 [get_ports "sum"]set_output_delay -max 1.0 [get_ports "carryout"]

LAYOUT:

RESULT:

WAVEFORMS:


REPORT :



7a. Write Verilog code and test bench for a Synchronous 4-bit counter, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

Verilog:

`timescale 1ns/1nsmodule binsync(clk,reset,count);input clk,reset;output [3:0]count;reg [3:0]count;always@(posedge reset or posedge clk)beginif(reset)count<=4'b0000;else if (clk)count<=count+1;end endmodule

Testbench:

`timescale 1ns/1nsmodule binsync_tb;reg clk;reg reset;wire [3:0]count;initialclk=1'b0;always #5 clk=~clk;binsync uut(.clk(clk),.reset(reset),.count(count));initialbeginreset=1'b0;#15 reset=1'b1;#30 reset=1'b0;#300 $finish;end initial$display($time,"count=%d",count);endmodule


CONSTRAINTS:

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]set_clock_transition -rise 0.1 [get_clocks "clk"]set_clock_transition -fall 0.1 [get_clocks "clk"]set_input_delay -max 1.0 [get_ports "reset"] -clock [get_clocks "clk"]set_output_delay -max 1.0 [get_ports "count"] -clock [get_clocks "clk"]

LAYOUT:

RESULT:

WAVEFORMS:


REPORT:


7b. Write Verilog code and test bench for a Asynchronous 4-bit counter, observe the waveform and synthesise the code with technological library with given constraints. Do the initial timing verification with gate level simulation?

Verilog:

`timescale 1ns/1nsmodule async(clk,reset,count);input clk,reset;output[3:0]count;reg c0,c1,c2,c3;always@(posedge clk or posedge reset)beginif(reset)c0<=1'b0;else c0<=~c0;endalways@(negedge c0 or posedge reset)beginif(reset)c1<=1'b0;elsec1<=~c1;endalways@(negedge c1 or posedge reset)beginif(reset)c2<=1'b0;elsec2<=~c2;endalways@(negedge c2 or posedge reset)beginif(reset)c3<=1'b0;elsec3<=~c3;endassign count[0]=c0;assign count[1]=c1;assign count[2]=c2;assign count[3]=c3;endmodule


Testbench:

`timescale 1ns/1nsmodule async_tb;reg clk,reset;wire[3:0]count;async r1(clk,reset,count);initialclk=1'b0;always #10 clk=~clk;initialbeginreset=1'b0;#10 reset=1'b1;#10 reset=1'b0;#190 reset=1'b1;#20 reset=1'b0;#100 reset=1'b1;#40 reset=1'b0;#10 reset=1'b1;#10 reset=1'b0;#290 reset=1'b1;#20 reset=1'b0;#100 reset=1'b1;#40 reset=1'b0;#250$finish;endinitial$monitor($time,"op=%d",count);endmodule

CONSTRAINTS:

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]set_clock_transition -rise 0.1 [get_clocks "clk"]set_clock_transition -fall 0.1 [get_clocks "clk"]set_input_delay -max 1.0 [get_ports "reset"] -clock [get_clocks "clk"]set_output_delay -max 1.0 [get_ports "count"] -clock [get_clocks "clk"]


LAYOUT:

RESULT:

WAVEFORMS:

REPORT:



ANALOG DESIGN

ANALOG DESIGN FLOW:

STEPS FOR THE ANALOG LAB

Creating The Library

Go to cd VLSI_LAB/cadence_analog_lab. Go to csh mode. Source the tool source ~/cshrc.main. Type `virtuoso &’ and press enter, it will open a virtuoso tool.

Go to the tool tab and select Library manager.


Create a new library by going to the link File → New → Library. Give the library name as CMRIT, and click ok. Select attach to an existing technology library and click ok.

Select gpdk180 and click ok


SCHEMATIC AND SYMBOL CREATION

In the library manager select cmrit library In Library manager select File → New → Cell view. Give the cell name as inverter.

Virtuoso Schematic Editor will open. Select create → instance, and select the required components (pmos & nmos symbols)

Select create → pins, and place the ports (vin, vdd, gnd, vout) on the editor.


Make the complete connection by using wires by selecting create → wire (narrow). After complete of the schematic, save the file by file → check & save .


To create symbol Create → Cell view → From cell view. Virtuoso symbol editor opens. Create shape of the cell using option in Create → Shapes. Make a boundary by Create → Selection box. And click automatic.


BUILDING THE TEST DESIGN FOR THE CELL

In the library manager select cmrit library In Library manager select File → New → Cell view. Give the cell name as inverter_test.

Virtuoso Schematic Editor will open. Select create → instance, and select the design to test (inverter from cmrit library). To apply inputs, create → instance. In the library select analogLib and select

appropriate inputs (vpulse, vdc, gnd). For vpulse V1 = 0v, V2 = 1.8v, period = 20n, pulse width = 10n, rise time = fall time =

1n. For vdc, dc voltage = 1.8v Put an output pin. Connect the circuit completely using wires, and check & save


STEP TO SIMULATE

In the Virtuoso Schematic Editor after completing the test circuit design, launch → ADE L.

Virtuoso Analog Design Environment window opens.


Goto Analyses → choose, select tran for transient analysis ( stop time = 200n, accuracy default → moderate) and apply, now select dc for DC analysis ( select → save dc operating point, component parameter and double click select component and select input source ‘vpulse’ in schematic editor, and dc, sweep range is 0 to 1.8v).



Goto outputs → to be plotted → select on schematic( input and output wires). Goto simulation → netlist and run.


STEPS FOR LAYOUT

1. Open the Library Manager in Virtuoso, select CMRIT and double click inverter, then goto File New Cellview.

2. In the Schematic Editor Window, Go to Launch Layout XL.3. In the Layout Window Go to Connectivity Generate All from source.4. Select the PR boundary and delete it.5. In the layout window Press CNTRL A to select all components.6. After that go to Connectivity Nets show/hide Incomplete.nets.7. In the layout window press shift F to view the layers for the transistor.8. Move each component to the I quadrant and place Vdd, Vss, Vin, Vout in the

appropriate position. 9. To draw the rectangle of layers for ex:- Metal1, Choose Metal1 dra in LSW(Layout

Selection Window) & press R or (create shape rectangle) & give the connections to Vdd, Vout, Vss.

10. To connect the input Vin to Gate(Polysilicon) place M1 (Poly1) contact from create via M1-poly1.

11. Place the substrate contacts Vdd & Vss i.e, M1 - n-well for Vdd & M1 - P-sub for Vss.

12. Draw the n-well layer to cover the Vdd & pmos transistor.13. Check and save the layout.


14. In the same window goto ASSURA run DRC.Check for the errors15. Goto ASSURA run LVS click OK. Check for the layout vs schematic16. In LVS debug Window, check for errors in summary and rectify if required.17. After layout and schematic matches, go to ASSURA Run RCX click ok.18. Av_extracted (in view) is created in your library.19. Open then av_extracted view and press shift F & verify the resistance and

capacitance value.

INVERTER


1.Design an Inverter with given specifications, completing the design flow mentioned below:

a. Draw the schematic and verify the followingiii. DC Analysisiv. Transient Analysis

b. Draw the Layout and verify the DRC, ERCc. Check for LVSd. Extract RC and back annotate the same and verify the Designe. Verify & Optimise for Time, Power and Area to the given constraint.

SPECIFICATIONS:

Library Name Cell Name PropertiesGpdk180 Pmos Model name=pmos1; w=2u; l=180nGpdk180 Nmos Model name=nmos1; w=2u; l=180n

Pin Name DirectionVin InputVout OutputVdd, Vss Input

Library Name Cell Name PropertiesCMRIT Inverter SymbolAnaloglib Vpulse Define pulse specification as

V1 =0v V2 = 1.8v period = 20n PW = 10n Rise time = fall time = 1n

Analoglib Vdd, Vss Vdd(Vdc)=2.5v, Vss=gnd

SCHEMATIC:


TEST SCHEMATIC:

LAYOUT:


WAVEFORM:


ANALYSIS

Transient analysis : stop time = 200n Choose moderate

DC analysis : ON – save DC operating point Component parameter select Vsin Start = 0 Stop = 1.8v


2.Design the following circuits with given specifications, completing the design flow mentioned below:

a. Draw the schematic and verify the followingiii. DC Analysisiv. Transient Analysis

b. Draw the Layout and verify the DRC, ERCc. Check for LVSd. Extract RC and back annotate the same and verify the Design

iii. A Single Stage differential amplifieriv. Common source and Common Drain amplifier

I. DIFFERENTIAL AMPLIFIER

SPECIFICATIONS:

Library Name Cell Name PropertiesGpdk180 Pmos Model name=pmo,pm1; w=15u; l=1uGpdk180 Nmos Model name=nmo,nm1; w=3u; l=1u

Model name=nm2,nm3; w=4.5u; l=1u

Pin Name DirectionIdc, V1,V2 InputVout OutputVdd, Vss Input

Library Name Cell Name PropertiesCMRIT Diff_amplifier SymbolAnaloglib Vsin Define pulse specification as

AC magnitude = 1; Amplitude = 5m; Frequency = 1k

Analoglib Vdd, Vss Vdd(Vdc)=2.5v, Vss=(Vdc)=-2.5

Analoglib Idc DC current = 30u


SCHEMATIC:

TEST SCHEMATIC:


LAYOUT:WAVEFORM:

ANALYSIS

Transient analysis : stop time = 5m Choose moderate

DC analysis : ON – save DC operating point Component parameter select Vsin Start = -5 Stop = 5

AC analysis : ON – frequency Start = 150 Stop = 100M Step size = logarithmic Points per decade = 20


II. COMMON SOURCE AMPLIFIER


SPECIFICATIONS:

Library Name Cell Name PropertiesGpdk180 Pmos Model name=pmos1; w=50u; l=1uGpdk180 Nmos Model name=nmos1; w=10u; l=1u

Pin Name DirectionVin, Vbias InputVout OutputVdd, Vss Input

Library Name Cell Name PropertiesCMRIT cs_amplifier SymbolAnaloglib Vsin Define pulse specification as

AC magnitude = 1; DC voltage=0; Amplitude = 5m; Frequency = 1k

Analoglib Vdd, Vss,Vbias Vbias = Vdd(Vdc)=2.5v, Vss=(Vdc)=-2.5

SCHEMATIC:

TEST SCHEMATIC:


LAYOUT:

WAVEFORM:


ANALYSIS





III. COMMON DRAIN AMPIFIER

SPECIFICATIONS:

Library Name Cell Name PropertiesGpdk180 Pmos Model name=pmo,pm1; w=50u; l=1uGpdk180 Nmos Model name=nmo,nm1; w=10u; l=1u

Pin Name DirectionIdc, V1,V2 InputVout OutputVdd, Vss Input

Library Name Cell Name PropertiesCMRIT cd_amplifier SymbolAnaloglib Vsin Define pulse specification as

AC magnitude = 1; DC voltage=0; Amplitude = 5m; Frequency = 1k

Analoglib Vdd, Vss, Vbias Vbias =Vdd(Vdc)=2.5v, Vss=(Vdc)=-2.5

SCHEMATIC:


TEST SCHEMATIC:


LAYOUT:

WAVEFORM:

ANALYSIS





3. Design an op-amp with given specifications, using given differential amplifier Common source and Common Drain amplifier in library and completing the design flow mentioned below:

a. Draw the schematic and verify the followingiii. DC Analysis


iv. Transient Analysisb. Draw the Layout and verify the DRC, ERCc. Check for LVSd. Extract RC and back annotate the same and verify the Design.

SPECIFICATIONS:

Library Name Cell Name PropertiesGpdk180 Diff_amplifier SymbolGpdk180 Cs_amplifier Symbol

Pin Name DirectionIdc, Vin,Vnoninv InputVout OutputVdd, Vss Input

Library Name Cell Name PropertiesCMRIT op_amplifier SymbolAnaloglib Vsin Define pulse specification as

AC magnitude = 1; Amplitude = 5u; Frequency = 1k

Analoglib Vdd, Vss Vdd(Vdc)=2.5v, Vss=(-Vdc)=-2.5

Analoglib Idc DC current = 30u

SCHEMATIC:


TEST SCHEMATIC:

WAVEFORM:

ANALYSIS






Documents

VLSI+LABREPORT1