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Levels of Abstraction1 System level

Processors, Memories, Peripherals Word files, Records, Programs HDL natural language

1 RTL level Registers, ALU, CCUs Bytes, words, double words

Block diagrams, state diagrams1 Lo ic level

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Gates, flip-flops 1,0, X: strong, weak, Z Logic diagrams, boolean equations

1 Circuit level R, C, L, Diodes, Transistors Voltage, current, temperature Schematic diagrams, circuit equations

1 Layout level NPN, PNP transitors, CMOS Values: voltage, current, temperature, fields

Device modes, incterconnects

VLSI Developments12345

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Synthesis

logiccell

VDD

input

1 Synthesis is the stage in design flow which is concerned with translatingVHDL code into gates - and that's putting it very simply

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Algorithm LevelSynthesis

RTL LevelSynthesis

Circuit LevelSynthesis

Anexampleofstandardcelllayout.

VSS

wiring

Physical LevelSynthesis

System Functions often split b/w CPU & ASIC1 Most economical means of implementing logic functions is to use uP1 When uP is too slow or too busy to handle some fast I/O, an ASIC can

be used to implement high-speed concurrent operations

uPSlow inputsSlow outputs

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ASIC

Slow inputs

Fast inputsFast outputs

Control &Feedback

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System-on-Chip (SoC) Appraoch1 SoC is the design approach of integrating the components of an

electronic system into a single chip

1 A single chip can perform the functions of an entire electronic system,such as MPEG decoder, network router, or cellular phone

1 SoC designs often consume less power, less design/package cost &more reliable than multichip systems that they are designed to replace

1 The key to SoC approach is integration. By integrating increasinglymore preassembled and verified blocks, which have dedicatedfunctions, into one chip, a sophisticated system is created in a timelyand economical fashion

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Why SoC?1 System on Chip (SoC) bridges the gap between Hardware & Software &

their implementation

1 In SoC design, chips are assembled at IP block level (design reusable)& IP interfaces rather than gate level

SoC Consists of

1 Current systems are complex & heterogeneouscontains different types of components

1 Half of Chip can be filled with :

1 Low-power processors1 Interconnected by field-programmable buses

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1 Analog

1RF

1 Power

1MEMs

1 IP

1 Digital

Control

P

DSP

Interfaces

1Memory

SRAM

DRAM

FLASH

i

1 Embedded in 20Mbytes of distributed DRAM &flash memory

1 Another Half: ASIC

1 Application Specific Integrated Circuit (ASIC)1 Computational power will not result from multi-GHz

clocking but from parallelism, with below 200 MHz

This will simplify the design for correcttiming, testability, & signal integrity

SoC Flow

GenericHW IP blocks

GenericSW IP blocks

SpecifySoC

Architectureplatform

PartitionHW/SW

ApplicationSpecific

Electronic system level design

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Operatingsystem

ApplicationSpecificHW IPs

IntegrateApplication

Specific IP blockinto Arch. platform

i iSW IP ModulesIntegrate SW

Specific IP Modules

Functionalsimulation

Low levelSW simulationHW design

flow

SW designflow

HW & SW (low level)FPGA platform

HW/SWCo-simulation

SoC Flow

HW & SW (low level)FPGA platform

Physicaldesign

ApplicationSW development

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PrototypeIC fabrication

HW/SW Verification onapplication prototypeor development board SW test

PrototypeIC fabrication

Ship ICs & SW to Clients

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SoC Design Flow

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SoC Example

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SoC Examples

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Intellectual Property (IP) Core

CriteriaClassification

Hard Core Soft Core

Structure Pre-defined organizationBehavioural source code,technology independent

1 In electronic design, intellectual property core (IP) core, or IP block isreusable unit of logic, cell, or chip layout design that is IP of one party

1 IP cores may be licensed to another party or can be owned & used bya single party alone

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l i

Modelling Modeled as a library componentSynthesizable with severaltechnologies

Flexibility Cannot be modified by designer Can be modified by the designer

Timing closure Timing ensured Timing not guaranteed

IP protectionStrong. Usually corresponds to alayout

Weak. Source code

ExampleFPGA Bitstream, GDSII file for IClayout

VHDL, Verilog

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Need for redesign1 Many of electronic products have life more than 10- years, and

consequently have to be redesigned several times in order to exploitnew technology

1 It is common for electronics to modified and new functions to be added

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Increasing device & complexity/DSM

1 Exponential increase in device complexity

Increasing with Moore's law (or faster)!

1 More complex system contexts

System contexts in which devices are deployed (e.g.cellular radio) are increasing in complexity

1 Require exponential increases in design productivity

Complexity

Increasing device

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Design of each transistor is getting more difficult!

Deep submicron effects1 Smaller geometries are causing a wide variety of

effects that we have largely ignored in the past:

Cross-coupled capacitances

Signal integrity

Resistance

Inductance

DSMEffects

Heterogeneity on chip/Market Pressure

1 Greater diversity of on-chip elements

Processors

Software

Memory

Analog

More transistors doin different thin s!

Heterogeneity

Diversity

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Stronger market pressure

1 Decreasing design window

1 Less tolerance for design revisions

Time-to-market

Exponentially more complex, greater design risk,greater variety, and a smaller design window!

A Quadruple-whammy

Com

plexity

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Time-to-marketDSMEffects

Heterogeneity

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Real Time Embedded Systems1 Electronic system containing CPU without an operating system visible

to end-user

1 It interacts with peripheral devices within fixed time constraints

1 Minimum of resources are employed to perform required tasks

1 In addition to functionality and cost, other constraints include powermanagement, fault tolerance, quality of services, security etc.

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CAD/EDA Tools1 Computer Aided Design (CAD)/Electronic Design Automation (EDA)

1 Circuit Analysis Tools

Predict circuit behavior at all process corners from high to low level

1 Symbolic Layout Tools

To ease task of physical design; mask verification to ensure

manufacturability

Tools to do tedious, repetitive work such as routing, tiling a mosaic ofbuilding-block cells, or verifying that layout and schematic match

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1 Problems:

Designing highly complex VLSI circuits (100K to xM FETs)

Classical, iterative procedures are unsuitable

Precise transistor models are necessary for reliable predictions1datainflation

1 Solutions:

New design methodologies

Powerful design tools

High level design languages

Silicon compiler would be useful

Evolution of EDA industry

Results(design productivity)

Synthesis Cadence, Synopsys

Whats next?

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Effort

(EDA tooleffort)

McKinsey S-Curve

Transistor entry Calma, Computervision, Magic

Schematic entry Daisy, Mentor, Valid

Why Low Power ?

1 Lifetime of a Device

Handhelds

1 Reduce Cost

Cooling

Packaging

1 High density on Chip-Portablesystems Smaller Batteries

Reduce Weight

Exploding Market of Portable Devices,SoC faces sever problem of Power Restrictions

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Servers

qu tousComputing

Desktops

Portables

i Reduce Volume

1 Reliability Thermal problems Scaling problems Electro-migration

1 Environmental Concerns Office equipment accounted for

5% of total US commercial

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Why Low Power?

1 Portable systems

Long battery life

Light weight

Small form factor

1 IC priority list Power dissi ation

1 Technology direction reduced voltage/power designs based on highperformance IC technology, high integration to minimize size, cost,power, speed

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i i i

Cost

Performance

1 Expected battery lifetime increase over next 10 years: 30-40%1 IC densities/Operating frequency will be double every generation

Why Low Power?

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80% Ptotal

Sources of Power Dissipation

1234 6 789AA9BCDE2FF2E

VDD

In Out

CMOS

1 7 1C

Short circuit path between

1 A34 C4 1C

Charging & Dischargingcapacitors

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10-20% Ptotal

1-10% Ptotal

Source: Design Aids for Low Power, Jan M. Rabaey

1B 6 9AAB

1B6 9AA

1 8 1C

Leaking diodes &transistors

CL

ISC

12345645

suppy ra s urngswitching

Principles of Low Power Design

1 Reduce supply voltage

Quadratic effect dramaticsavings

Negative effect on performance

1 Reduce capacitance

Smaller devices, newl i

1 Design Space Exploration Calculate bound under different constraints Trade-off between Power, Area, Speed

2

Speed

Power

Quality

Noise

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l i

Usually not design(er) parameter

1 Reduce switching frequency

Switching activity

Clock rate

1 Reduce glitches

1 Reduce short circuit currents

1 Reduce leakage currents

Clocks

I/O Drivers

Caches

ExecutionUnits

Control

40%20%

15%

15%10%

mProcessor

Source: Dr. Li-Rong Zheng (KTH)

2CVP = VIP =

Area

Yield

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Power Down Techniques

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Future of VLSI

Emergence of GSI (Giga-Scale Integration)

and TSI (Tera-Scale Intgration)

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-

ULSI (Ultra Large Scale Integration) & WaferScale Integration and more developed versions

of SoC (System on Chip)