INTRODUCTION TO VLSI DESIGN

Prepared By : SOMRITA GHOSH

VLSI Technology Very Large Scale Integration – A technology that

allows the construction and interconnection of large numbers (millions) of transistors on a single integrated circuit(IC).

Integration improves the designLower parasitics = higher speedLower power consumptionPhysically smaller in size

Integration reduces manufacturing cost - (almost) no manual assembly

WHAT

WHY

VLSI ApplicationsMicroprocessors

personal computersMicrocontrollers(Embedded systems)

Special Purpose Processors - ASICS (CD players, DSP applications)

Mobile and consumer electronics Telecommunications and networking Data processingHealthcare and industrial applications.

MOORE’s LawThe number of transistors on a chip would double about every 18 months

Gordon Moore (Intel)

Origin of this technologyTechnology

No. of transistors /IC

Examples Year

SSI <100 74XX series, 4xxx series

60’s

MSI 100 to 1000

74XXX series,45XX series

70’s

LSI 1000 To 10,000

8085, 80’s

VLSI 10,000 to 10^6

FPGA, CPLD, µC 90’s

ULSI 10^6 to 10^8/ 10^9

Complex SoC present

VLSI Design ProcessSystem

Specification

Functional Design

Logic Design

Circuit Design

Physical Design

Fabrication

Packaging

Factors of VLSI DesignPerformanceCostTime-to-MarketSizeComplexity Silicon Efficiency

Design Style

IC

Gate array

Standard Cell

Full Custom

ASICField Programmable Device

PALPLA

FPGASPLD CPLD

GAL PROM EPROM

Complexity of VLSI circuits

Full custom

Performance Size Cost Market time

Standard Cell Gate Array FPGA

Different design styles

Cost ,Flexibility,Performance

Design Styles

Full Custom Full-custom design is a methodology for designing ICs by specifying the

layout of each individual transistors and the interconnections between them.

Full-custom design potentially maximizes the performance of the chip, and minimizes its area, but is extremely labour-consuming to implement.

Full-custom design is limited to ICs that are to be fabricated in extremely high volumes, notably certain microprocessors and a small number of ASICs.

In the full custom design, the entire mask design is done anew without use of any library.

The development cost of such a design style is prohibitively high.

The concept of design reuse is becoming popular in order to reduce design cycle time and cost.

The most rigorous full custom design can be the design of a memory cell. Static or dynamic.

( Since the same layout design is replicated, there would not be any alternative to high density memory chip design.)

For logic chip design, a good compromise can be achieved by using a combination of different design styles on the same chip . Standard cells, data-path cells and PLAs.

In real full-custom layout in which the geometry, orientation and placement of every transistor is done individually by the designer

Design productivity is usually very low. Typically 10 to 20 transistors per day, per designer.

In digital CMOS VLSI, full-custom design is rarely used due to the high labor cost. Exceptions to this include the design of high-volume products such as memory chips, high-performance microprocessors and FPGA masters.

Full Custom Design ExampleA/D

PLA I/Ocomp

RAMMetal1

Via

Metal2

I/O Pad

(standardcell design)

[©Sherwani]

Full-custom designs:Circuit is partitioned into a collection of sub-circuits according to some criteria such as functionality of each sub-circuit.

It is done hierarchically. Chip is organized in clusters Clusters consists of units Units composed of functional blocks

Functional blocks can be of any sizeThe process is hierarchical and can have several levels of hierarchy.Each block in full-custom design may be very complex and may be consisting of several sub-blocks.Any block can be placed anywhere on the chip without restrictions.

Standard CellBasic idea: All of the commonly used logic cells are developed, characterized, and

stored in a standard cell library. A typical library may contain a few hundred cells. Inverters, NAND

gates, NOR gates, complex AOI, OAI gates, D-latches, and flip-flops. Each cell is designed with a fixed height.– To enable automated placement of the cells, and– Routing of inter-cell connections.– Cells are placed in rows and in between them routing channels are present. The power and ground rails typically run parallel to upper and lower

boundaries of cell.– Neighboring cells share a common power and ground bus.– nMOS transistors are located closer to the ground rail while- the pMOS transistors are placed closer to the power rail.The input and output pins are located on the upper and lower boundaries of the cell.

D C B A

A B C D

VDD Cell Metal 2 Metal 1 Feedthrough GND

Channel

Gate Array In a gate-array-based ASIC, the transistors are predefined on the

silicon wafer The predefined pattern of transistors is called the base array The smallest element that is replicated to make the base array is

called the base or primitive cell The top level interconnect between the transistors is defined by

the designer in custom masks - Masked Gate Array (MGA) Design is performed by connecting predesigned and characterized

logic cells from a library (macros) After validation, automatic placement and routing are typically

used to convert the macro-based design into a layout on the ASIC using primitive cells

Types of MGAs: Channeled Gate Array Channel-less Gate Array Structured Gate Array

Channeled Gate Array Only the interconnect is customized The interconnect uses predefined spaces between rows of base cells Manufacturing lead time is between two days and two weeks

Channel gate-array die Channel-less gate-array die

Channel-less Gate Array or Sea of Gates(SoG) There are no predefined areas set aside for routing - routing is over

the top of the gate-array devices Achievable logic density is higher than for channeled gate arrays Manufacturing lead time is between two days and two weeks

Structured Gate Array Only the interconnect is customized Custom blocks (the same for each design) can be embedded

These can be complete blocks such as a processor or memory array, or

An array of different base cells better suited to implementing a specific function

Manufacturing lead time is between two days and two weeks.

Gate array die with embedded block

FPGAUser programmableArray of logic cells

connected via routing channels

Design time fast , cost less

Three parts:a. Configurable logic

blocks(CLB)b. Programmable

interconnectsc. i/o blocks

Design Methodology

System level

Behavioral level

RTL level

Gate level

Transistor level

Top Down Design Methodology

CAD(Computer Aided Design) tools

CAD tools for VLSI chip design are used in different areas :

•High level synthesis •Logic level synthesis•Circuit optimization•Layout design•Simulation•Design rule check(DRC) and LVS check

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