1

VLSI Digital System Design

Clocking

2

Clocked System

• Basic structure

Q DlogicQ D

clock

3

Fundamental Timing Parameters

• Positive edge-triggered flip-flopCycle Time Tc

Setup Time Ts

Hold Time Th

Clock-to-Q Delay Tq

clock

D

Q

4

Static Storage Elements

• Level-sensitive latch

• Edge-triggered master-slave flip-flop

• RS latch

• T flip-flop

• JK flip-flop

5

Level-Sensitive Latch

clock

QD

clock

QD

Negative level-sensitive latchPositive level-sensitive latch

01

01

6

Positive Edge-TriggeredMaster-Slave Flip-Flop

clock

Q

clock

D 01

01

Master stage Slave stage

7

RS Latch

Q

~Q

R

S

Q

~Q

R

S

8

RS Latch Behavior

• S R Q

• 0 0 Maintain previous state

• 0 1 0

• 1 0 1

• 1 1 Undefined

9

Incorrect T Flip-Flop

clock

Q

clock

01

01

~clear

10

JK Flip-Flop Behavior

• J K Q

• 0 0 Maintain previous state

• 0 1 0

• 1 0 1

• 1 1 Toggle

11

Level-Sensitive Latch Circuit

clock

Q

D

Level-sensitive latch

01

~clock

clock

~clock

clock

DQ

Level-sensitive latch circuit

12

Jamb Latch Circuit

Jamb latch circuit

~Q

D

~clock

clock

weakclock

Q

D

~clock~clock

clock

Level-sensitive latch circuit

13

Jamb Latch Circuit Design

• Replace feedback transmission gate with:

• Feedback inverter that is weaker thandriving inverter

• Either: Decrease gain of feedback transistors– Increase L to decrease W/L

• Or: Increase gain of driving inverter

14

Level-Sensitive Latch Circuit

clock

Q

D

~clock~clock

clock

Level-sensitive latch circuit

clock

Q

D

~clock

~clock

clock

Redrawn level-sensitive latch circuit

15

BufferedLevel-Sensitive Latch Circuit

clock

Q

D

~clock

~clock

clock

Redrawn level-sensitive latch circuit

clock

Q

D

~clock

~clock

clock

Buffered level-sensitive latch circuit

16

Detailed BufferedLevel-Sensitive Latch Circuit

clock

Q

D

~clock

~clock

clock

Buffered level-sensitive latch circuit

clock

Q

D

~clock

~clock

clock

Buffered level-sensitive latch circuit,

details

17

Simplified BufferedLevel-Sensitive Latch Circuit

Q

~clock

clock

Buffered level-sensitive latch circuit,

clock

Q

D

~clock

~clock

clock

Buffered level-sensitive latch circuit

D~clock

clock

with one connection deleted

18

Dynamic Latches

• Time before refresh required depends upon leakage current

• Leakage current depends upon temperature

• Refresh even if behavior independent of stored value– Intermediate voltage level causes

driven gates to draw current

19

Clock Skew

Q D

C

clockR

Inputpad

20

Phase-Locked Loop

Q D

C

clock

PLL

RInputpad

21

Higher On-Chip Clock Frequency

Q D

C

clock

Div by 4

RInputpad

PLL

22

Phase-Locked Loop Block Diagram

FilterPhaseDetector

VoltageControlledOscillator(VCO)

ChargePump

Div by 4

Reference clock fin

4 * fin

23

Probability of Upset

• Upset is the case of a storage element resolving to the wrong data value

• p = probability of upset= T

0 exp( - t

r/t

c )

• T0= constant for the circuit design

• tc

= time constant of resolution for the element

= 1/GB= 1/(gain-bandwidth product)= constant for the circuit design

24

Resolve Time, tr

• p = probability of upset= T

0 exp( - t

r/t

c )

• tr

= resolve time

= time allowed for the storage elementto resolve its state

25

Probability of Upset Example

• T0= 0.1 s

• tc

= 0.1 ns

• tr

= 5.0 ns

• p = T0 exp( - t

r/t

c )

= 0.1 * exp( -5.0/0.1 )= 0.1 * exp( -50 )= 0.1 * 1.9 * 10-22

= 1.9 * 10-23 Hz-1Hz-1s-1

26

Mean Time Between Upsets

• MTBU = 1/( p * fc * f

d )

• p = probability of upset= T

0 exp( - t

r/t

c )

• fc

= clock frequency

• fd

= data frequency

27

MTBU Example

• p = 1.9 * 10-23 Hz-1Hz-1s-1

• fc

= 100 MHz

• fd

= 1 Mhz

• MTBU = 1/( p * fc * f

d )

= 1/( 1.9 * 10-23 * 108 * 106 )= 1/( 1.9 * 10-9 )= 5.2 * 108 s= 16.4 years

28

MTBU Perspective

• May have thousands of storage elementsin a system

• May have thousands or millions of systems

• Provide margin of safety

• Maximize resolve time, tr

29

Synchronizer

Q DQ D

clock

synchronized dataasynchronous data