VLSI DSP 2008 Y.T.HWANG 1-1

VLSI Designs for Digital Signal Processing

Instructor: Yin-Tsung Hwang

Department of Electrical Engineering

National Chung Hsing University

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Chapter 1Introduction to VLSI DSP

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SOC design Era

SOC architecture

MemoryMixed Signal

Processor Coprocessoror

Special FUSoftware

RF

Peripherals

JTAGApplication algorithm

C language

Interface

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Blue Tooth SOC – block diagram

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Blue Tooth SOC – Die photograph

Die size: 40 mm2

CMOS 0.25 m technology

5 metals

Customized function unit& Glue logic

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Hardwired v.s. Programmable Approaches

System design is often a tradeoff amongCost (hardwired)

Time to market (programmable processor)

Area/power (hardwired)

Design flexibility (programmable)

Performance (hardwired)

HW/SW partitioningSoftware modules: executed in CPU (e.g. ARM, PPC), micro processor (e.g. 8051) or DSP

Hardware modules: to perform customized or specific functions

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Wireless Base Station Example

Turbo codingspectrum spread/de-spread

Multi-user detectionRake receiverSmart antennas

HW components

SW components

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DSP for reality processing (1)

Features of DSP algorithmsFiltering, transform, coding and so on

real time process throughput

require high speed and massive computing capabilities

large volume of data

sophisticated algorithm reduced communication BW

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DSP for reality processing (2)

The roles of DSP

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Design by VLSI

Meritshigh integration

high parallelism

High data bandwidth

Reduced power consumption

suitable for modular design

FFT processor design

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What is VLSI DSP?

Implementing specific DSP algorithms in VLSIConverting DSP algorithms to VLSI circuitry

A hardwired solution

Exploiting the merits of VLSI design

Goals: To meet the computing demands

To reduce the power consumption

To reduce the chip area

To reduce the production cost

To achieve wide data bandwidth

To enhance the performance

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Why VLSI DSP? − computing demand (1)

Performance requirements driven by broadband communication

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Why VLSI DSP? − computing demand (2)

Current programmable processor solution

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Why VLSI DSP? − computing demand (3)

Current ASIC (FPGA) solution

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ASIC (FPGA) v.s programmable processor (1)

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ASIC (FPGA) v.s programmable processor (2)

TI C6X processor v.s. Xilinx 4000 series

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Why VLSI DSP? − power issue (1)

Lead microprocessor power continues to increase

Power delivery and dissipation will be prohibitive

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Why VLSI DSP? − power issue (2)

Chip power densitySun’s

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Why VLSI DSP? − power issue (3)

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Why VLSI DSP? − bandwidth issue

Dedicated interconnect among modules to increase data bandwidth

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Applications of VLSI DSP

Video Signal Processing (2D, 3D Filters) Digital communications Neural Networks and

more …….

Signal SynthesisModulation / DemodulationFast Fourier Transforms

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VLSI DSP design issues

Algorithm aspects

Architecture aspects

Circuit implementation aspectsNot addressed in this course

Algorithm to architecture mapping

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Algorithm Aspect (1)

point typegray scale transformation

histogram equalization

quantization

filter typetemplate matching

window technique (e.g. Hamming window)

Convolution / correlation

linear phase filtering

median filtering

moving average

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Algorithm Aspect (2)

Filter type (cont.)wiener filtering optimal for stationary signals to remove additive noise

Kalman filtering good for non-stationary signals

state vectors, measurement equations, errors

inverse filtering special case of Kalman filtering

adaptive filtering Least Mean Square (LMS), Recursive Least Square (RLS)

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Algorithm Aspect (3)

Matrix algebra typesingular value decomposition image processing (coding & enhancement)

channel estimation

Maximum entropy estimation

stochastic pointer estimation

sorter typebitonic sort

bubble sort

insertion sort

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Algorithm Aspect (4)

transform typeFourier transform DFT, FFT, IFFT Time domain v.s. frequency domain transformation Data modulation: OFDM

Cosine transform Discrete cosine transform (MPEG, JPEG) Modified discrete cosine transform (MP3, MPEG4)

Wavelet transform Multi-resolution sub-band coding, JPEG2000, MPEG4

Hough transform to determine all possible straight lines & curves

Hadamard transform speech processing, word recognition, data compression

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Algorithm Aspect (5)

Algorithm selectionPerformance evaluation E.g. LMS vs. RLS

Computing complexity E.g. full search v.s. fast algorithm in motion estimation

Data bandwidth complexity E.g. memory bandwidth, data storage size, I/O pin count

Numerical property E.g. FIR vs. IIR, rounding effect

Parallelism E.g. Schur v.s. Levinson Durbin algorithm

Hardware module reuse

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Algorithm Aspect (6)

Algorithm refinementtransform for parallelism E.g. look ahead transform

computing complexity reduction Fast computing algorithm, e.g. FFT in lieu of DFT

Relaxation in computation, e.g. norm 1 in lieu of norm 2

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Architecture Aspect (1)

Architecture classificationCustomized function unit

Array processor

Customized function unitfor fine grain level

parallelism

Exploit computing

concurrency within

each processing

iteration+ Slicer

R

A

B

1

64

Dual PortRam

64*12bits

LUT256*

10 bits

RAMRAM

RAM

R

R

R

ChannelEstimation

Coefficient

Update

MatchedFilter

Feed-forwardFilter

FeedbackFilter

y'

Cy

d

M

L

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Architecture Aspect (2)

Array processorSystolic architecture

For massive data parallelism

Exploit computing concurrency across processing iterations

Array processor vs. SIMD & MIMD srchitectures

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Architecture Aspect (3)

VLSI array processorsparallel + pipelined processing

wide internal communication BW

locally connected

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VLSI DSP design flow

Application & functional spec.

algorithm

architecture

Circuit implementation

IP authoring

Spec. refinement

Algorithm simulation,Transform, simplification

Architecture mappingResource allocation,Scheduling, pipelining,retimingProcessor element designVerilog coding, Timing closure

Test bench,Behavioral model

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Algorithm to architecture mapping

MappingFrom algorithm domain to architecture domain

Resource allocation

Scheduling

Architecture refinementpipelined adv : 1.clock rate increase 2.power saving

parallel processing

multi-rate

retiming

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Performance gain at different levels

algorithm ( improvement > 10 times)Better algorithm (e.g. QR factorization vs. matrix inverse)

fast algorithm (e.g. FFT in lieu of DFT)

architecture (improvement about 1~2 times)pipelined

parallel processing

multi-rate

retiming

Circuit (improvement about 10%~30% )fast circuit design

improved technology

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Conclusion

Algorithm mapping is crucial !!

Good command of algorithms

Skills of Architecture designs

Bridging the gap between algorithm design and hardware implementation