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Integrated System Design 1

VLSI Design Fundamentals

Low-Power Design

Professor Yusuf Leblebici Microelectronic Systems Laboratory (LSM)

yusuf.leblebici@epfl.ch!

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Reducing the Power Dissipation

The power dissipation can be minimized by reducing: supply voltage load capacitance switching activity

Reducing the supply voltage brings quadratic improvement. Reducing the load capacitance contributes to the improvement of both power dissipation and circuit speed.

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Psw = k CL V2cc fCLK

Reduce Switching Activity: • Conditional clock • Conditional precharge • Switching-off inactive blocks • Conditional execution

Run it slower: • Use parallelism • Less pipeline stages • Use double-edge flip-flop

Technology scaling: • The highest win • Thresholds should scale • Leakage starts to byte • Dynamic voltage scaling

Reduce the active load: • Minimize the circuits • Use more efficient design • Charge recycling • More efficient layout

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Disturbing Predictions for Power

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Controlling VDD and VTH for low power

Low power → Low VDD → Low speed → Low VTH → High leakage → VDD-VTH control

Active Stand-byMultiple V TH Dual-V TH MTCMOSVariable V TH VTH hopping VTCMOSMultiple V DD Dual-V DD Boosted gate MOSVariable V DD VDD hopping

*) MTCMOS: Multi-Threshold CMOS *) VTCMOS: Variable Threshold CMOS • Multiple : spatial assignment • Variable : temporal assignment

Software-hardware cooperation

Technology-circuit cooperation

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Dual-VTH concept

Low-VTH circuit!(High leakage)!

High-VTH circuit!(Low leakage)!

Critical paths!

Non-critical paths!

(* from Prof. T. Sakurai)

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Clustered Voltage Scaling for Multiple VDD’s

Lower V DD portion is shown as shaded

CVS Structure Conventional Design

Critical Path

Level-Shifting F/F

Critical Path

FF

FF FF FF FF FF

FF FF FF FF

FF

FF

FF

FF FF FF

FF

FF FF FF

FF

M.Takahashi et al., “A 60mW MPEG4 Video Codec Using Clustered Voltage Scaling with Variable Supply-Voltage Scheme,” ISSCC, pp.36-37, Feb.1998.

Once VL is applied to a logic gate, VL is applied to subsequent logic gates until F/F’s to eliminate DC current paths. F/F’s restore VH.

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Energy consumption is proportional to the square of VDD.

VDD should be lowered to the minimum level which ensures the real-time operation.

Normalized workload 0.0 0.2 0.4 0.6 0.8 1.0

Nor

mal

ized

pow

er

0.0

0.2

0.4

0.6

0.8

1.0

Variable Vdd Fixed Vdd

VDD should be as low as possible

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TransMeta Example

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TransMeta Example

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*Taken from Doug Laird’s presentation, January 19 th 2000

TransMeta Example

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TransMeta Example

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Why is lowering VDD not enough ?

•  Total P can be minimized by lower V –  lower V are a natural result of smaller feature sizes

•  But… transistor speeds decrease dramatically as V is reduced to close to “threshold voltage” –  performance goals may not be met –  td = CV / k(V-Vt)α where α is between 1-2

•  Why not lower this “threshold voltage”? –  makes noise margin and Ileak worse!

•  Need to do smarter voltage scaling!

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Reducing the Supply Voltage: Architectural Approach

•  Operate at reduced voltage at lower speed •  Use architecture optimization to compensate for

slower operation –  e.g. concurrency, pipelining via compiler techniques

•  Architecture bottlenecks limit voltage reduction –  degradation of speed-up –  interconnect overheads

•  Similar idea for memory: slower and parallel Trade-off AREA for lower POWER

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Example: Reference Datapath

  Critical path delay: Tadder + Tcomparator = 25 ns   Frequency: fref = 40 MHz   Total switched capacitance = Cref   Vdd = Vref = 5V   Power for reference datapath = Pref = CrefVref

2fref

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Parallel Datapath

  The clock rate can be reduced by x2 with the same throughput: fpar = fref/2 = 20 MHz   Total switched capacitance = Cpar = 2.15Cref   Vpar = Vref/1.7   Ppar = (2.15Cref)(Vref/1.7)2(fref /2) = 0.36Pref

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Pipelined Datapath

  fpipe = fref Cpipe = 1.1Cref Vpipe = Vref/1.7   Voltage can be dropped while maintaining the original throughput   Ppipe = CpipeVpipe

2 fpipe = (1.1Cref)(Vref/1.7)2 fref = 0.37Pref

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Datapath Architecture-Power Trade-off Summary

DatapathArchitecture

Voltage Area Power

Original 5V 1 1Pipelined 2.9V 1.3 0.37Parallel 2.9V 3.4 0.34Pipeline-Parallel 2.0V 3.7 0.18

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Power = Energy/transition * transition rate

= CL * Vdd2 * f0→1

= CL * Vdd2 * P0→1* f

= CEFF * Vdd2 * f

Power Dissipation is Data DependentFunction of Switching Activity

CEFF = Effective Capacitance = CL * P0→1

Power Dissipation Depends on Switching Activity !

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Example: Static 2 Input NOR Gate

Assume:P(A=1) = 1/2P(B=1) = 1/2

P(Out=1) = 1/4P(0→1)

= 3/4 × 1/4 = 3/16

Then:

= P(Out=0).P(Out=1)

CEFF = 3/16 * CL

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Transition Probabilities for Basic Gates

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Transition Probabilities for Basic Gates