Saraju P. Mohanty 1

VLSI Design and CAD Research VLSI Design and CAD Research at at

University of North TexasUniversity of North Texas

Saraju P. Mohanty Dept of Computer Science and Engineering

University of North Texassmohanty@cs.unt.edu

http://www.cs.unt.edu/~smohanty/

Associated LaboratoryVLSI Design and CAD Laboratory

http://www.vdcl.cse.unt.edu

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Outline of the Talk

About VDCLResearch ActivityPublicationsOpportunities for Masters and Ph.D.

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VDCLEstablished in August 2004Mission:

to carry out research in low power VLSI designto prepare next generation CAD tools for automatic design

One Faculty, one associated Faculty, and six student members.Located at F233.State-of-art research infrastructure include Sun Fire server, Dual-Xeon Servers, Sun Workstations, Linux Workstations and Tera Bytes of storage.Licensed and free CAD tools available.

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CMOS Driven Applications

Almost the entire industry today is driven by CMOS

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What is an Integrated Circuit ?

An integrated circuits is a silicon semiconductor crystal containing the electronic components for digital gates.Integrated Circuit is abbreviated as IC.The digital gates are interconnected to implement a Boolean function in a IC .The crystal is mounted in a ceramic/plastic material and external connections called “pins” are made available.ICs are informally called chips.

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How does a microprocessor look?

(1) ASIC (2) Sun UltraSparc (3) PentiumPro

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Design Abstraction Levels

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

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Digital Circuits : Logic to Device

(Transistor Diagram) (Layout Diagram)

(NAND Gate)

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Pentium IV : 52M Transistors (2001)

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VLSI Technology: Highest Growth in History

1958: First integrated circuitFlip-flop using two transistorsBuilt by Jack Kilby at Texas Instruments

2003Intel Pentium 4 μprocessor (55 million transistors)512 Mbit DRAM (> 0.5 billion transistors)

53% compound annual growth rate over 45 years

No other technology has grown so fast so longDriven by miniaturization of transistors

Smaller is cheaper, faster, lower in power!Revolutionary effects on society

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VLSI Industry : Annual Sales

1018 transistors manufactured in 2003100 million for every human on the planet

0

50

100

150

200

1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002

Year

Global S

emiconductor B

illings(B

illions of US

$)

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Research Interests

Synthesis and Optimization for Low Power Power Aware System Design VLSI Architecture for Security and Copyright Protection CAD and Modeling for Nanoscale VLSI Circuits

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Research Interests …

Synthesis and Optimization for Low Power Vary supply voltage, clock frequency, switching activity and capacitance, physical parameter through various phases of the synthesis process while considering their interactions and trade-offs.

Power Aware System DesignAim is to provide a low power, high performance architecture followed by its VLSI implementation for different applications, such as image and video processing, and wireless system

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Research Interests …

VLSI Architecture for Security and Copyright Protection

Goal is to develop architectures to perform compression, encryption, watermarking and scrambling in a common hardware.

CAD and Modeling for Nanoscale VLSI Circuits

Plan is to develop models for fast characterization of architectural and logic cells made of non-classical CMOS.

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Why Low Power?

Major MotivationReducing Power ConsumptionIncreasing Battery LifeMaking Portable Devices Really Portable…

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Why Low Power? …

Environmental concerns Battery life

Chip and system

cooling costs

Power supply rail design

Packaging costs

Noise immunity and

system reliability

Power directly affects

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Why Low-Power ? ……..

Power Density

IV

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Power Dissipation Components in CMOS

Source: Weste and Harris 2005

Total Power Dissipation

Static Dissipation Dynamic Dissipation

Sub-threshold current

Tunneling currentTunneling current

Reverse-biased diode Leakage

Capacitive Switching

Short circuit

Contention current

Tunneling currentTunneling current

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Leakages in Nanometer CMOSI1 : reverse bias pn junction (both ON & OFF)I2 : subthreshold leakage (OFF )I3 : oxide tunneling current (both ON & OFF)I4 : gate current due to hot carrier injection (both ON & OFF)I5 : gate induced drain leakage (OFF)I6 : channel punch through current (OFF)

P-Substrate

N+ N+

Source DrainGate I3 , I4

I1

I2I6

I5 Source: Roy 2003

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Power Dissipation Trend

Source: Hansen 2004

Tunne

ling

Tunne

ling

Trajectory, With High-K

DynamicSu

b-Th

resh

old

Gate Length

Chronological (Year)

Nor

mal

ized

Pow

er D

issi

patio

n

Phy

sica

l Gat

e Le

ngth

(nm

)

102

100

10-2

10-4

10-6

300

250

200

150

100

50

01990 1995 2000 2005 2010 2015 2020

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DKDT Based Logic SynthesisInput Circuit

Mapped Circuit

Intermediate Circuit

DKDT Assignment and Optimization

Technology Mapping

CellLibrary

(4 Types)K 1T1K 1T2K 2T1K 2T2

Tunneling Optimized Circuit

Placement and Routing

Final Circuit Layout

Technology Independent Optimization

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DKDT Technique: Results

NOTE: DKDT has no time penalty.

0102030405060708090

100

C432

C499

C880

C1355

C1908

C2670

C3540

C5315

C6288

C7552

Lee 2004

Sultania 2004

DKDT

% R

educ

tion

Benchmark Circuits

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Facts about the latest chip designed

(Claim: Lowest power consuming image watermarking chip available at present)

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Chip: Statistics

Technology: TSMC 0.25 µTotal Area : 16.2 sq mmDual Clocks: 280 MHz and 70 MHzDual Voltages: 2.5V and 1.5VNo. of Transistors: 1.4 millionPower Consumption: 0.3 mW

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Our Publication StatisticsSummary:

6 ACM/IEEE transactions accepted and several in pipeline29 peer reviewed IEEE/ACM conference papers

Selected List:S. P. Mohanty and N. Ranganathan, “Simultaneous Peak and Average Power Minimization during Datapath Scheduling”, IEEE Transactions on Circuits and Systems Part I (TCAS-I), Vol. 52, No. 6, June 2005, pp. 1157-1165.S. P. Mohanty and N. Ranganathan, “Energy Efficient DatapathScheduling using Multiple Voltages and Dynamic Clocking”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 10, No. 2, April 2005, pp. 330-353.S. P. Mohanty, N. Ranganathan, and R. K. Namballa, "A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S^2DC) Design", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 13, No. 7, July 2005, pp. 808-818. S. P. Mohanty and N. Ranganathan, “A Framework for Energy and Transient Power Reduction during Behavioral Synthesis”, IEEE Transactions on VLSI Systems (TVLSI), Vol. 12, No. 6, June 2004, pp. 562-572.

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Ph. D. in Computer Science

Background or through course:CMOS VLSIVLSI CADAlgorithmsGraph TheoryOptimization TechniquesArchitecture

Can focus on:Any of the four research interests mentioned

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MS in Computer Science

Background or through course:CMOS VLSIVLSI CADAlgorithmsGraph TheoryOptimization Techniques

Can focus on:CAD and Optimization for VLSI

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MS in Computer Engineering

Background or through course:CMOS VLSISemiconductor PhysicsAlgorithmsAdvanced VLSI Systems

Can focus on:Any of the four research interests mentioned

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Advantages of Thesis Option

Less number of credit hoursChance of getting degree in 3 full semestersChances of getting assistantship is higherImproves credibility of your masters degreeHigher chances of getting better jobMore bargaining power for salary

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Thank You !!!