VLP0303VHDL_environment_for_floating_point_Arithmetic_Logic_Unitdesign_and_simulation

8/7/2019 VLP0303VHDL_environment_for_floating_point_Arithmetic_Logic_Unitdesign_and_simulation

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VHDL environment for floating point Arithmetic Logic Unit - ALUdesign and simulation

1Rajit Ram Singh 2Vinay Kumar Singh 3poornima shrivastav 4Dr. GS [email protected] VINDHYAIndore- India

vinay. [email protected] Motors Ltd. Luck now -India

[email protected] Gwalior -India

ABSTRACTVHDL environment for floating point arithmetic andlogic unit design using pipelining is introduced; thenovelty in the ALU design.Pipeling provides a highperformance ALU. Pipelining is used to executemultiple instructions simultaneously. In top-downdesign approach, four arithmetic modules, addition,subtraction, multiplication and division are combined toform a floating point ALU unit. Each module is dividedinto submodules. Two selection bits are combined toselect a particular operation. Each module isindependent to each other .all modules in the ALUdesign are realized using VHDL, design functionalitiesare validated through VHDL simulation .allcomponents and module is successfully run, Synthesisand Simulation in the Xilinx12.1i software.

Keywords: ALU- Arithmetic Logic Unit, Top-Downdesign, Validation, Floating point, Test-Vector\

I.INTRODUCTION

Floating point describes a system for representingnumbers that would be too large or too small to berepresented as integers. Floating point representation isable to retain its resolution and accuracy compared tofixed point representation. Numbers are in generalrepresented approximately to a fixed number of significant digits and scaled using an exponent. Thebase for the scaling is normally 2, 10 or 16. The typicalnumber that can be represented exactly is of the form:

Significant digits Baseexponent

S B e

IEEE 754 standard for floating point representationin 1985. Based on this standard ,floating pointrepresentation for digital system should be platform independent and data are interchanged freely amongdifferent digital systems.

Arithmetic logic unit (ALU) is a digital circuitthat performs arithmetic and logical

operations. The ALU is a fundamentalbuilding block of the central processing unit(CPU) of a computer. e inputs to the ALU arethe data to be operated on (called operands)and a code from the control unit indicatingwhich operation to perform. Its output is theresult of the computation.

In many designs the ALU also takes or generates asinputs or outputs a set of condition codes from or to astatus register. These codes are used to indicate casessuch as carry-in or carry-out, overflow, divide-by-zero,etc. Floating Point Unit also performs arithmeticoperations between two values, but they do so fornumbers in floating point representation. And the ALUwith floating point operations is called a FPU.

Top-down approach (is also known as step-wise design) is essentially the breaking downof a system to gain insight into its

compositional sub-systems. In a top-downapproach an overview of the system isformulated, specifying but not detailing anyfirst-level subsystems. Each subsystem is thenrefined in yet greater detail, sometimes inmany additional subsystem levels, until theentire specification is reduced to baseelements. A top-down model is often specifiedwith the assistance of "black boxes", thesemake it easier to manipulate. However, black boxes may fail to elucidate elementarymechanisms or be detailed enough torealistically validate the modelIn order to stimulate a device off board, aseries of logical vectors must be applied to thedevice inputs. These vectors are called testvectors and are mostly used to stimulate thedesign inputs and check the outputs against theexpected values.

An pipeline is a technique used in the designof computers and other digital electronicdevices to increase their instruction throughput


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(the number of instructions that can beexecuted in a unit of time).

The fundamental idea is to split the processing of acomputer instruction into a series of independent steps,with storage at the end of each step. This allows thecomputer's control circuitry to issue instructions at theprocessing rate of the slowest step, which is much fasterthan the time needed to perform all steps at once. Theterm pipeline refers to the fact that each step is carryingdata at once (like water), and each step is connected tothe next (like the links of a pipe.)The origin of pipelining is thought to be the IBM Stretchproject(1954) .Implementing pipeline requires variousphases of floating point operations be separated and bepipelined into sequential stages.We propose VHDL environment for floating pointALU design and simulation. To ease the description,verification, simulation and hardware realization.VHDL is widely adopted standard and has numerouscapabilities that are suited for designs of this sort .theuse of VHDL for modeling is especially appealing sinceit provides formal description of the system and allowsthe use of specific description styles to cover thedifferent abstraction levels(architectural, register ,transfer and logic level) employed in design .

II MATERIAL AND METHODS

The main objective of this paper is to describes theimplementation of pipelining in design the floating -point ALU using VHDL.. the sub-objective s are todesign a 16-bit floating point ALU operating on the

IEEE 754 standard rd .floating point representations,supporting the four basic arithmetic operations;addition, subtraction, multiplication and division.second sub-objective is to model the behavior of theALU design using VHDL.Specifications for a 16-bit floating-point ALU design.

i. Input A and B and output result are 16-bit binaryfloating point.

ii. Operands A and B operate as followsA (operation) B=resultsOperation can be addition (+), subtraction (-),Multiplication (*), division (/)

iii. Selection a 2-bit input signal that selects

ALU operation and operate as shown in table1.iv. Status a 4-bit output signal work as a flag anmicroprocessor.

Table1: select ALU operation.

v. Clock pulse is only provided to the modulewhich is selected using demux.vi . Concurrent processes are used to allow

processes to run in parallel hence pipelining

Fig:1 top level view of the ALU design

ALU is separated into smaller modules:addition,subtraction,moltiplication and division,demuxand mux.each arithmetic module is further divided intosmaller modules .the top level view of fig.1 shows thetop level view of the ALU .it consist of four functionalarithmetic modules, three demultiplexes and twomultiplexers. the demuxs and muxes are used to routeinput operands and the clock signal to the correctfunctional modules .they also route outputs and statussignals based on the selector pins.

Output status0000 Normal operation0001 Overflow0010 Underflow0100 Result zero1000 Divide by zero

Selection Operation

00 Addition01 Summation10 Multiplication11 Division


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Fig: 2 view of selection of a add module

After a module completes its task, outputs and statussignals are sent to the muxes where they multiplexeswith other outputs from corresponding modules toproduce output result selector pins are routed to thesemuxes such that only the output from currentlyoperating functional module is sent to the output port.Clock is specifically routed rather then tiedpermanently to each module since only the selectedfunctional modules need clock signals. This providespower savings since the clock is supplied to therequired modules only and avoid invalid results at theoutput since the clock is used as a trigger in everyprocess.

Pipelining floating point addition module:

Addition module has two 16 bit inputs and one16 bitoutput selection input is used to enable or disable themodule this module is further divided into 4 submodules zero check, align, add_ sub and normalizemodule.

Fig: 3 pipeline floating point addition

Zero check modules:

This module detects zero operands early in theoperation and based on the detection result it has twostatus signals. This eliminates the need of sub sequentprocesses to check for the presence of zero operandstable 1 summarize the algorithm

Tab:1 setting zero check bit

Align moduleIn this module operations are perform based on status signal from previous stage zero operands are

Checked in the align module as well this moduleintroduces implied into the operands shown in table.

Tab:2 setting of implied bit

Add_ sub moduleThis module performs actual addition and subtractionof operands. Firstly operands are checked via the statussignals are carried out results are automaticallyobtained if either of the operand are zero shown in table3 normalization is needed if no calculation are donehere the operation is done based on the science and therelative magnitude of mantissa i.e. summaries in table 4status signal is set to one is indicate the need of normalization by the next stage

Zero_a2&zero_b2

Zero_a1xor

zero_b1

Zero_a2 Result

0 0 X Performadd_sub

0 1 1 b stage20 1 0 a stage21 X X 0

Tab:3 check for add_sub module

Tab: 4 add_sub operation

I/P a I/P b Zero_a1 Zero_b10 0 1 10 NZ 1 0NZ 0 0 1NZ NZ 0

Zero_a1xorzero_b1

a_sign Impliedbit for a

Impliedbit for b

0 X(dotcare)

0 0

1 1 0 11 0 1 0

Operation a_signxorb_sign

a>b Result Sign

a + b 0 X a+b +ve(-a)+(-b) 0 X a+b -vea+(-b) 1 Yes a-b +vea+(-b) 1 No b-a -ve(-a)+b 1 Yes a-b -ve(-a)+b 1 No b-a +ve


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Normalize module

Input is normalize and packed into the IEEE 754floating point representation if the normalize statussignal is set normalization is perform otherwise MSB isdropped .

Pipeline floating point subtraction module:

Subtraction module has two 16-bits inputs and one 16-bit output. Selection input is used to enable/ disable theentity depend on the operation. This module is dividedfurther into four sub-modules: zero-check alignsadd_sub and normalize module. The subtractionalgorithm differs only in the add_sub module where thesubtraction operator changes the sign of the result. thereaming three modules are similar to those in theaddition module.tab5 and tab 6 summarize theoperation

Tab: 5 checks for add_sub module

Operation a_signxorb_sign

a>b Result sign

(-a)-b 1 X a+b -vea-(-b) 1 X a+b +ve(-a)-(-b) 0 Yes a-b -ve(-a)-(-b) 0 No b-a +vea-b 1 Yes a-b +vea-b 1 No b-a -ve

Tab: 6 add_sub operation and sign fixing

Pipelined floating point multiplication module

Multiplication entity has three 16-bit inputs and two 16-bit outputs. Selection input is used to enable/disable theentity. multiplication module is divided into check-zero,check-sign, add-exponent and normalize and-concatenate all modules, which are executedconcurrently .status signal indicates special result casessuch as overflow, underflow and result zero, in thisproject pipelined floating point multiplication is dividedin to three stages(fig-4).stage1 checks whether the

operand is zero and report the result accordingly.stage2determines the product sign, add exponents andmultiply fractions.stage3 normalize and concatanitatethe product.

Fig 4. Pipeline structure of multiplication module

Check-zero module

Initially two operands are checked to determinewhether they contain a zero .if one of the operand iszero ,the zero_flag is set to 1 .the output results zero. if neither of them is zero then the inputs with IEEE 754format is unpacked and assigned to the check sign, addexponent and multiply mantissa modules, the mantissais packed with hidden bit 1.

Add exponent moduleThe module is activated if the zero flag is set .else zero

is passed to the next stage and exp_flag is set to 0,twoextra bit are added the exponent indicating overflowand underflow.

Multiply mantissa moduleIn this stage zero_flag is checked first. if the zero_flagis set to 0,then no calculation and normalization isperformed. The mant_flag is set to 0 if both theoperands are nonzero after the multiplication is donemant_flag is set to 1 to indicate that this operation isexecuted.

Check sign moduleThis module determines the product sign of twooperands .the product is positive, when the twooperands have the same sign; otherwise it is negative.The sign bit are compared using XOR circuit. thesign_flag is set to 1.Normalize and concatenate module

This module checks the overflow and underflow occursif the 9 th bit is 12.overeflow occurs if the 8 th bit is 1.if exp_flag, sign_flag and mant_flag are set, thenormalization is carried out. Otherwise, 16-zero bits areassigned to the result.

Zero_a2&zero_b2

Zero_a2xorzero_b2

Zero_a2

b_sign Result sign

0 0 X X Performadd_sub

NA

0 1 1 0 b_stage2 b_sign=10 1 1 1 b_stage2 b_sign=00 1 0 X a_stage2 a_sign1 X X X 0 NA


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During the normalization operation, the mantissa MSBis 1, hence no, normalization is needed. the hidden bit isdropped and the reaming bit is packed and assigned tothe output port .normalization module set the mantissaMSB to 1.the current mantissa is shifted left until 1 isencountered .foe each shift the exponent is decreasedby 1,if the mantissa MSB is 1,normalization iscompleted and first bit is the implied bit dropped. Theremaining bits are packed and assigned to the outputport. The final normalization product with the correctbiased exponent is concatenated with product sign.

Pipelined floating point division module

Division entity has three 16-bit inputs and two 16-bitoutputs. Selection input is used to enable or disable theentity. Division module is divided into six modules:check zero, align, dividend check sign, subtractexponent, divide mantissa and normalize concatenatemodules. Each module is executed concurrently. Statusindicates the special cases such as overflow, underflow,and result zero and divides by zero. Fig shows thepipeline structure of the division module.

Fig: 5 pipeline structure of the division module

Check-zero modules:

Initially two operands are checked to determinewhether they contain a zero .if one of the operand iszero, the zero_flag is set to 1 .the output results zero. If neither of them is zero then the inputs with IEEE 754format is unpacked and assigned to the check sign, addexponent and multiply mantissa modules, the mantissais packed with hidden bit 1.

Add exponent module:

The module is activated if the zero flag is set .else zerois passed to the next stage and exp_flag is set to 0,twoextra bit are added the exponent indicating overflowand underflow.Multiply mantissa module:

In this stage zero_flag is checked first. if the zero_flagis set to 0,then no calculation and normalization isperformed. The mant_flag is set to 0 if both theoperands are nonzero after the multiplication is donemant_flag is set to 1 to indicate that this operation isexecuted.

Check sign module:

This module determines the product sign of twooperands .the product is positive, when the twooperands have the same sign; otherwise it is negative.the sign bit are compared using XOR circuit. thesign_flag is set to 1.

Align dividend module:

This module compares both mantissas. if mant_a isgreater than or equal to the msant_b then the mant_amust be aligned .for every bit right shift of the mant_amantissa ,the mant_a exponent is then increased by1.this increase may result in an exponent overflow, inthis case an overflow flag is set. Otherwise, the processcontinues with the parallel operation of exponentsubtraction and mantissa division. Align_flag is set to 1.

Subtract exponent module

This module is activated if the zero flag is set. if not,zero value is passed to the next stage and exp_flag isset to 0.two extra bits are added to the exponent toindicate overflow .here two exponents are subtracted.the bias is added back. after this the exp_flag is set to

1.Divide mantissa module

In this stage ,align flag is checked first. if align flag is 0then no mantissa division is performed .mant_flag isset to 0.if both operand are not zero, mant_a is dividedby mant_b .in division algorithm ,comparison betweentwo mantissa is done by subtracting the two values andchecking the output sign.

III .SIMULATION AND DISCUSSION

Design is verified through simulation, which is done in

a bottom up fashion .small modules are simulated inseparate test benches before they are integrated andtested as a whole.Align RTL1:


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Simulation Result of Align:

RTL of Demux:

Demux wave :


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Multiplexer:

Simulation result of Mux:

RTL of division:

RTL division:

Iv COCLUSION

By simulating with various test vectors the proposedapproach of pipeline floating point proposed approachOf pipeline floating point ALU design using VHDL issuccessfully designed, tested and implementedcurrently, we are conducting further research thatconsider the further reduction in the hardwarecomplexity in terms of synthesis and fully download thecode into Altera FLEXIOK: EPFIOKIOLC, FPGA chip

on LC 84 package for hardware realization

Reference:

[IIANSIWEE Std 754-1985, IEEE Standard forBinary Flooring-Point Arithmetic, IEEE, NewYork, 1985.[2]M. Daumas, C. Finot, "Division of Floating PointExpansions with an Application to theComputation of a Determinant", Journal o/ Universol Compurer Science, vo1.5, no. 6, pp. 323-338, June 1999.[3]AMD Athlon Processor techmcal brief, Advance

Micro Devices Inc., Publication no. 22054, Rev. D,Dec. 1999.[4]S. Chen, B. Mulgeew, and P. M. Grant, "AClustering techmque for digital communicationsChannel equalization using radial basis functionNetworks,'' IEEE Trans. Neural Networks, vol. 4,pp. 570-578, July 1993.[5] Mamu Bin Ibne Reaz, MEEE, Md. Shabiul Islam,MEEE, Mohd. S. Sulaiman, MEEE. ICSE2002 Proc.2002,penang-Malaysia.

Simulation of division :


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VLP0303VHDL_environment_for_floating_point_Arithmetic_Logic_Unitdesign_and_simulation