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© Copyright 2018 Xilinx Presented By Balachander Krishnamurthy Sr. Product Marketing Manager October 2 nd , 2018 Vivado Synthesis Tips & Tricks

Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

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Page 1: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

Presented By

Balachander Krishnamurthy

Sr. Product Marketing Manager

October 2nd, 2018

Vivado Synthesis Tips & Tricks

Page 2: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

Topics for Today

˃ The UltraFast Design Methodology

˃ UFDM: Customer Case Study

˃ Waiver Mechanism

˃ Vivado Incremental Synthesis

˃ QoR: Tips & Tricks

2

Page 3: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

UltraFast Design Methodology

3

Page 4: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

UG1292: UFDM Timing Closure Quick Reference Card

˃ Step-by-step Analysis and

Suggestions

˃ Address common timing

closure challenges

HLx and SDx

Project and Non-project

6

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug1292-ultrafast-timing-closure-quick-reference.pdf

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug1292-ultrafast-timing-closure-quick-reference.pdf
Page 5: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

Report Run Strategies

˃ Create custom report strategies similar to custom

run strategies

˃ Improve compile time

Select which reports are generated for each run

Configure options for each report individually

˃ Reuse report strategies across runs and projects

5

Page 6: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

UFDM: Customer Case Study

7

Page 7: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

Customer Case Study: Design not functional

˃ Major Xilinx customer with tight production deadline

˃ Customer claimedRunning ‘place_design -fanout_opt’ caused functional issue

Adding ILA to DCP, design issue is gone

Not a CDC issue

˃ OneSpin equivalency checking is cleanopt_design DCP compared with place_design DCP

˃ SR filed and escalated to factory

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Page 8: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

˃ Many UltraFast Methodology Violations

Timing -1 Incorrect clock waveform

Timing-3 Breaking clock propagation delay and potentially skew accuracy

Timing-6, 27 Primary clock defined on hierarchical pin

Timing-36 Inaccurate skew due to missing insertion delay on a generated clock

Customer Case Study: Analysis by factory

9

Page 9: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

˃ Report CDC flagged ~10K Critical violations!

Waivers can help focus on new or un-reviewed issues

˃ CDC-11 violations introduced by placer fanout opt

User allowed replication of CDC endpoint (RAMB/WE control signal)

=> RAMBs written in different cycles

Safe CDC topology would have prevented replication

˃ OutcomeDesign working after addressing methodology and CDC violations

Customer Case Study: Analysis by factory …2

WE

10

Page 10: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

Waiver Mechanism

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Page 11: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

Waiver Mechanism

˃ Hide violations in CDC/DRC/Methodology checks in the designFocus only on what is relevant

˃ Waivers can be created, queried, reported against and deletedTrack user, timestamp and description

Waivers should be reviewed by the design team

XDC Compatible, allows read/write and scoping

Duplicate waivers ignored

˃ Recommend Don’t waive Critical violations

Waive Warning (after reviewing them) and Info types

˃ Xilinx IPs have adopted waiver mechanism

˃ DocumentationUG906: Design Analysis and Closure Techniques

UG938: Tutorial Design Analysis and Timing Closure (NEW)

12

Page 12: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

Creating a Waiver

˃ Create from: Report CDC / DRC / Methodology result window

˃ Create from: CDC / DRC / Methodology violation objects

˃ Create from: manual specification of all argumentsArguments are order dependent. They must match order inside the violation object

report_cdc -name cdc_1foreach vio [get_cdc_violations -name cdc_1 -filter {CHECK == CDC-1}] {

if {[regexp {^top/sync_1} [get_property STARTPOINT_PIN $vio]]} {create_waiver -of $vio -description {Safe by protocol}

}}

Notice: only description

argument specified with

this method.

13

Page 13: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

Reporting Waivers

˃ In Report CDC / DRC / Methodology GUI (and command

line)

Report can be generated with the waivers

Report can be generated by ignoring the waivers

Can report only waived violations

˃ report_waivers

Only Text Based

GUI Support coming soon

Report CDC/DRC/Methodology must be run prior to extract statistics

Useful Waiver Commandscreate_waiver

get_waivers

delete_waivers

write_waivers

report_waivers

14

Page 14: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

Vivado Incremental Synthesis

15

Page 15: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

Incremental Synthesis

˃ Flow similar to incremental P & R

˃ Benefits:40% synthesis runtime reduction

‒ Change is localized

Iterate quickly while working on a module

More design iterations in the front end

Improved predictability in results

Fewer changes in netlist structure when compared to previous flow

Improved results/QoR/runtime when used with Incremental P & R

Revised RTL

Synthesis

Reference

Checkpoint

RTL ChangeReference RTL

synth_design read_checkpoint

–incremental

synth.incr.dcp

write_checkpoint

–incremental_synth

synth.incr.dcp

Reference Run Incremental Run

synth_design

16

Page 16: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

Top Module (M)

M1

Incr. Synthesis - Cross-Boundary Optimizations

˃ More cross boundary optimizations leads to more re-synthesis (G’1 G’2)

˃ Changed / dissolved partitions also need to be re-synthesized

Reference Run

➢ Track cross-boundary optimizations

Incremental Run

➢ Re-synthesize changed modules + its dependencies

G1M3

G2

M4

Top Module (M’)

M1

M3

G3

G4

M4

G3

G4

G2

G3

G4

G2

G1

G2G3

G1G4

Mc

G’1

G’2

18

Page 17: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

Log file and Non-Project Mode Flow˃ Reference run

run.tcl

‒ synth_design

‒ write_checkpoint –incremental_synth –force postSynth.dcp

‒ opt_design

‒ place_design

‒ Phys-opt_design optimizations1

‒ route_design

‒ write_checkpoint routed.dcp

‒ Phys-opt_design optimizations2

‒ write_checkpoint ref_run_post-route_physopt.dcp

˃ Incremental runrun.tcl

‒ read_checkpoint –incremental ../ReferenceRunDir/postSynth.dcp

‒ synth_design

‒ write_checkpoint –incremental_synth –force postSynth_incr.dcp

‒ opt_design

‒ read_checkpoint –incremental ../ReferenceRunDir/ref_run_post-route_physopt.dcp optimizations1 + optimizations2

‒ place_design

‒ route_design

‒ write_checkpoint routed_incr.dcp

19

Report has 4 sections

1. Incremental synthesis was run or Not

2. Changed Modules and %Resynthesis

3. Check point details

4. RTL partitions (Reuse and Resynthesis)

Page 18: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

QoR: Tips & Tricks

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Page 19: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

Tips and Tricks: ROM Optimization

Missing uniformity in ROM data => 64th location

• 64-deep ROM, 4-bit wide accessing different locations

• Loop with 30 iterations

• 10 ROM structures per iteration (300 ROMs in total)

• Data in 0-15 repeated in 16-31. 32-47 and 48-62

• Could this be 16 deep instead of 64 deep?

21

Page 20: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

Tips and Tricks: ROM Optimization

Check the condition to access the data for address#63

The ROM now can become 16-deep and 4-bit wide

22

LUT difference = Original – Proposed (3087 - 1826) = 1261

Page 21: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

Tips and Tricks: 500 MHz Wide Multiplier

• Tip: Review log file

• 36 DSP’s for 100x100 multiplier

• Not meeting timing, needs pipeline registers

• 8 pipeline registers needed for timing closure

24

Page 22: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

Tips and Tricks: Multiplier => LUT mapping

˃ Higher utilization v/s competition for multipliers

˃ Need to compare LUT based mapping

Map to DSP (use_dsp48 = “no”)

Convert to LUT based (-max_dsp 0)With use_dsp48 = “no” attribute

With –max_dsp 0

25

Page 23: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx

Summary

˃ Following the UltraFast Design Methodology reduces Time-to-Market

˃ Waiver Mechanism for CDC, Methodology and DRCs enables clean

reports and design sign-off

˃ Ensure Clock Domain Crossing issues are reviewed and fixedUse the waiver mechanism to focus on real issues

˃ Vivado Incremental synthesis reduces compile time

Reach out to your FAE for details/issues

26

Page 24: Vivado Synthesis Tips and Tricks - Xilinx...Title: Vivado Synthesis Tips and Tricks Author: Jeffrey Myers Created Date: 12/18/2018 2:54:53 PM

© Copyright 2018 Xilinx


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