Virtuoso Layout Accelerator User Guidechiataimakro.vicp.cc:8880/待整理/Cadence IC设计/cadence版图设计/版图设计...Virtuoso Layout Accelerator User Guide June 2000 3 Product

Virtuoso Layout Accelerator User Guide

Product Version 4.4.6June 2000

1995-2000 Cadence Design Systems, Inc. All rights reserved.Printed in the United States of America.

Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA

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Disclaimer: Information in this publication is subject to change without notice and does not represent acommitment on the part of Cadence. The information contained herein is the proprietary and confidentialinformation of Cadence or its licensors, and is supplied subject to, and may be used only by Cadence’s customerin accordance with, a written agreement between Cadence and its customer. Except as may be explicitly setforth in such agreement, Cadence does not make, and expressly disclaims, any representations or warrantiesas to the completeness, accuracy or usefulness of the information contained in this document. Cadence doesnot warrant that use of such information will not infringe any third party rights, nor does Cadence assume anyliability for damages or costs of any kind that may result from use of such information.

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Contents

Preface ............................................................................................................................... 12

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Typographic and Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1

Intr oduction to the Vir tuoso La yout Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2

Editing Y our Technology File f or Vir tuoso La yout Accelerator . . . . . . . . . . . . . . . 17

Sample Technology File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Virtuoso XL Technology File Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Layer Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Physical Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Virtuoso XL Rules (lxRules) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Compactor Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3

Preparing Y our Connectivity Sour ce

for the Vir tuoso La yout Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Placing Design Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Using Design Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Netlist Processor Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Analog Expression Language Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Simulation Design Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Using One-to-Many Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Iterated Instances and Bus Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Multiplication Factor (mfactor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Series-Connection Factor (sfactor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

June 2000 2 Product Version 4.4.6


One-to-Many Assignment with the Update Components and Nets Command . . . . . 32Using Many-to-Many or Many-to-One Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Modifying Many-to-Many or Many-to-One Mapping Between Components . . . . . . . . 36Deleting Many-to-Many or Many-to-One Mapping Between Components . . . . . . . . . 36

Using Virtuoso XL Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Using the lxUseCell Property to Specify Layout Devices to Use . . . . . . . . . . . . . . . . 38Using the lvsIgnore Property to Exclude Schematic Symbols . . . . . . . . . . . . . . . . . . 47Using the lxlgnoredParams Property to Exclude Device Properties . . . . . . . . . . . . . 51Using the lxViewList and lxStopList Properties to Prepare Hierarchical Designs . . . 51

4

Preparing Instances and Pins in Your Layout for the Vir tuoso Layout Accelerator

55

Preparing Pins for the Virtuoso Layout Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Preparing Pins for Permutability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Search Order Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Setting the permuteRule Property in the Symbol Master . . . . . . . . . . . . . . . . . . . . . . 62Setting the permuteRule Property in the Device Master . . . . . . . . . . . . . . . . . . . . . . 65Setting the permuteRule Property in the Symbol Instance . . . . . . . . . . . . . . . . . . . . 69Setting the permuteRule Property in the Device Instance . . . . . . . . . . . . . . . . . . . . . 72Setting the permuteRule Property in the CDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Preparing Instances for Hierarchical Connectivity Checking . . . . . . . . . . . . . . . . . . . . . . 80

5

Setting Up Y our Vir tuoso La yout Accelerator En vir onment . . . . . . . . . . . . . . . . . . 82

Setting Up Your Desktop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Customizing Your Desktop Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Using Multiple Cellviews . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Printing to the CIW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Changing Display Colors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Using Bindkeys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Displaying Bindkeys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89



Loading Virtuoso XL Bindkeys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Setting Environment Variablesin the Layout XL Options Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Working with Virtuoso XL Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Information About Online Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Layout XL Options Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

6

Setting Up De vice Ab utment f or Vir tuoso Layout Accelerator . . . . . . . . . . . . . . 111

Introduction to Abutment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Abutment Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Setting Up Cells for Abutment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

abutAccessDir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117abutClass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Steps in Auto-Abutment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118Sample Parameterized Cells Set Up for Abutment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Creating CMOS Pcells to Use with Abutment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125Setting Environment Variables for Abutment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Move Together . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130Constraint Assisted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Using Device Abutment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

7

Generating Y our La yout with Vir tuoso La yout Accelerator . . . . . . . . . . . . . . . . . 133

Starting Virtuoso XL from the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Importing a Netlist for a Connectivity Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Mapping File Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138Starting Virtuoso XL from the Layout View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140Defining the Design Boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143Working with Layout Generation Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Creating Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145Saving and Loading Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146



Modifying Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146Loading Template Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146Saving Template Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148Layout Generation Template File Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151General Syntax Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151Boundaries Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154I/O Pins Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155Sample Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Generating a Layout with Components Not Placed(Gen From Source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160Placing Components in a Layout in the Same Relative Position as in the Schematic (Placefrom Schematic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169Moving Components from the Schematic into the Layout (Pick from Schematic) . . . . . 170

Placing a Group of Schematic Elements Together . . . . . . . . . . . . . . . . . . . . . . . . . . 171Placing Individual Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Abutting Devices Using Pick from Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177Cloning Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181Cloning Using Multiple Cellviews . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184Using Correspondence Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Information About Online Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189Add Correspondence Pairs Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190Cloning Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191Correspondence Pairs Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192Define Connectivity Reference Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193Display Specific Correspondence Components Form . . . . . . . . . . . . . . . . . . . . . . . 194Import XL Netlist Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195Layout Generation Options Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196Load Template File Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199Pick from Schematic Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200Remove Correspondence Components Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203Save Template File Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204Set Pin Label Text Style Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205Startup Option Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206



8

Editing Y our La yout with Vir tuoso La yout Accelerator . . . . . . . . . . . . . . . . . . . . . 207

Identifying Incomplete Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209Moving Objects Manually in the Virtuoso Layout Accelerator . . . . . . . . . . . . . . . . . . . . 213

Moving Objects Using Move Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213Setting the Move Form to Appear Automatically . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Aligning Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217Swapping Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219Permuting Component Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Permuting Pins Manually . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222Checking Permutation Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Using Device Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223Using Automatic Spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225Using Interactive Device Abutment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227Setting Component Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

About Component Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228MOS Transistor Stacking and Folding Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 228Defining Component Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229Modifying a Component Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Using Transistor Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233Using Transistor Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236Adding Instances to a Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240Adding Pins to a Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241Assigning Pins to a Net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243Maintaining Connectivity When Editing a Flattened Pcell . . . . . . . . . . . . . . . . . . . . . . . 245Information About Online Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Assign Nets Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247Edit Component Types Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248Move Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250Set Transistor Folding Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251Show Incomplete Nets Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252Stretch Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254Virtuoso XL Alignment Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255



9

Stretc hing P arameteriz ed Cells in Vir tuoso XL . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257Stretching a Contact Array in a Pcell Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Stretching Using Area Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259Stretching Using Point Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Stretching Multiple Handles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262Selecting a Handle Assigned to Multiple Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 264Setting Environment Variables for Stretchable Pcells . . . . . . . . . . . . . . . . . . . . . . . . . . 265Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

10

Using the Vir tuoso Custom Placer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267Place Menu Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268Other Commands Used with the Virtuoso custom placer . . . . . . . . . . . . . . . . . . . . . 268Placement Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Setting Up the Virtuoso Layout Accelerator for Placement . . . . . . . . . . . . . . . . . . . . . . 270Identifying the Placement Translation Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271Setting Cadence Design Framework II Environment Variables . . . . . . . . . . . . . . . . 271Setting Environment Variables for the Router and Placer . . . . . . . . . . . . . . . . . . . . 272Setting MOS Chaining and Folding Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273Defining the Boundary Layer (Placement Region) . . . . . . . . . . . . . . . . . . . . . . . . . . 276Using Auto-Abutment During Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Placement Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276Types of Placement Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Placement Parameters and Component Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279Defining Component Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280MOS Transistor Chaining and Folding Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 280Defining Components Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

Pin Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283Assigning Pins to an Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284Assigning Pins to a Fixed Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287



Assigning Spacing Between Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288Setting the Placement Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

Component-Assisted MOS Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289User-Defined Row-Based Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300Choose Component Types Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Running the Placer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307Prerequisites to Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308Running the Placer: Initial Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308Troubleshooting Placement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310Refining Placement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311Running the Placer: Detailed Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

Showing Congestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312Information About Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Auto Placer Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314Choose Component Types Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316Pin Placement Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317Placement Style Form (Component-Assisted Placement) . . . . . . . . . . . . . . . . . . . . 319Placement Style Form (User-Defined Placement) . . . . . . . . . . . . . . . . . . . . . . . . . 322

11

Preparing Y our Design f or Routing in the Vir tuoso La yout Accelerator . . . . . . 324

Understanding Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325Selecting Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328Connecting Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Creating Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330Connecting Nets with Path Stitching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332Connecting Nets with Design Shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

Checking Connectivity with Flight Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335Checking Connectivity with Markers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

Finding Markers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335Explaining Markers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336Deleting Single Markers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337Deleting All Markers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337



Defining Physical Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338Using the Virtuoso Compactor on a Routed Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

12

Creating Multipar t Paths in Vir tuoso XL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

About Creating Multipart Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346About Creating a Multipart Path in a Layout Window . . . . . . . . . . . . . . . . . . . . . . . . 347About Saving a Multipart Path as a Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

Flow for Creating Multipart Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349Defining the Master Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350Defining Connectivity for the Master Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354Adding a New Subpart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357Defining Connectivity for a Subpart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370Editing a Subpart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372Deleting a Subpart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374Creating a Multipart Path in a Cellview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377Saving Multipart Path Values as a Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

Example: Creating a Guard Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380Example of an MPP Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390Setting the mppTemplate Environment Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

Checking the Value of mppTemplate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392Changing the Value of mppTemplate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

Create Multipart Path Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394Create Multipart Path – Master Path Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394ROD Subpart Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

13

Checking Design Data in the Vir tuoso La yout Accelerator . . . . . . . . . . . . . . . . . 408

Finding Design Elements (Probing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409Probing Hierarchical Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412Removing Probes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415Exiting the Probe Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415Showing the Options Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415



Checking Shorts and Opens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416Comparing Design Elements and Parameters (Checking against the Connectivity Source)416Information About Online Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

Probe Options Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

14

Updating Design Data in Vir tuoso XL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

Updating Components and Nets(ECO Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421Updating Layout Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427Updating Schematic Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429Updating Device Correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431Updating the Connectivity Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433Changing the Device (Instance) View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434Information About Online Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

Change Instance View Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436Change Inst View Device List Form/Update Layout Device List Form/Update Schematic Device List Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

15

Troub leshooting Pr ob lems in the Vir tuoso La yout Accelerator . . . . . . . . . . . . . 438

Problems with the Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440Invalid Markers from Previous Software Versions . . . . . . . . . . . . . . . . . . . . . . . . . . 440Options Form Does Not Appear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441Virtuoso XL Commands Disappear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441Virtuoso XL Performance Is Slow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

Problems with Editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443Components Move Slowly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443Extra Probes Appear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443Layout Generation Options Form Does Not Keep Values from the Last Entry . . . . . 443Parameters Not Updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443Schematic Not Editable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443Warning to Update Your Design Appears at Startup . . . . . . . . . . . . . . . . . . . . . . . . 444



Problems with Stretching Parameterized Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445Pcell Stretch Handles Are Not Visible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445Difficulty Selecting Pcell Stretch Handles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446Difficulty Stretching Pcell Handles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446Cannot See Objects Inside Pcell During Stretch . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

Problems with Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448Connections Not Made . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448Incomplete Nets Command Does Not Recognize Connected Pins and Nets . . . . . 448Markers for Nonexistent Overlaps and Shorts Appear . . . . . . . . . . . . . . . . . . . . . . . 448Path Ends Not Accepted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449Placement and Routing Do Not Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449Virtuoso XL Does Not Recognize Physical Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

A

Vir tuoso XL Command Quic k Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451



Preface

This document is for developers and designers of integrated circuits. It contains informationabout how to use the Virtuoso® layout accelerator (Virtuoso XL).

The Preface discusses the following:

■ Related Documents

■ Typographic and Syntax Conventions


Virtuoso Layout Accelerator User GuidePreface

Related Documents

The following documents give you more information about related tools and the Cadence®

SKILL language.

■ For information about how to install the product, refer to Cadence Installation Guide.

■ For information about library structure, the cds.lib configuration file, or name mappingfor data shared across multiple Cadence tools, refer to the Cadence ApplicationInfrastructure User Guide.

■ For information about how to perform design tasks with the Virtuoso layout editor, referto the Virtuoso Layout Editor User Guide.

■ For information about how to access the technology file using SKILL, refer to theTechnology File and Display Resource File SKILL Reference Manual.

■ For information about SKILL functions, refer to the Custom Layout SKILL FunctionsReference Manual.

■ For information about database SKILL functions, including the data access functions,refer to the Design Framework II SKILL Functions Reference Manual.

■ For information about creating parameterized cells using the graphic user interface orlow-level SKILL functions, refer to the Virtuoso Parameterized Cell Reference.

■ For a tutorial on creating parameterized cells using the graphic user interface, refer to theCell Design Tutorial.

■ For information about using relative object design (ROD) functions, refer to the RelativeObject Design User Guide.

■ To learn about using the Virtuoso layout synthesizer (LAS), refer to theVirtuoso Layout Synthesizer User Guide and the Virtuoso Layout SynthesizerTutorial.

■ For intormation on using inherited connections and net expressions with variousCadence tools in the design flow refer to Inherited Connections Flow Guide .

■ For a description on connectivity and naming conventions for inherited connections andhow to add and edit net expressions in a schematic or symbol cellview refer to VirtuosoSchematic Composer User Guide .

■ For information about streaming mask data, refer to the Design Data Translator’sReference.


Virtuoso Layout Accelerator User GuidePreface

Typographic and Syntax Conventions

The syntax conventions used in this documentation are described below.

literal Words in nonitalic monospaced type indicate text you must typeexactly as it is presented. These words represent command(function or routine) or option names.

argument... Words in italic monospaced type indicate text that you mustreplace with an appropriate argument or other data, such as apath. The three dots indicate that you can repeat the argument.Substitute one or more names or values.

italic Words in italics indicate names of manuals, commands, andform buttons, form fields, and other features of the user interface(UI).

| The vertical bar (OR-bar) separates possible choices for a singleargument and takes precedence over any other character. Alsoseparates the values returned by a SKILL function.

[ ] Brackets indicate and enclose optional arguments.

{ } Braces indicate you must specify one of the enclosedarguments.



1Introduction to the Virtuoso LayoutAccelerator

The Virtuoso® layout accelerator (Virtuoso XL) is a connectivity-based editing tool thatautomates each stage of the design task, from component generation through automatic/interactive routing. When used as part of an automated custom physical design methodology,Virtuoso XL lets you generate custom layouts from schematics or netlists and edit layouts thathave defined connectivity.

Virtuoso XL continuously monitors connections of components in the layout and comparesthem with connections in the schematic. You can use Virtuoso XL to view incomplete nets,shorts, invalid connections, and overlaps to help you wire your design. It lets you both speedup and customize the layout process.

The following chapters contain information on these design topics:

■ Editing Your Technology File for Virtuoso XL

■ Preparing Your Connectivity Source for Virtuoso XL

■ Preparing Instances and Pins in Your Layout for Virtuoso XL

■ Setting Up Your Virtuoso XL Environment

■ Setting Up Device Abutment in virtuoso XL

■ Generating Your Layout with Virtuoso XL

■ Editing Your Layout with Virtuoso XL

■ Stretching Parameterized Cells in Virtuoso XL

■ Preparing Your Design for Routing in Virtuoso XL

■ Creating Multipart Paths in Virtuoso XL

■ Checking Design Data in Virtuoso XL

■ Updating Design Data in Virtuoso XL


Virtuoso Layout Accelerator User GuideIntroduction to the Virtuoso Layout Accelerator

■ Troubleshooting Problems in Virtuoso XL

For information about Virtuoso XL SKILL functions, refer to the Custom Layout SKILLFunctions Reference Manual.



2Editing Your Technology File for VirtuosoLayout Accelerator

This chapter explains how to edit the technology file for your design so that you can generate,place, and route a layout with the Virtuoso® layout accelerator (Virtuoso XL). This chapterincludes specific information about the elements you need to prepare and discusses thefollowing topics:

■ Sample Technology File on page 17

■ Virtuoso XL Technology File Requirements on page 18

❑ Layer Rules on page 19

❑ Devices on page 20

❑ Physical Rules on page 21

❑ Virtuoso XL Rules (lxRules) on page 22

❑ Compactor Rules on page 24

The Virtuoso layout editor and other Cadence® layout applications require technology-specific information about your design to be stored in a technology file for the design library.You can use Cadence SKILL language functions to query or update the technology file.

For further information about how to create and edit technology files, see the TechnologyFile and Display Resource File User Guide.

The layout editor software includes a sample technology file that you can use or adapt for theneeds of your design.

Sample Technology File

Virtuoso XL includes a sample technology file, mpu.tf that you can use or change to meetthe requirements of each design. The file contains data for a two-layer metal CMOS processand information about Virtuoso XL technology file requirements.


Virtuoso Layout Accelerator User GuideEditing Your Technology File for Virtuoso Layout Accelerator

To see the contents of mpu.tf , type

cd your_install_dir /tools/dfII/samples/techfilemore mpu.tf

where your_install_dir is the directory in which you store the Cadence software.

The mpu.tf technology file covers these areas:

■ Differences between the pre-4.4 versions and the 4.4 and later versions of thetechnology file

■ Layer definitions (layer numbers, purposes, priorities, and connectivity)

■ Symbolic devices (including symbolic contacts)

■ Physical rules, such as spacing rules (including minWidth ) and ordered spacing rules

■ Electrical rules

■ Virtuoso XL-specific rules

■ Other application-specific rules

You must define this information in the technology file of all libraries referenced in your design.

Virtuoso XL Technology File Requirements

The technology file information you need to run Virtuoso XL includes additions to the followingsections of the technology file:

■ Layer information in the Layer Rules class

■ Symbolic contact information in the Devices class

■ Device spacing information in the Physical Rules class

■ Connectivity information in the Virtuoso XL Rules class

■ Compactor information in the Compactor Rules class

Note: If you have information in the Device-Level Editor (DLE) Rules class in your technologyfile, you do not have to rewrite it; the Virtuoso XL software translates dleRules intolxRules .



Layer Rules

In the layerRules class, Virtuoso XL requires the equivalentLayers subclass tospecify layers that have equivalent connectivity and the viaLayers subclass to definelayers used for vias and the layers they connect. Virtuoso XL uses this information todetermine short circuits and open circuits.

■ equivalentLayers (called leEquivalent in versions 4.3.4 and earlier) defineslayers that are electrically equivalent.

In the following example, in the equivalentLayers subclass, when the metal1 layertouches the vddmetal1 layer, the two layers form a connection.

layerRules(equivalentLayers( ( metal1 vddmetal1)))

■ viaLayers (called leEquivalent in versions 4.3.4 and earlier) defines layers usedfor vias and the layers they connect.

In the viaLayers subclass, layers must be named in order. In the following example,the layer in the first column (metal1) is the lower layer and the layer in the third column(metal2) is the upper layer.

layerRules(viaLayers( ;(layer1 viaLayer layer2) (metal1 via metal2) (poly1 contact metal1)))

If you have contact and via layers defined as equivalent to theircorresponding interconnect layers, you can flatten contacts or draw newshapes to maintain or create connectivity.

Note: If you use devices from different libraries for your design, the layer and connectivityinformation in the technology file for each library must be compatible.



Devices

In the Devices class, Virtuoso XL requires symbolic contact definitions for instances usedas vias and for path stitching (symContactDevice ).

Devices(symContactDevice(

; (viaName viaLayer viaPurpose layer1 purpose1 layer2 purpose2; w l (row column xPitch yPitch xBias yBias) encL1 encL2 legalReg)

(M2_M1 via drawing metal1 drawing metal2 drawing .6 .6 (1 1 1.8 1.8 center center) .6 .6 _NA_)

)) ; end symContactDevice

You need contact definitions if you want to

■ Place contacts using the Create – Contact command

■ Perform path stitching (which automatically places contacts) using the Create – Pathcommand

■ Perform path stitching with the routing commands

Note: The mpu.tf file has sample contact definitions in the Devices class.



Physical Rules

The Create – Path command requires that in the physicalRules class, theSpacingRules subclass must contain the minWidth parameter, which defines theminimum width of objects and the default width of paths drawn on a particular layer.

physicalRules(

spacingRules(;(rule layer value) (minWidth cont 0.60) ) )

;spacingRules



Virtuoso XL Rules (lxRules)

In the lxRules class, Virtuoso XL requires information about layer purposes using thefollowing subclasses:

■ lxExtractLayers (leConducting in versions 4.3.4 and earlier) definesconducting layers.

■ lxNoOverlapLayers (leOverlap in versions 4.3.4 and earlier) defines layers thatcannot overlap.

Note: In previous releases, the lxRules class was called the dleRules class.

All purposes within a layer are electrically equivalent unless they are defined separately in thelayerRules class.

You must specify layers used for connectivity with lxExtractLayers .In this example, all metal1 drawing layers and metal2 net and metal2 pin layersconnect components. The list for lxExtractLayers must be one line, with no end-of-lineor return characters.

lxRules(

lxExtractLayers(

((metal1 (metal2 pin)(metal2 net))

)

)

You must set lxExtractLayers for a layer before you can set lxNoOverlapLayersand equivalentLayers for that layer.

lxNoOverlapLayers specifies two layers that cannot overlap. In this example, when thepoly layer touches the diff layer, Virtuoso XL reports an error.

lxRules(

lxNoOverlapLayers(

(poly diff)

)

)

Note: If you are working with a hierarchical design, you can set properties on instances atthe lower levels of the design to avoid false overlap and short markers.



The lxBlockOverlapCheck property, defined on a shape, instance, or instance master,tells the extractor not to check whether a nonoverlap layer of this shape or instance istouching a nonoverlap layer at the current cellview level or at different cellview levels

The lxBlockExtractCheck property, defined on a shape only, tells the extractor not tocheck the connectivity between this shape and others it touches.



Compactor Rules

If you plan to use the Virtuoso compactor to compact your Virtuoso XL design, you need toinclude information about layer purposes in the compactorRules class, using the followingsubclasses:

■ compactorLayers defines the layer names and purposes used in the design.

compactorLayers( ; layer usage ; ----- ----- ( diff "diffusion" ) ( poly1 "conduction" ) ( metal1 "conduction" ) ( metal2 "conduction" ) ( metal3 "conduction" ) ( via "via" ) ( via2 "via" ) ( pwell "well" ) ( pimplant "implant" ) ( hardFence "hardFence" ) ( softFence "softFence" ) ( prBoundary "cellBoundary" ) )

■ symWires lists symbolic wires and how the compactor processes them when itcompacts a design.

symWires(

;( name layer [(impLayer impSpacing)] [(default min max)][(legalRegion regionLayer)] [WLM] )

;( ---- ----- --------- ----------- --- --- ------- ----------- ---------- --- )

("poly1" ("poly1" "drawing") nil (.6 nil nil) nil 5.0 )

("pdiff" ("diff" "drawing") (("pimplant" "drawing") .3) (.6 nilnil) ("outside" "pwell") 100.0 )

("ndiff" ("diff" "drawing") nil (.6 nil nil) ("inside" "pwell")100.0 )

("metal1" ("metal1" "drawing") nil (.6 nil nil) nil 0.04 )

("metal2" ("metal2" "drawing") nil (.6 nil nil) nil 0.02 )

("metal3" ("metal3" "drawing") nil (1.2 nil nil) nil 0.02 )

)



■ symRules checks enclosures between objects on different layers and spacing ofobjects on the same layer. The drc functions specify that rules apply only to particulardevices or objects on the same or different nets.

symRules(

; list of rules

drc(("cont" "drawing" "M1_POLY1") ("diff" "drawing" "NTR") (sep <.6))

drc(("cont" "drawing" "M1_POLY1") ("diff" "drawing" "PTR") (sep <.6))

)

) ; end of Compactor Rules

For more information about the compactorRules and symWires subclasses, see thecompactor section of the Technology File and Display Resource File SKILL ReverenceManual.

For more information about using the Virtuoso compactor, see the Virtuoso CompactorReference Manual.



3Preparing Your Connectivity Sourcefor the Virtuoso Layout Accelerator

This chapter explains how to prepare the connectivity source for your design (schematic ornetlist) for generating, placing, and routing a layout with the Virtuoso® layout accelerator(Virtuoso XL). This chapter covers thse topics:

■ Placing Design Elements on page 26

■ Using Design Variables on page 27

■ Using One-to-Many Mapping on page 28

■ Using Many-to-Many or Many-to-One Mapping on page 34

■ Using Virtuoso XL Properties on page 37

❑ Using the lxUseCell Property to Specify Layout Devices to Use on page 38

❑ Using the lvsIgnore Property to Exclude Schematic Symbols on page 47

❑ Using the lxlgnoredParams Property to Exclude Device Properties on page 51

❑ Using the lxViewList and lxStopList Properties to Prepare Hierarchical Designs onpage 51

Placing Design Elements

You can use any schematic to generate a layout with Virtuoso XL. However, the process iseasier if you follow these guidelines when you create your schematic:

■ Place symbols of devices and pins in the schematic approximately where you want themto be in the layout. The Virtuoso XL Create – Place From Schematic command letsyou place layout devices and create pins in positions that correspond to the positions oftheir schematic symbols.

■ Make sure all parameters are useful


Virtuoso Layout Accelerator User GuidePreparing Your Connectivity Source for the Virtuoso Layout Accelerator

■ Use consistent parameter defaults for comparable symbols

Virtuoso XL applies the parameters of the symbols to the layout devices.

Note: When transferring information from the schematic to the layout, Virtuoso XL flattensthe schematic (expands schematic symbols into corresponding devices) if you provide a viewlist or a stop list to show Virtuoso XL which view of the lower-level instances to use.

Virtuoso XL also supports the use of

■ Design variables

■ One-to-many mapping

■ Many-to-many and many-to-one mapping

If you are preparing a hierarchical design, you also need to make sure the symbol view ofeach top-level design element is mapped to the correct layout view of the correspondinglayout element for generating the layout.

Using Design Variables

You can use the following design variables with Virtuoso XL:

■ Netlist Processor (NLP) expressions

■ Analog Expression Language (AEL) expressions

■ Simulation design variables

Netlist Processor Expressions

NLP expressions are properties that specify parameter values. These expressions are usedby the Open Simulation System (OSS) in netlisting.

For more details about using NLP expressions, see the Open Simulation SystemReference Manual.

Analog Expression Language Expressions

AEL expressions, such as iPar and pPar , define the value of a parameter as a function ofother instance parameters or parameters passed from other levels of hierarchy.

If you specify the value of a parameter using an AEL expression, the parameter



■ Must be defined in the component description format (CDF) for the cell of which thesymbol is a view

■ Must be a string for which parseAsNumber and parseAsCEL properties are set toyes

■ Must not have a CDF callback (because the evaluation of the expression does not triggerthe execution of the callback)

If Virtuoso XL detects a parameter value defined with iPar , pPar , or other AEL expressionsnot defined in the CDF, you see a warning in a message box.

For more information about AEL expressions, see “Scope of Parameters” in the AffirmaAnalog Circuit Design Environment User Guide.

Simulation Design Variables

When you use simulation design variables to specify the value of a parameter in the circuit,Virtuoso XL uses the value last saved during the simulation of the circuit as the value for thelayout implementation.

For more information about simulation design variables, see “Design Variables andSimulation” in Chapter 3 of the Affirma Analog Circuit Design Environment User Guide.

Using One-to-Many Mapping

You can implement one-to-many mapping in Virtuoso XL designs using

■ Iterated instances and bus pins

■ The multiplication factor (m-factor)

■ The series-connected factor (s-factor)

■ One-to-Many Assignment with the Update Components and Nets Command

Iterated Instances and Bus Pins

You can use iterated instances and bus pins in a schematic with Virtuoso XL. Use of iteratedinstances enables one-to-many mapping between pins and devices in the schematic andmultiple instances of the pins and devices in the layout.

For example, the figure below shows



■ Bus pin SEL<0:1> in the schematic mapped to bus pins SEL<0> and SEL<1> in thelayout

■ Iterated instance K<0:1> mapped to instances IK(0)|P0, IK(0)|N0, IK(1)|P0, and IK(1)|N0in the layout

Multiplication Factor (mfactor)

The multiplication factor (mfactor ) is a parameter that defines a one-to-many parallelrelationship between a device in a schematic and multiple instances of the device in thelayout.

K

Top-level schematic

SE

L<0>

SE

L<1>

pmos

pmos

IK (0)IP0 IK (0)IN0

IK(1)IN0IK (1)IP0

Layout (showing incomplete nets)

nmos

nmos



The mfactor can be a property on a device. If you want to use m-factor at other levels of

the design, use iterated instances instead of m-factor.

You can implement the mfactor as a CDF parameter or as a property of an instance or acell. As a property of an instance or a cell, it can be a string, an integer, or a floating-pointnumber.

You can use an environment variable, mfactorSplit , to control whether themfactor produces multiple layout devices or not.

You can also add a Boolean property, lxMfactorSplit on a given instance to overridethe global value given by the mfactorSplit environment variable.

Note: You cannot use multiplication factors with components that cannot be used in parallel,such as voltage sources.

Series-Connection Factor (sfactor)

The series-connection factor (sfactor ) is a parameter that can be used to define a one-to-many relationship between a device in a schematic and multiple instances in seriesconnection in the layout. You set the value of the sfactor property (called s or S, unless youchange it in the Layout XL Options form) to the number of layout devices you want togenerate. When you run the Gen from Source or Update Components and Nets

Top-level schematic

Lower-level schematic

Layout (showing incomplete nets)

np

n

np

n

|I0|Q9.2|I0|Q9.1

I0



command, Virtuoso XL generates the number of layout devices specified as the propertyvalue. It creates all the devices identical in size.

Note: In the 4.4.5 release, you can define the sfactor for two-terminal instances only. Findout about this??????

The sfactor can be a property on a device at the top level or on a lower level of your designhierarchy.

You can implement the sfactor as a CDF parameter or as a property of an instance or acell. As a property of an instance or a cell, it can be an integer, a string, a floating-pointnumber, or an expression.

You can use an environment variable, sfactorParam , to tell Virtuoso XL which parameterof the device is to be split. The default names of the parameters to be split are “r R” for resistor,“C c” for capacitor, and “l L” for inductor. You can set this environment variable from the LayoutXL Options form.

Note: If both mfactor and sfactor are defined on the same instance, sfactor is ignored.

net2

net2

|A.s1

s = 3R = 3k

Schematic Layout (showing incomplete nets)

A

net1

R = 1k

R = 1k

R = 1k

net1

|A.s2

|A.s3

|A|.netS2

|A|.netS1

s factor



One-to-Many Assignment with the Update Components and NetsCommand

You can also map a single device in the schematic to multiple devices in the layout by usingthe Update Components and Nets command. You might want to do this if you need to mapa device in the schematic to a flattened layout instance.

Note: You can map One-to-Many devices only between cellview pairs; that is, between theschematic and layout that correspond to each other and are on the same hierarchical level.For example, you cannot map an instance in the one to multiple instances accessed througha descend edit in the other.

To map an instance in the schematic to multiple instances in the layout, follow these steps.

1. From the layout Connectivity menu, choose Update – Device Correspondence.

The schematic window and the Command Interpreter Window (CIW) prompt you tochoose one or more instances from the schematic.

2. Select the component from the schematic.

3. Press Return in the schematic window.

The layout window and the CIW prompt you to choose one or more instances from thelayout window.

You can select more than one device by Shift click or by click and drag. You candeselect using Control click or by Control click and drag. Preselected componentsare considered part of the selection unless you specifically deselect them.

For example, in the diagram below, you can select the resistor A from the schematic tobe mapped to the resistors R21, R22, and R6 in the layout.

4. When you have finished your selection, press Return .

net2

net2

R21R = 8k

Schematic Layout (showing incomplete nets)

A

net1

r = 5kr = 2kr = 1k

net1

R22

R6



Virtuoso XL checks your selection for connectivity. If the number of external nets in thelayout selection is less than the number of external nets in the schematic selection, themapping is not set.

If the number of external nets in the layout selection is the same as or greater than thenumber of external nets in the schematic selection, a dialog box shows the nets that donot match and asks if you want to use Assign Nets to assign the nets of the layoutcomponents to nets corresponding to those in the schematic.

a. Choose Yes.

The Assign Nets function highlights all unmatched nets from the schematic andlayout.

The CIW and layout window prompt you to select a pin within an instance to add toa net.

You can press F3 to see a list of the nets in the design.

b. Click on a pin in one of the instances in the layout that you want to correspond to theinstance in the schematic.

The CIW and layout window prompt you to select a net to add the pin to.

c. Click on a net in the schematic or a path in the layout.

Assign Nets connects the pin to the net.

d. When you have finished assigning nets, click Cancel on the Assign Nets Form orpress Escape to cancel the Assign Nets command.

The Assign Nets command is not canceled and the prompt to select a pin does notdisappear until all the unassigned pins are connected to nets.

The Device Correspondence command checks to see that the components are all inone group.

❑ If they are all in the same group, Virtuoso XL leaves them in the group and the CIWdisplays a message that mapping has been successful.

❑ If only some of them are in a group, Virtuoso XL puts the rest in the group and theCIW displays a message that mapping has been successful.

❑ If none of them is in a group, Virtuoso XL creates a new group and puts them all in.The CIW displays a message that mapping has been successful.

❑ If they are in different groups, the CIW displays a message that mapping cannot beset because they are in different groups.



If Virtuoso XL needs to create a group, the group is called lxMTM. A property calledlxMTM is created and attached to the group in the layout. The property value is the nameof all the selected components from the schematic. All the components selected from thelayout are the members of the group.

Note: More than one group in a layout cellview can be named lxMTM. But a componentcan belong to only one such group.

You can repeat this process to assign all the elements in the “many” group to nets.

5. Press Escape to cancel the Device Correspondence command.

Using Many-to-Many or Many-to-One Mapping

You can map multiple devices in the schematic to one or more devices (including shapes) inthe layout by using the Update Components and Nets command. You might want to do thisif you need to map a symbol or symbols in the schematic to a flattened layout instance.

Note: You can map many-to-many devices only between cellview pairs; that is, between theschematic and layout that correspond to each other and are on the same hierarchical level.For example, you cannot map an instance in the one to multiple instances accessed througha descend edit in the other.

To map multiple symbols in the schematic to one or more instances in the layout, follow thesesteps.

1. From the layout Connectivity menu, choose Update – Device Correspondence.

The schematic window and the Command Interpreter Window (CIW) prompt you tochoose one or more instances from the schematic.

2. Select the components to be mapped from the schematic.



You can select more than one device by Shift click or by click and drag. You candeselect using Control click or by Control click and drag. Preselected componentsare considered part of the selection unless you specifically deselect them.

For example, in the diagram below, you could select the resistors R1and R2, NMOStransistors N1 and N2, and devices X and Y from the schematic to be mapped to thedevices L and M in the layout (many-to-many) or the block MISC in the layout (many-to-one).



The number of external nets in the selected group in the schematic (in the example, NetsA, B, and C) must be the same as the number of external nets in the selected group inthe layout.

The software lets you ignore global nets, such as Vdd and Gnd, in the schematicbecause global nets are not indicated on many schematics. But if a schematic has globalnets, they must be shown in the layout.

4. When you have finished your selection, press Return in the layout window.

If you are assigning many-to-many, the Device Correspondence command checks tosee that the layout components are all in one group.

❑ If they are all in the same group, Virtuoso XL leaves them in the group and the CIWdisplays a message that mapping has been successful.

❑ If only some of them are in a group, Virtuoso XL puts the rest in the group and theCIW displays a message that mapping has been successful.

❑ If none of them is in a group, Virtuoso XL creates a new group and puts them all in.The CIW displays a message that mapping has been successful.

❑ If they are in different groups, the CIW displays a message that mapping cannot beset because they are in different groups.

If Virtuoso XL needs to create a group, the group is called lxMTM. A property calledlxMTM is created and attached to the group in the layout. The property value is the name

Vdd

N1net A net B

N2

R1 R2

Vdd

Gnd

net A

X

YGnd

net1 net2

net3

net C

M

L

net C

net B

Vdd

Gnd

net A

MISC

net C

net B

Schematic Layout (Many-to-Many) Layout (Many-to-One)



of all the selected components from the schematic. All the components selected from thelayout are the members of the group.

Note: More than one group in a layout cellview can be named lxMTM. But a componentcan belong to only one such group.

After the components are checked, the Device Correspondence command creates thenew group.

Modifying Many-to-Many or Many-to-One Mapping Between Components

To modify a mapping between components, follow these steps.

1. From the layout window Connectivity menu, choose Update – DeviceCorrespondence.

The layout window and the CIW prompt you to select one or more instances from theschematic.

2. In the schematic, select one of the components in the group that you want to modify.

All the components in the group are highlighted.

3. To delete some schematic components from or add others to the group, use Controlclick to select those components to add and Shift click to deselect the components tobe deleted.



5. To delete some layout components from or add others to the group, use Control clickto select those components to add and Shift click to deselect the components to bedeleted.

6. Press Return in the layout window.

The new mapping is checked and, if found acceptable, created.

Deleting Many-to-Many or Many-to-One Mapping Between Components

To delete a mapping between components, use the Update – Device Correspondencecommand to set a one-to-one mapping between the components.



To delete a many-to-many (or many-to-one) mapping between components, follow thesesteps.

1. From the layout window Connectivity menu, choose Update – DeviceCorrespondence.

The layout window and the CIW prompt you to select one or more instances from theschematic.

2. In the schematic, select one of the components in the group whose mapping you wantto delete.

All the components in the group are highlighted.

3. Use Shift click to deselect all the components except one.



5. Use Shift click to deselect the components to be deleted except the one you want tomap to the schematic component.

6. Press Return in the layout window.

The many-to-many (or many-to-one) mappings are deleted.

Using Virtuoso XL Properties

Before Virtuoso XL can create a layout from a schematic, you must create a layout device forevery symbol in the schematic. The layout master cell of a device or contact can be a fixedcell, a parameterized cell (pcell), or a device or contact defined in the technology file.

Pcells are often the most effective because you can assign the dimensions of the device atlayout generation and vary the sizes of a contact each time you place the cell.

For more information about pcells, see the Virtuoso Parameterized Cell ReferenceManual.

To tell Virtuoso XL which layout configuration of a schematic symbol to use in a design, youcan

■ Add the lxUseCell property to the symbols of device cells to specify which cell (orlibrary and cell, if a you want to use a cell from different library) to use for the layoutinstance



■ Add or turn on the lvsIgnore , ignore , ignoreNames , or nlAction property onsymbols in the schematic to keep them from being placed in the layout

■ Add the lxIgnoredParams property to block unwanted parameters

■ Add the lxViewList and lxStopList properties to the symbols of device cells inhierarchical designs to specify the layout views to use

Note: The lxIgnoredParams , lxViewList , and lxStopList properties havedefault values that are used when properties are not found. The corresponding environmentvariable names are lxIgnoredParams , viewList , and stopList . Their values are allstrings containing words separated by spaces.

Using the lxUseCell Property to Specify Layout Devices to Use

When a device symbol has more than one layout cell associated with it, you can tell VirtuosoXL which cell to use in generating the layout by setting the lxUseCell property for thesymbol as one of the following:

■ A property of the symbol instance in the schematic

■ A property of the symbol master in the library

■ A component description format (CDF) parameter of the symbol

Virtuoso XL looks for the lxUseCell property in the order listed above.

For digital designs, the cells can be in different libraries.

For mixed-signal designs, you must use a CDF to define the parameters for the devices;therefore, the symbol and layout must be in the same library and cell.

If a symbol does not have an lxUseCell property or the property is not assigned a value,Virtuoso XL defaults to the cell with the same library and cell name as the symbol.

If there is already an instance of the cell with the expected name in the layout, the softwareuses that instance.

Specifying the Layout Device in the Symbol Instance

To specify a layout device in the symbol instance, set the lxUseCell property on a symbolinstance in the schematic. To set a property on a symbol instance, follow these steps.

1. From the schematic window, choose Design – Make Editable to make the designeditable.



2. In the schematic window, click on the symbol to select it.

3. From the schematic window, choose Edit – Properties – Objects.

The Edit Object Properties form appears.

4. Click Add.



The Add Property form appears.

5. Type lxUseCell in the Name field.

6. Set the Type cyclic field to string.

7. Type the name of the layout device to use in the Value field.

8. Click OK.



The lxUseCell property appears in the Edit Object Properties form.

9. Click OK.

Virtuoso XL uses the cell you specified when you generate or reinitialize the layout.

Specifying the Layout Device in the Symbol Master

To specify the layout device in the symbol master, set the lxUseCell property on a symbolinstance in the schematic.

To set a property on a symbol master in the schematic, follow these steps:



1. Open the symbol master of the device.

2. From the schematic window, choose Edit – Properties – Cellview.

The Edit Cellview Properties form appears.

3. In the Property section of the form, click Add. (If the Add option is not visible, click userat the top of the form.)




4. Type lxUseCell in the Name field.


6. Type the layout device name in the Value field.

7. Click OK.

The lxUseCell property appears in the Edit Cellview Properties form.

8. Click OK.

Virtuoso XL uses the layout device you specified for the symbol when you generate orreinitialize the layout.

Specifying the Layout Device in the Device CDF

To specify the layout device in the device CDF, you add the lxUseCell default parameterto the device CDF.

To add a default parameter to the device CDF, follow these steps.



1. In the Command Interpreter Window (CIW), choose Tools – CDF – Edit.

The Edit Component CDF form appears.

2. In the Library Name field, type the library name.

3. In the Cell Name field, type the cell name.

Note: Do not click OK or Apply or press Enter : these actions cause the form todisappear.



The Edit Component CDF form expands to include information about the device.

4. Click Add.

Component Parameters sectionAdd button

lib1



The Add CDF Parameter form appears.

5. Set the paramType cyclic field to string.

6. In the name field, type lxUseCell .

7. In the defValue field, type the name of the layout device you want to use.

8. Click OK.

defValue field



The lxUseCell property appears in the Edit Component CDF form.

9. Click OK.

The system adds the lxUseCell parameter to the component.

For more information about CDFs, see the Component Description Format User Guide.

Using the lvsIgnore Property to Exclude Schematic Symbols

If you do not want the corresponding layout device for a symbol in the schematic to appear inthe layout, you can exclude these symbols by setting the lvsIgnore , ignore , ornlAction property for the symbol. You can also set the lvsIgnore property for layoutdevices if you do not want Virtuoso XL to check them.




2. In the schematic window, click on the symbol to select it.

3. From the schematic window, choose Edit – Properties – Objects.


4. Click Add.




5. In the Name field, type lvsIgnore .

6. Set the Type cyclic field to boolean.

The Choices field disappears from the Add Property form.

7. Turn on Value and click OK.



The lvsIgnore property appears in the Edit Object Properties form.

8. Click OK.

Virtuoso XL does not place the schematic symbol in the layout and does not highlight it asa missing device or as part of an incomplete net. Analog layout versus schematic (LVS)checking does not use symbols with lvsIgnore set to on.

Note: You can use the Virtuoso XL Layout Options form to set the ignore Namesenvironment variable to define other properties to use as ignore properties.

Note: A schematic device that has the string property nlAction with a value of ignorebehaves the same as one with an lvsIgnore or ignore property.



Using the lxlgnoredParams Property to Exclude Device Properties

Virtuoso XL maintains in the layout the value of parameters and the properties of devices inthe schematic.

If there are devices in your schematic with properties that you do not want to be checkedwhen you use the Connectivity – Check – Against Source command or transferred to thelayout when you use the Connectivity – Update – Layout Parameters command, specifythose device parameters to be excluded using the lxIgnoredParams property.

You can also set this property on layout components that are the same except for theirparameters, so that the differing paramters are ignored by the cloning functionality.

The lxIgnoredParams property has the type string and takes as its values the names ofthe properties that you want Virtuoso XL to ignore.

You can define the lxIgnoredParams property as

■ A property of the symbol instance in the schematic(add the property to the symbol just as you do the lxUseCell property)

■ A property of the symbol master in the library(add the property to the master just as you do the lxUseCell property)

■ A property of the device instance in the layout(add the property to the instance just as you do the PermuteRule property)

■ A component description format (CDF) using the Command Interpreter Window (CIW)Tools – CDF – Edit command (add lxlgnoredParams as a CDF parameter just asyou do the lxUseCell property using the names of the properties you want to ignoreas the defValue )

Using the lxViewList and lxStopList Properties to Prepare HierarchicalDesigns

To prepare a hierarchical design for use with Virtuoso XL, you must make sure the symbol foreach top-level design element is mapped to the correct lower-level design element for layoutgeneration.

To map one cell to another cell,

■ You can add the lxUseCell property to an instance of a cell, or you can add thelxUseCell property as a CDF parameter to a cell



■ You can use the lxViewList and lxStopList properties to specify which layout viewto use

❑ The lxViewList property creates a switch view list that tells Virtuoso XL whereto look for the view name of a cell on the lower levels of a hierarchical design. Thedefault value is schematic netlist symbol layout compactedsymbolic .

❑ The lxStopList property creates a stop view list that tells Virtuoso XL where tostop looking; that is, it identifies the view with the most detailed description or theone with no further layers of hierarchy as the stop view. The default value islayout compacted symbolic .

For a more detailed explanation of hierarchy expansion using the lxStopList andlxViewList properties, see “How the Netlister Expands Hierarchy” in Chapter 3 of theAffirma Analog Circuit Design Environment User Guide.

Note: In releases 4.3.4 and earlier, the maskLayoutViewName property specified whichview to use in the layout. Virtuoso XL still recognizes this property if you have not defined thelxStopList property.

Setting the lxViewList and lxStopList Properties

You define the lxViewList and lxStopList properties just as you define thelxUseCell or any other property:

■ As a property of the symbol instance in the schematic

■ As a property of the symbol master in the library

■ As a property of the device instance in the layout

■ As a component description format (CDF) parameter of the layout device

After generating a layout, you can change the view using the layout window Connectivity –Change Instance View command. The Change Instance View form lets you choose a viewfrom the list defined in the lxStopList property.

Note: You cannot use Virtuoso XL while you are viewing a lower level of a hierarchicaldesign. The Virtuoso XL menus disappear from the layout window when you descend into ahierarchical design and reappear when you return to the top level.

The following figure represents the schematic hierarchy and shows which layout viewsVirtuoso XL chooses under these conditions:

■ lxStopList is set to layout layoutS



■ lxViewList is set to schematic cmos.sch

The chosen layout views are shown with thick-line boxes.

In this figure, as Virtuoso XL builds the layout, it looks at each symbol in the Top Cell.

The Mux cell has no view listed in the stop list; therefore, Virtuoso XL goes to the view list andswitches into the Mux schematic. All devices in the Mux schematic have views that are in thestop list; therefore, Virtuoso XL places those views.

The AND cell has a view listed in the stop list; therefore, Virtuoso XL places that view andnever switches into the view list.

Overriding the stopList Property

If you want to descend into a device through a particular instance where the master has thelxStopList property defined, but you want to go a level further down, you can set thevalue of the lxStopList property to an empty string (“ ”).

The software then continues to descend to the next level. The next level does not inherit thisvalue, so the software stops there unless you set the value of the lxStopList property toan empty string on that level as well.

schematic

Top Cell

layoutAND

cmos.schschematic

Mux

symbolsymbol

layoutS

PMOS

symbol

layout

PMOSNMOS

symbol

layout

symbol

layout

symbol

layout

PMOS

symbol

layout

PMOSNMOS

symbol

layout

symbol

layout

symbol

layout

NMOS NMOS

chosen layout view



The figure below shows the views the software chooses if you use the empty string (“ ”) valueon a view. The chosen layout views are shown with thick-line boxes.

This time, the software first stops at the AND cell that has a view listed in the stop list, but theview has the lxStopList property set to the empty string (“ ”), so the software does notstop there and descends into the views in the level below and stops at the next views that arelisted in the stop list.

For a more detailed explanation of hierarchy expansion using the lxStopList andlxViewList properties, see “How the Netlister Expands Hierarchy” in Chapter 3 of theAffirma Analog Circuit Design Environment User Guide.

schematic

Top Cell

layoutAND

cmos.schschematic

Mux

symbolsymbol

layoutS property=lxStopList value=" "

PMOS

symbol

PMOSNMOS

symbol symbol symbol

PMOS

symbol

layout

PMOSNMOS

symbol

layout

symbol

layout

symbol

layout

NMOS NMOS

layoutSlayoutSlayoutSlayoutS

chosen layout view



4Preparing Instances and Pins in YourLayout for the Virtuoso LayoutAccelerator

This chapter explains how to prepare layout elements for use with the Virtuoso® layoutaccelerator (Virtuoso XL). This chapter covers the following topics:

■ Preparing Pins for the Virtuoso Layout Accelerator on page 57

■ Preparing Pins for Permutability on page 57

■ Preparing Instances for Hierarchical Connectivity Checking on page 80

You can also define pins to be connected externally to the design.

Note: The layout window Connectivity commands let you tell the software to connect pinsin four different ways:

Define Pins – Must Connect lets you connect selected pins in a net externally at ahigher level of the hierarchy.

Define Pins – Strongly Connected lets you connect selected pins within the device.By default, pins are connected internally (strongly).

Define Pins – Weakly Connected lets you connect selected pins in a limited externalconnection to avoid specific internal connections (typically ones with high-resistancepaths). lxHiSetOptions

Define Pins - Pseudo Parallel Connect lets you connect selected instance terminalson the same net within an instance as though they were connected externally; that is,they are defined as a connection but do not ever need to be physically connected.

For more information about must-connect pins, strongly connected pins, weakly connectedpins, and pseudo-parallel connected pins, see “Defining Pin Connections.” in Chapter 12 ofthe Virtuoso Layout Editor User Guide.


Virtuoso Layout Accelerator User GuidePreparing Instances and Pins in Your Layout for the Virtuoso Layout Accelerator

If you are using parameterized cells (pcells) and want to give them the capability for abutment(overlapping pins to create a connection), see Chapter 6, “Setting Up Device Abutment.”



Preparing Pins for the Virtuoso Layout Accelerator

For connectivity assignment tracing and cross-probing to work correctly in Virtuoso XL, thepins and pin names in the layout cellview of a device must match those in the correspondingschematic symbol.

If there are extra pins in the symbol, Virtuoso XL does not maintain their connectivity in thelayout. If you add extra pins, whose names are global nets (for example, vdd!) to the layout,Virtuoso XL does maintain connectivity of these pins in the layout.

In addition, Virtuoso XL maintains connectivity of extra pins in the layout whose connectivityis defined via inherited connections. The inherited connection can be defined relative to thelayout instance itself or relative to the schematic hierarchy that ends with the schematicinstance corresponding to that layout instance.

Note: Do not place pins where you do not want to make a connection; for example, on a polylayer that covers the gate area of a FET.

If there are pins in the schematic that you do not want to show up in the layout, you can assignthe ignoreNamesproperty to it.

Preparing Pins for Permutability

If you want to make the instance pins or terminals of a device permutable (exchangeable),you must define the permuteRule property for the device.

cdsTerm(C)

cdsTerm(E)

cdsTerm(B)

CBE

G

G

D S

gnd!

analoglib library style pin layout basic library style pin layout

analoglib library style pin symbol basic library style pin symbol

G

G

D S



You can define the permuteRule property as

■ A property of the symbol master cellview in the schematic

■ A property of the device master cellview in the layout

■ A property of the symbol instance in the schematic

■ A property of the device instance in the layout

■ A component description format (CDF) parameter of the device cell

If you define the permuteRule property on a schematic symbol, that setting overrides anyother rule defined in the layout for that instance.

All pins that are not listed in the permuteRule property for a device are fixed (notpermutable) by default.

You can set an environment variable, CDS_Netlisting_Mode , to specify the order inwhich the software looks for the permuteRule property.

The Auto Permute Pins option in the Layout XL Options form must be active for Virtuoso XLto permute pins automatically. Virtuoso XL lets you permute pins manually when the AutoPermute Pins option is not active.

Search Order Variable

To specify the order in which the software looks for the permuteRule property, you can setan environment variable, CDS_Netlisting_Mode ,in your .cshrc file or .cdsenv file.

Setting Search Order

setenv CDS_Netlisting_Mode Analog device CDF only

setenv CDS_Netlisting_Mode Digital 1. instance2. master cellview3. LVS cellview

setenv CDS_Netlisting_ModeCompatibility

1. device CDF2. instance3. master cellview4. LVS cellview



If the environment variable CDS_Netlisting_Mode does not exist, the value defaults toDigital .

Note: The value (Analog , Digital , or Compatibility ) must be written with a capitalletter.

Virtuoso XL checks for the permuteRule property in a way similar to the way the Assura™Diva® verification tools check for this property. However, these tools check permutability rulesonly in the Layout Versus Schematic (LVS) cellview and in the CDF, while Virtuoso XL checkspermutability rules in the symbol cellview and in the layout instance and master cellviews, aswell as the LVS cellview and the CDF.

In case of conflict between rules and pins, the rule is ignored and no pin permutation isallowed.

Syntax

The syntax for the permuteRule property is the same as is used in the Assura Divaverification tools. Two keywords used in the property are p, for permutable, and f, for fixed. Forexample, the property contents

(p 1 2)

defines pins 1 and 2 as permutable, and any other pins as fixed.

For example, in the multi-emitter BJT shown here,

pins E1, E2, and E3 are permutable; therefore you define the property permuteRule as

(p E1 E2 E3)

You can define permutable pins hierarchically. For example, the property contents

E1 E2 E3

B

C E1 E2 E3

B

C



(p (p 1 2) (p 3 4))

defines pin sets 1,2 and 3,4 as permutable pins and defines the two sets to be permutablewith each other.

Permutable sets can be defined as in this example:

(p (p A B C) (p D E F))

The property contents

(f (p 1 2) (p 3 4))

defines two permutable pin sets as not permutable with each other.

D

EF

A

B

C



Macros

To avoid entering long lists of permutable pins for the permuteRule property, you can usethe following macro notations:

■ ALL, to indicate all the pins in the cell

(f ALL)

(p ALL)

■ Range indications, where pins are numbered or sorted as in bus notations

(f A<0:12> (p A<13> A<14>) A<15:16>)

The notation

(p A<0:3> B<4:7>)

is equivalent to

(p A<0> A<1> A<2> A<3> B<4> B<5> B<6> B<7>)

and states the equivalence of all pins to each other.

The notation

(p (f A<0:3>) (f B<4:7>))

states the equivalence between two sets of nonpermutable pins

A<0:3> and B<4:7>

You can also express range indications in descending order

(p A<3:0> B<7:4>)



Setting the permuteRule Property in the Symbol Master

To set a property on the symbol master cellview, follow these steps.


2. Choose Edit – Properties – Cellview.


3. Click Add.




4. In the Name field, type permuteRule .


6. In the Value field, type the syntax indicating the permutability you want.

7. Click OK.



The permuteRule property appears in the Edit Cellview Properties form.

8. Click OK.

After you generate or reinitialize the layout, Virtuoso XL uses the permutability of the pinsyou indicated.



Setting the permuteRule Property in the Device Master

To set a property on the master cellview of a device, follow these steps.

1. From the layout window showing the device master, choose Design – Properties.


2. Turn on Property at the top of the form.



The form changes to display properties.

3. Click Add.






6. In the Value field, type the syntax indicating the permutability you want.

7. Click OK.



The permuteRule property appears in the Edit Cellview Properties form.

8. Click OK.

After you generate or reinitialize the layout, Virtuoso XL uses the permutability of the pinsyou indicated.



Setting the permuteRule Property in the Symbol Instance

To set a property on a symbol instance in the schematic, follow these steps.


2. Click on the symbol to select it.

3. Choose Edit – Properties – Objects.


4. Click Add.






7. In the Value field, type the syntax for the permutation you want.

8. Click OK.



The permuteRule property appears in the Edit Object Properties form.

9. Click Apply.

Virtuoso XL uses the permutation that you specified (even if you regenerate or reinitializethe layout).



Setting the permuteRule Property in the Device Instance

To set a property on a device instance in the layout, follow these steps.

1. In the layout window, click on the instance to select it.

2. Choose Edit – Properties.

The Edit Instance Properties form appears.

3. Turn on Property at the top of the form.

|R17



The form changes to show properties.

4. Click Add.






7. In the Value field, type the syntax for the pins to be permuted.

8. Click OK.



The permuteRule property appears in the Edit Instance Properties form.

9. Click Apply.

Virtuoso XL uses the permutability that you specified (unless you regenerate orreinitialize the layout).



Setting the permuteRule Property in the CDF

For more information about CDFs, see the Component Description Format User Guide.

To add a default parameter to the device CDF, follow these steps.

1. In the Command Interpreter Window (CIW), choose Tools – CDF – Edit.

The Edit Component CDF form appears.

Note: Do not press the Return key after typing information in a field in this form; it causesthe form to close.

2. In the Library Name field, type the library name.

3. In the Cell Name field, type the cell name.

4. Move the cursor out of the form or press Tab.



The Edit Component CDF form expands to include information about the device.



5. Scroll down to the Simulation Information section of the form.

6. In the Simulation Information section of the form, click Edit.

Edit button



The Edit Simulation Information form appears.

7. From the Choose Simulator cyclic field, choose auLVS.

8. In the permuteRule field, type the syntax that defines the pins you want to permute.

9. Click OK.

10. On the Edit Component CDF form, click OK.

The system adds the permuteRule parameter to the component.

Syntax(p 1 2)

1 2



Preparing Instances for Hierarchical ConnectivityChecking

When you are working with a hierarchical design and want to check connectivityhierarchically, by setting the Extract Connectivity to Level value on the LayoutXL Options form or in a setup file using the extractStopLevel environment variable, youneed to set extra properties on instances at the lower levels of the design to avoid falseoverlap and short markers. Instances at the lower levels of the design need to haveconnectivity information already assigned or need to be opened in Virtuoso XL for theconnectivity checking to work.

The lxBlockOverlapCheck property, defined on a shape, instance, or instance master,tells the extractor not to check whether a nonoverlap layer of this shape or instance istouching a nonoverlap layer at the current cellview level or at different cellview levels.

In the illustration above, the lxBlockOverlapCheck property can be defined on thediffusion layer so that no short marker will be created.

The lxBlockExtractCheck property, defined on a shape only, tells the extractor not tocheck the connectivity between this shape and others it touches.

In the illustration above, the layer that crosses net1 and net2 has the propertylxBlockExtractCheck , so there is no connectivity checking between this shape and allothers it touches.

G

G

DSdiffusion

poly

A: extra layer by mistake

net1 net2

le_ex_#

metal1This shape crosses net1 and net2



If the shape does not already have connectivity, the software assigns anle_ex_# net name to it.

If you assign connectivity to the shape manually or with Cadence® SKILL code, it will keepthe connectivity, but the shape will always be considered incomplete because the softwarewill not check it when checking the connectivity.

For hierarchical connectivity to work for pcells, the connectivity must be defined on theshapes within the pcell. You can assign connectivity interactively using the Connectivity –Assign Nets command or using SKILL functions.



5Setting Up Your Virtuoso LayoutAccelerator Environment

This chapter explains how to set up your Virtuoso® layout accelerator (Virtuoso XL) designenvironment to suit your preferences and work habits. You can use design variables tochange the value of many aspects of your design environment either for an individual designsession or permanently (until you change the value of a variable). This chapter discusses thefollowing topics:

■ Setting Up Your Desktop on page 83

❑ Customizing Your Desktop Layout on page 83

❑ Using Multiple Cellviews on page 84

❑ Printing to the CIW on page 84

■ Changing Display Colors on page 85

■ Using Bindkeys on page 89

❑ Displaying Bindkeys on page 89

❑ Loading Virtuoso XL Bindkeys on page 89

■ Setting Environment Variables in the Layout XL Options Form on page 91

■ Working with Virtuoso XL Environment Variables on page 96

■ Setting Environment Variables on page 107

Information about Virtuoso XL online forms is at the end of the chapter.


Virtuoso Layout Accelerator User GuideSetting Up Your Virtuoso Layout Accelerator Environment

Setting Up Your Desktop

After you start Virtuoso XL, you see “Virtuoso® XL Layout...” in the banner above the layoutwindow (on the right) and you see a schematic window (on the left) that corresponds to thelayout window. This is the default configuration.

You can move, resize, and iconify the Command Interpreter Window (CIW), schematicwindow, Layer Selection Window (LSW), and layout window to suit your needs.

Customizing Your Desktop Layout

You can save and reuse your window environment the way you have customized it by

■ Using the CIW Options – Save Defaults command

■ Adding the appropriate environment variables to your .cdsenv file, as in the examplebelow.

When you use the CIW Options – Save Defaults command to save the size and position ofthe schematic and layout windows as you have customized them, Virtuoso XL saves this

Schematicview

Layoutview

LSW

CIW

as

Virtuoso ® Schematic Editing: lib2 amp schematic Virtuoso ® XL Layout Editing: lib2 amp schematicLSW



environment information to the layout cellview as a property. When you open the layout andschematic cellviews the next time, they appear in the same configuration as they had whenyou saved them.The command sends the LSW and the CIW window size and location information to the.cdsenv file.

To prevent Virtuoso XL from rearranging or resizing windows from the way you have arrangedthem, add the following line to the .cdsenv file:

layoutXL autoArrange boolean nil

Note: If you save your current window positions and form settings to a file other than.cdsenv (for example, .envFileName ), you can recall them by typing the following in theCIW or in your .cdsinit file:

envLoadFile("layoutXL" ".envFileName")

Using Multiple Cellviews

If you open multiple cellviews in Virtuoso XL, the second and subsequent sets of windows arenot automatically configured the way the first set is.

You can open more than one schematic-layout pair of windows in Virtuoso XL and work oneach pair independently. If you open a schematic and two copies of the same layout, theVirtuoso XL Connectivity – Check, Connectivity – Probe, and Connectivity – Updatecommands apply to both layouts.

If you have a schematic and two different layouts open, the Virtuoso XL Connectivity –Check, Connectivity – Probe, and Connectivity – Update commands apply to only thelayout from which you selected the command.

Printing to the CIW

To instruct Virtuoso XL to print process information to the CIW, not to a separate Virtuoso XLInfo window, type the following command in the CIW or store it in your .cdsenv file:

layoutXL infoWindow boolean nil



Changing Display Colors

You can change the colors and characteristics of the entry layers that Virtuoso XL commandsuse for display purposes. You can change the display layers Virtuoso XL uses for the followingcommands:

■ The Show Incomplete Nets command uses the y0 – y9 entry layers to show flightlines

■ The Connectivity – Check – Against Source command uses the hilite drawing9entry layer to identify missing devices

■ The Connectivity – Probe command uses the hilite drawing through hilite drawing9entry layers to probe pins, nets, and devices

■ The Highlight command for placement constraints uses the annotate drawing3 entrylayer to highlight in the layout the components bound by a placement constraint

■ The Pick from Schematic command uses the hilite drawing1 layer to highlightschematic symbols

You can edit these layers from the window opened by the CIW Tools – Display Resources– Editor command.

Note: Although it is possible to edit these layers from the LSW, it is not recommended. To doso, you must add these layers to the LSW as valid layers. Valid layers are those you use forcreating layout shapes.

To change the colors using the Display Resources Editor, follow these steps.

1. In the CIW, choose Tools – Display Resources – Editor.



The Display Resource Editor window appears.

2. Turn on All, so that you can see all of the available layers (not just the ones you havedefined as drawing layers).

3. In the Layers column, choose the name of the layer to change.

4. Turn on the Fill Style, Fill Color, Outline Color, Stipple, and Line Style options youwant to use for that layer.

5. Click Apply.

The next time you use a command that displays the layer you changed, the color orpattern changes in the design window.

Click on All



To highlight incomplete connections with flight lines, Virtuoso XL cycles throughthe y0 – y9 layers.

Virtuoso XL displays the flight lines of each net in a different color. If there are more than 10incomplete nets, the colors repeat unless you have specified layers for specific nets (see“Incomplete Nets”).

If you assign new colors to the flight lines,

■ Assign colors that do not resemble each other or resemble the colors you use for pathsand components

■ Avoid solid fill so you can see what is underneath

Virtuoso XL uses the hilite drawing through hilite drawing9 entry layers for probes, whichidentify equivalent design elements on the schematic and the layout.

Virtuoso XL uses the hilite drawing9 layer to identify components in the schematic that arenot in the layout (and vice versa) with the Connectivity – Check – Against Sourcecommand.

If you change the colors of the hilite drawing layers,

■ Use thick lines so you can see device pins

■ Use bright colors to make probes and highlights easy to find

npn

npn

Unconnected nets

npn

in

Q7Equivalent design elementsQ7

Schematic Layout



Note: Do not make the hilite drawing layer and the hilite drawing2 layer solid fill becausethese layers are used to indicate selected components and to manipulate shapes.



Using Bindkeys

Bindkeys, also called function keys, are keyboard macros that assign a menu command to akey you choose from the keyboard.

When your cursor is in the layout window, you can use all of the bindkeys that are loaded forthe applications you are running.

Displaying Bindkeys

To display the list of bindkeys for Virtuoso XL, follow these steps.

1. From the CIW, choose Options – Bindkey.

The Key or Mouse Binding form appears.

2. In the Application Type Prefix cyclic field, choose Layout.

3. Click Show Bind Keys.

A text window displays the layout editor bindkeys and commands.

Loading Virtuoso XL Bindkeys

You can find a list of default bindkeys for Virtuoso XL at the following location:



your_install_dir /samples/local/lxBindKeys.il

where your_install_dir is the top directory in which you store Cadence® software.

To load this file of bindkey definitions every time you run Virtuoso XL, add the following to your.cdsinit file:

load(prependInstallPath("samples/local/lxBindKeys.il"))



Setting Environment Variablesin the Layout XL Options Form

Environment variables control the values of Virtuoso XL options. You can set someVirtuoso XL environment variables in the individual options forms for Virtuoso XL commands.You can set other Virtuoso XL environment variables using the Layout XL Options form. (SeeTable 5-1 on page 93.)

You must set the options related to initialization (Show All Incomplete Nets and AutoArrange Windows) on the Layout XL Options form before you start your design session. Thevalues you enter for these options in the current session take effect the next time you startVirtuoso XL. Changes made to other values take effect as soon as you click OK or Apply. Toavoid having to restart the session, set these values in your . cdsenv or .cdsinit file.

Not all the Virtuoso XL environment variables are available through forms. You can set thevalue of environment variables not available on forms in your .cdsenv or .cdsinit file. Fora list of all the Virtuoso XL environment variables and their values, see Table 5-2 on page 96.

To set environment variables using the Layout XL Options form, follow these steps.

1. From the layout window, choose Options – Layout XL.



The Layout XL Options form appears.



2. In the Edit section at the top of the form, select Global Options or CellviewOptions, depending on whether you want the information you enter in this form applyto the your whole design environment or to only one cellview.

If you choose Cellview Options, several of the options on this form are grayed outbecause they cannot be localized to individual cellviews.

3. In the main body of the form, choose the layout options you want to apply to your design.Most of these options correspond to and set environment variables in your .cdsenv file,as shown below

Table 5-1 Layout XL Options Corresponding to Environment Variables

Layout XL Option Environment Variable

Connectivity

Connectivity Extractor extractEnabled

Extract Connectivity to Level extractStopLevel

Cross Selection crossSelect

Auto Abutment autoAbutment

Auto Space autoSpace

Auto Permute Pins autoPermutePins

Constraint Assisted Mode constraintAssistedMode

Verification

Show: Ignore Parameters ignoredParams

Show: Ignore Names ignoreNames

Tolerance paramTolerance

Generation

Show: Traverse Hierarchy Views viewList



4. In the Load/Save section at the bottom of the form, set the options according to whetheryou want to load the information from a file, save the information to a file, or delete theinformation in the form from the current cellview, the design library, the tech library, or afile.

If you choose the File option, the type-in field becomes active to let you type in a pathand name of a file.

❑ To save your design options to a cell or library other than the one from which youopened the form or to a tech library, type the name of a file and click Save to.

❑ To load previously saved options into this form, type the name of a file and click Loadfrom.

Show: Layout Instance Views stopList

Update Layout Instances updateReplacesMasters

Multiple Instances

mfactor Names mfactorNames

sfactor Names sfactorNames

sfactor Splitting Param sfactorParams

Generate Multiple Instances Turns off both mfactor and sfactor

Initial Display

Show All Incomplete Nets showIncNetEnable

Auto Arrange Windows autoArrange

Device Folding

Generate Minimal Folding lxFingeringNames

Table 5-1 Layout XL Options Corresponding to Environment Variables, continued

Layout XL Option Environment Variable



❑ To delete these values from a cell or a library, click Delete from.

Note: You cannot delete environment values from a file.

5. Click OK.

The environment variable values you choose are enforced for all subsequent designsessions until you change the value of the variables again.



Working with Virtuoso XL Environment Variables

Environment variables control the values of the options offered in Virtuoso XL as they do forother applications. You can set the following environment variables for Virtuoso XL:

Table 5-2 Virtuoso Layout Accelerator Environment Variables

Virtuoso XL Variable Description

alignApplySeparation Determines whether separation between alignedcomponents is enforced.Default Value: tValid Values: t , nil

alignDirection Determines whether a direction is enforced on alignedobjects and, if enforced, which direction is enforced.Default Value: horizontalValid Values: horizontal , vertical

alignLayer Determines which layers are involved in alignment.Default Value: noneValid Values: string

alignMethod Determines the reference point in the objects to be aligned.Default Value: BBox centerValid Values: BBox center , BBox edge , layer center ,layer edge , origins

alignSeparation Determines the number of user units by which alignedobjects are separated.Default Value: 1.0Valid Values: floating-point number

autoAbutment Controls whether or not Virtuoso XL allows preparedtransistors to be automatically abuttedDefault Value: tValid Values: t , nil

autoArrange Controls whether or not Virtuoso XL rearranges theconfiguration of windows on your desktop.Default Value: tValid Values: t , nil



autoPermutePins Enables automatic permutable pins (pins are permutedautomatically during manual routing or editing) whenVirtuoso XL is initiated.Default Value: tValid Values: t , nil

autoSpace Enables automatic spacing of components on which theautomatic spacing properties vxlInstSpacingDir andvxlInstSpacingRule are set.Default Value: tValid Values: t , nil

checkTimeStamps Determines whether Virtuoso XL checks your schematic timestamps through the hierarchy and warns you if yourschematic has changed since Virtuoso XL generated yourlayout.Default Value: tValid Values: t , nil

ciwWindow Determines the position of the CIW window on the screen.Default Value: ((0 0) (0 0))Valid Values: string in SKILL list format

constraintAssistedMode If set to t , causes the Move and Stretch commands toplace components in a layout using the algorithms of theconstraint-driven placer; if set to nil , causes the Move andStretch commands to ignore constraints. Fixed constraintswill prevent locked objects from being moved when set to t .Default Value: tValid Values: t , nil

createBoundaryLabel Specifies that a label specifying the library, cell, and viewnames of the design is created automatically when you createa boundary using the Layout Generation Option formassociated with the Gen From Source command.Default Value: nilValid Values: t , nil

Table 5-2 Virtuoso Layout Accelerator Environment Variables , continued




crossSelect Specifies that cross-selection (a component is selected inthe layout when you select the corresponding component inthe schematic or vice versa) operates.Default Value: tValid Values: t , nil

extractEnable Enables the extractor to be active when Virtuoso XL isinitiated.Default Value: tValid Values: t , nil

extractStopLevel Controls the level at which hierarchical extraction stops.Default Value: 0Valid Values: integer

Note: If you are using parameterized cells (pcells)

and change the extract level, false markers might show upover the pcells. You can prevent these false markers fromappearing by using the lxBlockOverlapCheck andlxBlockExtractChec k properties on instances at thelower levels of the design.

flightLineEnable Determines whether the rubberbanding flight lines shownduring the Move command are turned on as the default.Default Value: tValid Values: t , nil

ignoredParams Determines whether the value of device properties in theschematic are transferred to those devices in the layout.Default Values: lxIgnoredParams , dleIgnoredParams ,lxStopList , dleStopList , lxUseCell , dleUseCell ,maskLayout , ViewName, posi ,instancesLastChanged , instNamePrefix , pin# ,lxTimeStamp , dleSchExtractPath ,lxPlacementStatusValid Values: all default values (which should never beremoved) plus any other parameters you need to add





ignoreNames Defines a list of properties that cause pins and instances tobe ignored during Virtuoso XL update and comparisoncommands.Default Values: lvsIgnore , ignore , nlActionValid Values: all default values (which shouldnever be removed) plus any other parametersyou need to add

incNetCycleHilite Determines whether Show Incomplete Nets cycles throughthe y0–y9 drawing layers to display incomplete nets. IfincNetCycleHilite is nil , the layer specified in theincNetHiliteLayer environment variable is used for all nets.Default Value: tValid Values: t , nil

incNetHiliteLayer Determines what layer Show Incomplete Nets uses todisplay incomplete nets (if the incNetCycleHiliteenvironment variable is set to nil ).Default Value: y0 drawingValid Values: y0 - y9 string

infoWindow Determines whether messages about Virtuoso XL processesappear in an Info window (if t ) or in the CIW (if nil ).Default Value: tValid Values: t , nil

initAspectRatio Determines the width-to-height ratio of the design to beautomatically generated or reinitialized.Default Value: 1.0Valid Values: floating point-number

initAspectRatioOption Determines whether the Aspect Ratio option is turned on inthe Layout Generation Options form.Default Value: Aspect Ratio W/HValid Values: Aspect Ratio W/H , Boundary Width ,Boundary Height

initBoundaryLayer Defines the entry layer the software uses to enter the designboundary in the layout window.Default Value: prBoundary boundaryValid Values: string





initCreateBoundary Enables the software to create a design boundary in thelayout window.Default Value: tValid Values: t , nil

initCreateInstances Enables Virtuoso XL to create instances as specified in thePlace From Schematic command.Default Value: tValid Values: t , nil

initCreateMTM Enables Virtuoso XL to assign many-to-many groupingsDefault Value: tValid Values: t , nil

initCreatePins Enables Virtuoso XL to create pins as specified in the LayoutGeneration Options form.Default Value: tValid Values: t , nil

initDoFolding Enables Virtuoso XL to fold prepared transistors intoseparate fingers.Default Value: tValid Values: t , nil

initDoStacking Enables Virtuoso XL to abut prepared transistors into stacks.Default Value: tValid Values: t , nil

initEstimateArea Determines whether Virtuoso XL estimates the size of thedesign boundary based on the values entered in the LayoutGeneration Options form used with the Gen from Source orUpdate Components and Nets commands.Default Value: tValid Values: t , nil

initGlobalNetPins Determines whether the Virtuoso XL Gen from Sourcecommand creates pins for global nets.Default Value: tValid Values: t , nil





initIOPinLayer Specifies which of the layers defined in the technology file isto be used as the pin layer when you use the Gen fromSource or Update Components and Nets commands.Default Value: noneValid Values: string

initIOPinName Specifies the name of the pins generated when you use theGen from Source or Update Components and Netscommands.Default Value: noneValid Values: string

initPinHeight Specifies the pin height to be used when you use the Genfrom Source or Update Components and Netscommands.Default Value: minWidth of layerValid Values: floating-point number

initPinMultiplicity Specifies the number of pins of each kind to be placed.Default Value: 1Valid Values: integer

initPinWidth Specifies the pin width to be used when you use the Genfrom Source or Update Components and Netscommands.Default Value: minWidth of layerValid Values: floating-point number

initPrBoundaryH Specifies the height of the design boundary to be used whenyou use the Gen from Source or Update Componentsand Nets commands.Default Value: 10.0 or last valueValid Values: floating-point number

initPrBoundaryW Specifies the width of the design boundary to be used whenyou use the Gen from Source or Update Componentsand Nets commands.Default Value: 10.0 or last valueValid Values: floating-point number

initSymbolicPins Determines whether Virtuoso XL creates symbolic pins.Default Value: tValid Values: t , nil





initUtilization Specifies the percentage of area within the design boundaryto be filled when the Estimate Area option is turned on inthe Layout Generation Options form used with the Gen fromSource or Update Components and Nets commands.Default Value: 25.0Valid Values: floating-point number

layoutWindow Determines the position of the layout window when VirtuosoXL is initiated.Default Value: ((0 0) (0 0))Valid Values: ((0 0) (0 0)) string in SKILL listformat

lswWindow Determines the position of the (LSW) when Virtuoso XL isinitiated.Default Value: ((0 0) (0 0))Valid Values: ((0 0) (0 0)) string in SKILL listformat

lxAllowPseudoParallelNets

Enables detection of pseudo-parallel nets (nets with only twodevices connected that can be split using the same numberof fingers) if set to t.Default Value: nilValid Values: t , nil

lxDeltaWidth Determines the effective width of folded transistors. Theeffective total width is defined asWeff = M (W + lxDeltaWidth)where M is the number of fingers and W is the identical widthof each transistor.Default Value: 0Valid Values: floating-point number

lxFingeringNames Specifies property names other than fingers or finger to tosplit the number of fingers.Default Value: fingers fingerValid Values: string





lxStackPartitionParameters

Sets the device stacking partition parameters.The value is a list of two items. The first value controls howfar up in the hierarchy Virtuoso XL looks for opportunities toabut devices. A value of 1 permits abutment of devices withinthe same gate only. A value of 2 permits abutment of anydevices in the same master. Higher values permit abutmentwith devices at progressively higher levels of the designhierarchy.The second value sets the maximum number of devices in astack.The values (-1 -1) let Virtuoso XL decide how to handle eachstack.Default Value: "(1 8)"Valid Values: string

lxStackMinimalFolding Controls folding to yield the minimum number of legs foreach folded device. If set to true (t),the folding will yield theminimal number of fingers, whether this is even or odd.

Default Value: nilValid Values: t , nil

lxWidthTolerance Sets the allowed device width variation for folding. Of the twopositive numbers provided as the value, the first in the list isthe absolute value of the negative tolerance; the second isthe positive tolerance.Default Value: "(0.0 0.0)"Valid Values: string

maintainConnections Enables the automatic Maintain Connections option whenVirtuoso XL is initiated.Default Value: nilValid Values: t , nil

mfactorNames Specifies property names other than m or M to designate thenumber by which to multiply the number of transistors.Default Value: m MValid Values: string

mfactorSplit Determines whether Virtuoso XL should place split devicesfound in the schematic as multiple devices in the layout.Default Value: tValid Values: t , nil





moveAsGroup Determines the ability to move groups of components boundby placement constraints as a unit (set by turning on thetogether option on the Virtuoso XL version of the Edit –Move form).Default Value: tValid Values: Boolean

paramTolerance Specifies the relative tolerance the Verify Parameterscommand uses to compare values between the layout andthe schematic.Default Value: 1e-6Valid Values: any positive floating-point number

pathProbe Determines whether the Path command automaticallyprobes (highlights) the net attached to the shape under thestarting point for the path. It also changes the current layer tothe layer of the shape under the starting point for the path.Default Value: tValid Values: t , nil

probeCycleHilite Specifies whether the Probe command cycles through thehilite drawing0 – hilite drawing9 entry layersfor showing probes.Default Value: tValid Values: t , nil

probeDevice Determines whether the Probe command highlights deviceson the schematic and layout.Default Value: tValid Values: t , nil

probeHiliteLayer Determines whether the hilite entry layer or another layeris used to display probes.Default Value: hilite drawingValid Values: hilite drw to hilite dr9 layers (string)

probeInfoInCIW Determines whether the output of the Probe commandappears in the CIW as well as in the Probe form.Default Value: nilValid Values: t , nil





probeNet Determines whether nets can be highlighted on theschematic and layout by the Probe command.Default Value: tValid Values: t , nil

probePin Determines whether pins can be highlighted on theschematic and layout by the Probe command.Default Value: tValid Values: t , nil

schematicWindow Determines the position of the schematic window on thescreen when Virtuoso XL is initiated.Default Value: ((0 0) (0 0))Valid Values: ((0 0) (0 0)) string in SKILL listformat

sfactorNames Specifies the names of properties other than "s" or "S"defined in the schematic to designate the number ofcorresponding series-connected devices to be generated inthe layout. The s-factor property value can be expressed asan integer or an expression.Default Value: s SValid Values: string

sfactorParam Specifies parameters other than “r R c C l L ” todesignate the parameter that needs to be calculated for eachgenerated device.Default Value: r R c C l LValid Values: string

showIncNetEnable Specifies that the Show Incomplete Nets command isactive when Virtuoso XL is initiated.Default Value: nilValid Values: t , nil

stopList Determines the view of a design that permits no furtherdescent in a hierarchical design.Default Value: layoutValid Values: string (view names of cells; for example,layout, compacted, symbolic, abstract,autoAbstract)





Note: The environment variables dlrNetConstNetWeight, dlrRoutingBoundaryOption,and dlrNetConstNetClass, associated with the obsolete Device-Level Router, are no longeraccessible.

templateFileName Specifies a default template file for the Gen from Sourcecommand. If its value is the empty string(" ", the default), the default filename islayout_cell_name. lxt . If it is anything other than theempty string, its value is used as the default filename.Default Value: "" ( empty)Valid Values: string

updateReplacesMasters When you run the command, if t , lets a layout instance witha name matching a schematic instance name keep its nameand have its master replaced. If nil , renames the instanceusing the correct master and places it below the designboundary.Default Value: nilValid Values: t , nil

viewList Determines the views of a design that are used indescending through a hierarchical design to find stoppingviews (see stopList).Default Value: schematic netlist symbol layoutcompacted symbolicValid Values: string (view names of cells; for example,abstract , autoAbstract , layout , compacted ,symbolic)





Setting Environment Variables

If you use any values of environment variables consistently and do not want to set thesevalues each time you use a command, you can set the variables to the value you customarilyuse for a single session or you can set them permanently in setup files such as the .cdsenvfile and the .cdsinit file.

To set environment variables for a single session, do any of the following:

■ Include envSetVal( ) in any other Cadence SKILL file you load

■ Type envSetVal( ) in the CIW

To set environment variables permanently, do any of the following:

■ Include the environment variables in the .cdsenv file in your home directory. Forexample:

layoutXL alignApplySeparation boolean t

■ Include envSetVal( ) in your .cdsinit file

For example, to set the Virtuoso XL alignApplySeparation variable (to force Virtuoso XL toseparate aligned components by a separation factor you supply), type the following in theCIW or include it in a setup file:

envSetVal("layoutXL" "alignApplySeparation" 'boolean t)

To determine the current value of any Virtuoso XL environment variable, type in the CIW:

envGetVal("layoutXL" "alignApplySeparation" 'boolean)



Information About Online Forms

Layout XL Options Form

Edit

Global Options applies the values specified in this form to the cellview being edited aswell as to all other views of this cell.

Cellview Options applies the values specified in this form only to the cellview beingedited.

Connectivity

Connectivity Extractor turns on hierarchical extraction. When hierarchical extractionis turned off, the Incomplete Nets command is disabled.

Extract Connectivity to Level sets the level where hierarchical extraction stops.

Cross Selection turns on cross-selection (between layout and schematic).

Auto Abutment turns on automatic abutment, which allows prepared transistors to beautomatically stacked together so that they can share pins.

Auto Space turns on automatic spacing, which allows components with the automaticspacing properties vxlInstSpacingDir and vxlInstSpacingRule to beautomatically spaced according to the values specified in the properties.

Auto Permute Pins turns on automatic pin permutation during manual routing orediting.

Constraint Assisted Mode turns on constraint-assisted placement.

Verification

Show Ignore Parameters sets the value of device properties in the schematic to thosein the layout.

Show Ignore Names defines a list of properties that cause pins and instances to beignored during Virtuoso XL updates.

Add lets you type in the names of parameters.

Remove lets you remove parameters by clicking on the name of the parameter in the listbox.



Tolerance sets the allowable percentage of difference in values between the layout andthe schematic.

Generation

Show Traverse Hierarchy Views shows the list of views included in the view list whendescending a hierarchical design.

Show Layout Instance Views shows the list of views included in the stop list whendescending a hierarchical design.

Add lets you type in the names of views.

Remove lets you remove views by clicking on the name of the view in the list box.

Update Layout Instances , when turned on, sets the command to replace an updatedinstance in the layout window with another with the same name. When turned off, it setsthe command to put a marker on the old instance in the layout window and place the newinstance below the design boundary.

Multiple Instances

mfactor Names lists the property names defined in the schematic other than mor Mtodesignate the number by which to multiply the number of transistors.The mfactorproperty value can be expressed as an integer or an expression.

sfactor Names lists the names of properties other than s or S defined in the schematicto designate the number of corresponding series-connected devices to be generated inthe layout. The sfactor property value can be expressed as an integer or an expression.

sfactor Splitting Param lists the property names defined in the schematic in additionto r , R, c , C, l , and L to designate the parameter that needs to be calculated for eachgenerated device.

Generate Multiple Instances , when turned on, lets Virtuoso XL place devices with themfactor (multiplier) and sfactor (series) properties found in the schematic as multipledevices in the layout.

Initial Display

Show All Incomplete Nets activates the Show Incomplete Nets command the nexttime you start Virtuoso XL (not in the current session). To see all incomplete netsimmediately, use the Connectivity – Show Incomplete Nets command.

Auto Arrange Windows sets the positions of the design windows the next time youstart Virtuoso XL.

Load/Save



Cellview lets you load/save/delete the values specified in this form from/to the cellviewfrom which you chose the Layout XL Options form.

Library lets you load/save/delete the values specified in this form from/to the library thatincludes the cellview from which you chose the Layout XL Options form.

Tech Library lets you load/save/delete the values specified in this form from/to the techlibrary of the cellview from which you chose the Layout XL Options form.

File lets you load/save/delete the values specified in this form from or to your .cdsenvfile (the default) or a file whose name you type in the text field.



6Setting Up Device Abutment forVirtuoso Layout Accelerator

This chapter shows you how to use the Virtuoso® XL abutment capability. Abutment allowscells to be automatically aligned or overlapped and electrically connected. This chapterdiscusses the following topics:

■ Introduction to Abutment on page 112

■ Abutment Requirements on page 112

■ Setting Up Cells for Abutment on page 113

■ Sample Parameterized Cells Set Up for Abutment on page 120

■ Creating CMOS Pcells to Use with Abutment on page 125

■ Setting Environment Variables for Abutment on page 130

■ Using Device Abutment on page 132


Virtuoso Layout Accelerator User GuideSetting Up Device Abutment for Virtuoso Layout Accelerator

Introduction to Abutment

The Virtuoso XL abutment capability lets you create a connection between two cellsoverlapping each other without introducing design rule violations or connectivity errors. Thetwo sets of shapes must include pins connected to the same net.

Abutment reduces the area occupied by the circuit and the length of the interconnect wiring.You can use abutment during interactive layout.

For information about building Parameterized Cells (pcells) with relative object design (ROD)functions, see the Virtuoso Relative Object Design User Guide and the ParameterizedCells Installation and Reference.

Abutment Requirements

Devices can be abutted only between pins of different instances. Abutment of pins requiresthe following conditions:

■ Both instances must be pcells set up for abutment or cells with abutment properties.

■ Both instances must be from the same master or have the abutClass property.

MOS transistors sharing a diffusion

Wells sharing part of their surface and bias contacts

Resistors sharing terminals

A. Same size, terminals withexternal connection onsamenet

B. Same size, no otherconnections on the same net

C. Different size, terminals withexternal connection on thesame net



To abut two different cells, you must add the property abutClass to the pin of each celland enter the same abutment class name as the value for each property.

If two similar pcells have different parameter values, they have different submasters; inthat case, abutment works only if they have the same master.

■ Both instance pins must be connected to the same net.

■ Both instance pins must be defined on shapes of the same layer or on layers that aredefined as equivalent layers in the technology file.

■ Both instance pins must have opposite abutment directions; for example, right for a pinon the right side of a cell and left for a pin on the left side of a cell.

■ The shapes of the two pins must be identical, or one of them must be able to becompletely contained within the other.

■ During placement, the Connectivity Extractor and Auto Abutment options in theVirtuoso XL Options form must turned on.

Abutted devices can share diffusion, contacts, metal tabs, or any shape combined in aninstance pin.

Setting Up Cells for Abutment

You can set up both regular cells (in any technology) and pcells for abutment. To set up aregular cell so that it can be abutted, you need to add the following four properties to the pins.

■ abutFunction

■ abutOffset

■ abutAccessDir

■ abutClass

You can also place these properties on the pins on a master cell to provide abutment functionfor all pins on the cell.

If you are using pcells, you can use the default abutment functions.

abutFunction

abutFunction is a callback that you create to process abutment and un-abutment. Thevalue of this property is a string consisting of the name of a user-defined Cadence® SKILL



function that is executed before abutment takes place. Auto-abutment passes this functioneight arguments in a list made up of the following information in this order:

1. The dbId of the cell being abutted

2. The dbId of the cell being abutted to

3. The dbId of the pin figure of the cell being abutted

4. The dbId of the pin figure of the cell being abutted to

5. The abutment access direction of pin being abutted (integer):

❑ 1 - top

❑ 2 - bottom

❑ 4 - left

❑ 8 - right

6. An integer with a valid value of 1or 2 that indicates connection condition:

❑ 1 - pins are connected to the same net and do not connect to any other pin

❑ 2 - pins are connected to the same net and the net connects to other pins

7. An integer specifying auto-abutment events:

❑ 1 - abutFunction must compute and return abutment offset (in the direction ofabutment)

❑ 2 - abutFunction must adjust pcell parameters for abutment. This is calledbefore the offset event.

❑ 3 - abutFunction must adjust pcell parameters for unabutment

8. A dbId that is the abutment group pointer available to events 2 and 3. It is used to storeinformation so that unabutment can return pins to their original state. It is a generallyaccepted method to use the group attribute of a cell to hold original parameter valuesprior to modification by abutment.

abutFunction returns different values for different auto-abutment events:

■ If the event is 1, it returns a floating-point number, the offset needed to abut the cells inthe direction of abutment. If it returns two floating-point numbers, the second number isthe distance in user units that the abutting cell is moved perpendicularly to the abuttingedge.

■ If the event is 2, it returns t for success and nil for failure.



■ If the event is 3, it can return anything; the value returned is not used.

Here is an example of the abutFunction property:

procedure( abutFunction(iA iB pA pB pASide connection event @optional(group nil)) prog((result)

case(event

(1 ; Compute offsetresult = getAbutmentOffset(iA iB pA pB pASide connection)

)

(2 ; Adjust pcell parametersresult = setAbutmentParams(iA iB pA pB pASide connection

group)

)

(3 ; Adjust pcell parameters back to defaultresetAbutmentParams(group iA iB)

result = t

)

(t ; Anything else return a nil result = nil

)

)

return(result)

)

)

abutOffset

abutOffset 5

abutOffset sets an offset based on the reference edge. The reference edge is the outsideedge of the pin that triggered the abutment on each cell in the direction defined by theabutment direction. The value of this offset is a floating-point number. This number can bepositive or negative and indicates a distance (in user units) to offset the reference edge to theoutside direction of the cell. A negative number causes the pins to overlap.

If the abutFunction parameter adjustment event returns nil , auto-abutment looks for aproperty on the pin called abutOffset and applies the value of this property for offset. Ifthe property abutOffset does not exist, auto-abutment uses the outside edge of the pinwith no offset.



Alignment Perpendicular to Abutment Direction

If the pin of the device being abutted overlaps the other pin on the bottom or top, the pins arealigned by the bottom or top edges, respectively. This also applies from side to side whenabutment is vertical.

Multiple Pins

Multiple pins on the edge of a cell can be abutted. Any pair of pins with the correct propertiescan trigger auto-abutment, but once auto-abutment has been triggered, other pins on thatedge that touch pins on the cell it is abutted to will not retrigger auto-abutment. If those pinsdo not connect, auto-permute tries to resolve the conflict. If the conflict cannot be resolved,the connection violation is flagged.

Note: Make sure that you define abutment in such a way that no Design Rule Checker (DRC)or connectivity violations are introduced by abutment between any selected pair of pins.

res

res

res

res

Interactive move places one cellapproximately overlapping another

abutOffset = -5

res

res

res

res

abutOffset = 5

Cells are first aligned and then theoffset is applied. In this case,abutOffset = 0 or not set



Different abutFunctions Defined

If each pin being abutted has a different abutFunction defined, auto-abutment calls onlythe function defined by the pin in the cell being moved.

abutAccessDir

abutAccessDir list("right")

abutAccessDir provides information to make sure the proper edges are abutting; forexample, a left side to a right side, or a bottom to a top. Cells with rail pins need to add accessdirections for both sides because there is one pin for both right and left sides of the cell (“left”“right”). MOS cells have just one pin per side, so they need only one direction (“left”).

abutClass

abutClass "stdcell"

abutClass allows two different cells to abut, even if their master cells are not the same.abutClass is placed on the pin. Each pin targeted for abutment can belong to only oneclass. Pins on different edges of a cell can belong to different classes. Therefore, a cell canhave multiple abutment classes but only one class per pin. The property can also be added



to the cellview to implement a global class for all the pins. Auto-abutment checks for theabutClass property first on the pin and then on the master.

Steps in Auto-Abutment

1. Overlapping pins trigger auto-abutment.

2. Auto-abutment identifies cells for abutment by master name or class.

3. Auto-abutment calls abutFunction .

4. abutFunction has the opportunity to adjust parameters of the pcells and calculatereference edge offsets of the conventional cells.

5. Pcells calculate a new configuration based on any parameters changed byabutFunction .

abutClass properties

interface cell

Class C

Class BClass A



6. If the cells can be abutted (the abutment connection condition is 1 or 2), the cells areabutted to the reference edges and the pins are aligned perpendicular to the direction ofabutment.

If the cells cannot be abutted (the abutment connection condition is 3), they remain intheir original configuration.



Sample Parameterized Cells Set Up for Abutment

Example 1

The generic example below shows what each of the different parts does.

----------------------------------------------------------------

; Function: abutFunction(iA iB pA pB pASide connection event@optional (group nil))

;

; Inputs: group - the abutment group that these two cells belong to.

;_______________________________________________________________

;

; iA = Instance Id of cell that will move during abutment

;_______________________________________________________________

;

; iB = Instance Id of cell being abutted to

;_______________________________________________________________

;

; pA = Overlapping Pin Fig of iA

;_______________________________________________________________

;

; pB = Overlapping Pin Fig of iB

;_______________________________________________________________

;

; pASide = Abutting pin access direction

;_______________________________________________________________

;

; connection = an integer value of 1 or 2 that indicates:



;

; 1. pins are connected to the same net and do not

; connect to any other pin.

;

; 2. pins are connected to the same net and the net

; connects to other pins

;_______________________________________________________________

;

; event = integer that represents abutment event:

;

; 1. compute abutment offset

; 2. pcell parameter adjustment for abutment

; 3. pcell parameter adjustment for unabutment

;_______________________________________________________________

;

; group = abutment group pointer available to events 2 and 3

;_______________________________________________________________

;

; Outputs: depends

;

; Side effects:

;

procedure( abutFunction(iA iB pA pB pASide connection event @optional(group

nil))

prog((result)

case(event

(1 ; Compute offset

result = getAbutmentOffset(iA iB pA pB pASide connection)



)

(2 ; Adjust pcell parameters

result = setAbutmentParams(iA iB pA pB pASide connectiongroup)

)

(3 ; Adjust pcell parameters back to defaultresetAbutmentParams(group iA iB)

result = t

)

(t ; Anything else return a nil

result = nil

)

)

return(result)

)

)



Example 2

This example shows how to add abutment properties to pins in an inverter pcell.

.; *** the following 4 pins are on metal1 and are on ***; *** the power and ground rails. This will allow ***; *** abutment to other standard cells ***

obj = leftVddPin~>dbId

dbReplaceProp(obj "abutAccessDir" "list" list("left"))

dbReplaceProp(obj "abutClass" "string" "stdcell")

dbReplaceProp(obj "abutFunction" "string" "stdCellFunc")

; *** the following property is a technique for passing ***

; *** information to the user defined function. In this ***

; *** case the minimum cell height is dependent on many ***

; *** factors including design rules and is originally ***

; *** calculated in the pcell code. This avoids ***

; *** duplicating calculations in the user-defined ***

; *** function ****

dbReplaceProp(obj "minCellHeight" "float" minH)

obj = rightVddPin~>dbId

dbReplaceProp(obj "abutAccessDir" "list" list("right"))




obj = leftGndPin~>dbId





obj = rightGndPin~>dbId







; *** The following 4 pins are the diffusion pins ***

; *** of the individual MOS devices in the inverter ***

; *** this will allow abutment of other individual ***

; *** MOS devices to the inverter ***

obj = POutPin~>dbId


dbReplaceProp(obj "abutClass" "string" "ptran")

dbReplaceProp(obj "abutFunction" "string" "mosAbutFunc")

dbReplaceProp(obj "contactParam" "string" "POutCnts")

dbReplaceProp(obj "w" "float" pw)

; *** these spacing properties are used if abutment fails

dbReplaceProp(obj "vxlInstSpacingDir" "list" list("right"))

dbReplaceProp(obj "vxlInstSpacingRule" "float" .35 )

obj = NOutPin~>dbId


dbReplaceProp(obj "abutClass" "string" "ntran")


dbReplaceProp(obj "contactParam" "string" "NOutCnts")

dbReplaceProp(obj "w" "float" nw)

dbReplaceProp(obj "vxlInstSpacingDir" "list" list("right"))


obj = PPwrPin~>dbId


dbReplaceProp(obj "abutClass" "string" "ptran")




dbReplaceProp(obj "contactParam" "string" "PPwrCnts")

dbReplaceProp(obj "w" "float" pw)

dbReplaceProp(obj "vxlInstSpacingDir" "list" list("left"))


obj = NPwrPin~>dbId


dbReplaceProp(obj "abutClass" "string" "ntran")


dbReplaceProp(obj "contactParam" "string" "NPwrCnts")

dbReplaceProp(obj "w" "float" nw)

dbReplaceProp(obj "vxlInstSpacingDir" "list" list("left"))


Creating CMOS Pcells to Use with Abutment

To create pcells that have a built-in abutment capability, follow these steps.

1. Create a pcell specifically for abutment.

Editing an existing pcell for abutment is much more difficult than creating a new one forthe purpose.

2. Add the following abutment parameters to the pcell.

❑ Conditional inclusion or exclusion of contacts

This parameter adds or removes the contact. You can conditionally include orexclude the contacts and connecting metal tab. You must conditionally excludethese features if you are creating a graphical pcell. The pcell parameter mustremove all features that are required for metal hookup and leave only the diffusionmaterial to be stretched. For CMOS device abutment, you add this property to boththe drain and the source sides of the device.



Property Name Value (name of pcell parameter Value TypeabutCondExclusion drainContact? ilString

❑ Gate pin identification

This parameter identifies the gate pins so the abutment software knows where theedge of the gate is. In this example, the value G is the name of the gate net insidethe pcell.

Property Name Value (name of pcell parameter) Value TypeabutGateNet G ilString

❑ Access direction identification

This parameter identifies the abutment access direction. Valid access directions areleft , right , bottom , and top . This variable should contain only reasonablevalues. If access is only from the right, then add only that value.Note: Access is from the right or the left.

Property Name Value (name of pcell parameter) Value TypeabutAccessDir list("top" "left") ilList

gatenet.gif



❑ Stretchable material

This parameter stretches the material toward or away from the gate when theinstance is altered for abutment. The default value of the stretch parameter must bethe distance from the edge of the material to the edge of the gate. Numeric valuesare in user units.

Property Name Value (name of Pcell parameter) Value TypeabutStretchMat list (“drainStretch” ilList

list ("abutMinExt" 0.5)list ("abutRule1Ext" 0.75)list ("abutRule2Ext" 1.0)

list ("abutContactExt" 3.0))

The first element in the list (drainStretch ) is the name of the stretchablematerial parameter. You name this parameter yourself to identify the material to bestretched.

accessdir.gif



The second element in the list (abutMinExt ) is the rule for minimum diffusionoverhang from the edge of the poly gate. The argument to this element (0.5) is therule value.

The third element in the list (abutRule1Ext) is the poly-layer-to-poly-layer rule. Thisrule is used when the net connecting the two instances does not share the net withany other pin.

The fourth element in the list (abutRule2Ext) is the poly-layer-to-diffusion rule. Therule is used when the gate width is different for the two instances being abutted.

The fifth element in the list (abutContactExt ) is the diffusion extension valueused when one of the contacts needs to be added during the abutment process.



With the contacts off by default, the abutment program needs to know how close tomove the selected cell to abut properly.

contactext.gif



Setting Environment Variables for Abutment

Two environment variables that you can set in the Move form affect how abutment works inyour design:

■ moveAsGroup (Move Together in the Move form)

■ constraintAssistedMode (Constraint Assisted in the Move form)

Move Together

This variable tells the system to treat the instances in a selected set as a group and tomaintain their relative position. If two cells in the selected group can be abutted to differentcells, only one abutment will occur because abutting both would upset the relative position ofthe set. The cell chosen is the one that causes the selected set the least movement.

Constraint Assisted

Virtuoso XL can set and maintain constraints added to instances. If some of the instancesbeing moved belong to a satisfied constraint, the abutment system must maintain theconstraint. If abutment would cause a constraint to be broken, the abutment system will notabut the two cells.

To set the environment variables you want to affect the abutment process, follow these steps.

1. From the layout window, choose Edit – Move.

2. Press F3.



The Move form appears.

3. Under Constraint Assisted Control, turn on together or individually.

If you do not want constraints to have any influence on interactive moves, turn on ignore.You can also activate constraint enforcement with the Constraint Assisted Modeoption in the Virtuoso XL Options form.

Note: If you move abutted devices in the layout editor, the abutment group is broken but thecontacts are left as if they are still abutted.

Constraint Assisted Control



Using Device Abutment

When you are ready to use device abutment during the creation of a layout, see “AbuttingDevices Using Pick from Schematic” on page 177 .

When you are ready to use device abutment while you are editing a layout, see “UsingInteractive Device Abutment” on page 227 .



7Generating Your Layout with VirtuosoLayout Accelerator

This chapter shows you how to use the Virtuoso® layout accelerator (Virtuoso XL) to generatea layout and make an initial placement of components in it. This chapter covers the followingtopics:

■ Starting Virtuoso XL from the Schematic on page 134

■ Importing a Netlist for a Connectivity Reference on page 135

■ Starting Virtuoso XL from the Layout View on page 140

■ Defining the Design Boundary on page 143

■ Working with Layout Generation Templates on page 144

■ Generating a Layout with Components Not Placed (Gen From Source) on page 160

■ Placing Components in a Layout in the Same Relative Position as in the Schematic(Place from Schematic) on page 169

■ Moving Components from the Schematic into the Layout (Pick from Schematic) onpage 170

■ Abutting Devices Using Pick from Schematic on page 177

■ Cloning Components on page 177



Virtuoso Layout Accelerator User GuideGenerating Your Layout with Virtuoso Layout Accelerator

Starting Virtuoso XL from the Schematic

To start Virtuoso XL from a schematic window, follow these steps.

1. From the Command Interpreter Window (CIW), choose File – Open.

The Open File form appears.

2. In the Library Name cyclic field, choose a library name.

3. In the Cell Name field, type a cell name.

4. In the View Name cyclic field, choose a schematic view.

5. Click OK.

The schematic view you specified appears.

6. From the schematic window, choose Tools – Design Synthesis –Layout XL.

Note: Layout XL does not appear in the Tools menu unless the Virtuoso XL softwareis installed. If you do not see Layout XL in the Tools – Design Synthesis menu, checkwith your system administrator.

user/mnt2/home/cds.lib



The Startup Option form appears.

7. Choose whether you want to open a new or an existing layout cellview.

8. Click OK.

If you choose Create New, the Create New File form appears. The default view is a newlayout.

❑ In the Library Name cyclic field, choose a library name.

❑ In the Cell Name field, type a cell name.

❑ In the View Name field, type a view name.

❑ Click OK.

If you choose Open Existing, the Open File form appears.

❑ In the Library Name cyclic field, choose a library name.

❑ In the Cell Name field, type a cell name.

❑ In the View Name field, type a view name.

❑ Click OK.

The default configuration of Virtuoso XL appears: the schematic window, the layoutwindow, the CIW, and the LSW (Layer Selection Window).

Importing a Netlist for a Connectivity Reference

To import a netlist to use as the connectivity source for a Virtuoso XL design, follow thesesteps.

1. From the CIW, choose File – Import – XL Netlist.



The Import XL Netlist form appears.

2. In the Netlist File field, type the name of the input file (the netlist you want to import).

To see the names of your directories and files in the file browser, put the cursor in theNetlist File field or the Mapping File field and click Browse.

Currently, only netlists in the CDL (Circuit Description Language) format can beimported.

3. Choose whether you want to copy the imported netlist file to the destination library, linkthe imported netlist file to the destination library, or move the imported netlist file to thedestination library.

4. Type the name of a mapping file to import.

The mapping file lists device classes, device properties, and other properties and mapsthem to the names they have in the layout.

For example, the names of resistors in the netlist might be r1 through rn; the mappingfile would map them to resistors in the layout with the cell name res.



You can also use the mapping file to map terminal names in the netlist (such as resistorterminal names Plus and Minus) to terminal names in the layout (such as resistorterminal names A and B), and parameter names in the netlist (such as the resistancevalue r) to parameter names in the layout (such as the resistance value R).

The Import XL Netlist form loads the information in the mapping file into the cellview youspecify on the form, overwriting any previously entered information. The mapping filestructure, with an example, is shown in the next section.

Note: You can import an input netlist file, a mapping file, or both.

5. In the Library field, type the name of the library in which you want to store the netlist and/or mapping file.

6. In the Cell field, type the name of the cell in which you want to store the netlist and/ormapping file.

7. In the View field, type the name of the view you want to give the netlist.

To see the libraries, cells, and views in the Library Browser, put the cursor in the Libraryor Cell or View fields and click Browse.

8. Click OK.

Virtuoso XL imports the netlist and/or mapping file to the library, cell, and view name youspecified. You can now use this netlist as a connectivity reference for a Virtuoso XLdesign.



Mapping File Structure

The structure of the mapping file is as follows:

lxNetlistCellMap(

( device_class

( device_type

( property )

( property )

...

)

( property )

...

)

( property )

...

)

where

■ device_class is a string identifying a device class. For CDL netlists, this is the firstcharacter(s) of the device name; for example, M for MOS, Q for BJT.

■ device_type identifies the device type. It contains the keyword, a separator, and thename of the device type. For CDL netlists, this is the MODEL property, whose separatoris “=” and whose value can be any string; for example, N or PNP.

■ property is a property. Properties can be defined in any number at any level inside thetemplate, and inheritance rules apply to them. Therefore, properties defined at a highlevel apply globally to all devices defined at that level or lower, except where they arelocally overwritten.

The following is the list of properties:

❑ useCell name defines name as the layout cell to be used to implement the device.

❑ paramNameMap list defines a mapping table between the device parametersand the layout cell’s parameters. list is a list of pairs in the form device_paramcell_param .



❑ pinNameMap list defines a mapping table between the device pin names andthe layout cell’s pin names. list is a list of pairs in the form device_pincell_in .

❑ paramSet list sets a list of parameters to the given values. The list containselements of the type name type value , meaning that the value of name in thecell must be set to the value of the given type.

❑ stopList list defines list as the stop list.

❑ ignoreNames list_of_names specifies instances to be ignored during layoutgeneration. This property applies only at the top level of the design. If this propertyis used at lower levels, it still applies to only the top level and the software issueswarnings to remind you of this.

❑ ignoreCells list_of_names defines subcircuits whose instances are to beignored during layout generation. This property applies only at the top level of thedesign. If it appears at a lower level, it still applies only to the top level and thesoftware issues warnings to remind you of this.

❑ ignoreParams list_of_params defines names of parameters to be ignoredduring layout generation. This property applies within the level it is defined in.

❑ ignorePins list_of_pins defines names of pins to be ignored during layoutgeneration. This property applies to all the instances within the level it is defined in.

The order in which devices and properties are defined in the mapping file is irrelevant.

Example

lxNetlistCellMap(("M"

(("MODEL" "=" "P")(useCell "pmos")(paramNameMap ("WP" "w")("wp" "w")("LP" "l") ("lp" "l"))(paramSet ("l" "float" 1.1))

)

(("MODEL" "=" "N")(useCell "nmos")(paramNameMap ("WN" "w")("wn" "“w")("LN" "l")("ln" "l"))

)

(paramNameMap ("W" "w") ("L" "l") ("M" "m")("C" "c") ("A" "a") ("P" "p") ("R" "r"))

(pinNameMap ("s" "S") ("g" "G") ("d" "D")("b" "B"))



(paramSet("l" "float" 1.0)("w" "float" 1.3)("sourceContact?" "boolean" t)("drainContact?" "boolean" t)("showLabels?" "boolean" t)

)

(stopList "symbolic") )

(stopList "layout compacted symbolic"))

In this example, the stop list layout compacted symbolic applies to all devices, exceptMOS, to which the stop list symbolic applies. Similarly, parameter l is set to 1.0 for allMOS devices, except the ones of type P, for which it is set to 1.1 .

Starting Virtuoso XL from the Layout View

To start the Virtuoso XL from a layout window, follow these steps.

1. From the CIW, choose File – Open.




2. In the Library Name cyclic field, choose a library name.

3. In the Cell Name field, type a cell name.

4. In the View Name cyclic field, choose a layout view.

5. Click OK.

The layout view you specified appears.

6. From the layout window, choose Tools – Layout XL.

The default configuration of Virtuoso XL appears: the schematic window, the layoutwindow, the CIW, and the LSW.

Note: Layout XL does not appear in the Tools menu unless the Virtuoso XL softwareis installed. If you do not see Layout XL in the Tools menu, check with your systemadministrator.

user/mnt2/home/cds.lib



If the layout from which you chose the Layout XL command has no connectivityreference (schematic or netlist) associated with it, the Define Connectivity Referenceform appears.

7. Choose one of the following as the connectivity source type.

❑ If there is no connectivity reference for the layout, choose None.

Virtuoso XL is installed, but Virtuoso XL commands requiring information from aconnectivity source are disabled. You can at a later time define a connectivityreference by choosing Connectivity –Update – Source.

When you choose None (no connectivity reference), the connectivity modelrequires that the nets of pins and instance terminals cannot be changed, but the netsof all other shapes can be changed if they connect to a pin or instance terminal.

❑ If the connectivity reference is a schematic, choose Schematic and do one of thefollowing:

- Type the name of the library, cell, and view into Library, Cell, and View fields.

- Click Browse to see what cells are available in the Library Browser, and click on acell name in the Library Browser.

- Click Sel by Cursor and then click on an open schematic.

❑ If the connectivity reference is a netlist, choose Netlist.



The Define Connectivity Reference form changes to let you enter the top cell of thenetlist.

Note: To use a netlist as the connectivity source, import the netlist into Virtuoso XL usingthe CIW command File – Import – XL Netlist.

You can click Browse to open the Library Browser to find a netlist and click on the netlistname to enter it in the Define Connectivity Reference form.

8. Click OK.

Virtuoso XL opens a schematic window showing the schematic you specified.

Defining the Design Boundary

When you initialize a layout, Virtuoso XL provides a design boundary.

To reset the default size for the design boundary, choose the layout window Design – GenFrom Source command and set the options in the Boundary section of the LayoutGeneration Options form.



To stretch, move, or delete the design boundary, use the layout editor Edit commands. Thedesign boundary must be a valid layer in the LSW and must be layer prBoundary or layercellBoundary , or else it must have the purpose boundary (by) .

To place all objects and pins inside the boundary, use the layout window Edit – Place fromSchematic command.

To draw a new design boundary, follow these steps.

1. If you are using the Layout Generation Options form to generate a new layout, turn offBoundary.

2. In the LSW, click on the prBoundary layer.

The boundary layer appears as the current layer at the top of the LSW. You can alsouse the layer cellBoundary from the Layout Generation Options form Boundarysection Layer cyclic field.

3. From the layout window, choose Create – Rectangle or Create – Polygon.

4. Draw the design boundary in the layout window where you want it placed.

❑ For a rectangular boundary, click to place one corner of the new boundary, drag themouse to place the opposite corner, and release the mouse button.

❑ For a polygonal boundary, use the cursor to click on the first point, each corner point,and end point (identical to the first point) of the polygon.

The new boundary appears in the layout window.

Note: if there are multiple shapes on the prBoundary or cellBoundary layers, amessage box appears (only once) asking you to select which one is the top-level boundary.

Working with Layout Generation Templates

Layout generation templates let you

■ Save information about the I/O pins, boundary, and placement style for a particular cell

■ Reuse that information to generate and update the layout for similar cells

Templates let you set a large number of layout generation options quickly and consistently.You can apply templates to existing layout cellviews as well as to new cellviews during layoutgeneration.



Templates can contain all of the available sections or just a subset of the available sections.For example, you might use separate templates for your I/O pin constraints and yourcomponent placement style.

Creating Templates

There are two ways to create a template:

■ From the Layout Generation Options form, click Save.

You can choose to save I/O pin and boundary information.

■ Create the file with a text editor.

The easiest way to create a template is to

1. Save a template for an existing cellview

2. Edit the template file with a text editor

3. Delete the cellview-specific information

4. Save the remaining, generic information as your new template

Table 7-1 Template Sections and Contents

Template Section Scope of the Template

I/O Pins The shape and layer of the I/O pins for the generated layout

Boundary The boundary shape and layer

There are a variety of ways to define the shape, as you can seewhile you adjust the Boundary options in the Layout GenerationOptions form.

Placement All of the placement options you can set with the Place –Placement Style command.



Saving and Loading Templates

You can save and load templates while working with several different commands and forms.The type of template information you can save or load depends on what is appropriate to thecurrent task.

Modifying Templates

To modify templates, edit the file with a text editor. Follow the syntax rules described in LayoutGeneration Template File Syntax.

Templates do not remain associated with cellviews after you save or load them. In otherwords, modifying a template file has no effect on any cellview until you load it into thatcellview.

Loading Template Files

To load existing information about pins, the design boundary, and/or placement style from atemplate file into your layout, follow these steps.

1. From the layout window, choose Design – Gen from Source.

2. At the bottom of the Layout Generations Options form select Load.

Table 7-2 Commands and Template Sections

This Command... Lets You Save and Load ThisTemplate Information...

Design – Gen From Source Pin and Boundary

Connectivity – Update – Components and Nets Pin and Boundary



The Load Template File form appears.

The Name field shows the default template name, layout_cell_name .lxt .

3. Click on the directories in the left list box to descend into your file hierarchy until youreach the name of the template file to use.



The left and right arrows at the right side of the form let you go up and down in the filehierarchy.

4. Click on the name of the template file in the right list box to enter it in the Name field.

5. In the Load sections area, turn on the sections of the template file you want to load(I/O Pins and Boundary).

6. In the Existing data area, turn on Merge if you want to merge the information from thetemplate with the placement data already in virtual memory or turn on Replace if youwant to replace the placement data in virtual memory with different placement data in atemplate file.

7. Click OK.

The values in the template you selected are loaded into the Layout Generation Optionsform (associated with the Gen From Source and Update Components and Netscommands), if open, and are used in the current design session. Loading the values intoone or more of these forms is the only way to get the values into the design.

Note: You can also load a template as part of Layout Generation (see Generating a Layoutwith Components Not Placed (Gen From Source)) or Update Components and Nets (seeUpdating Components and Nets (ECO Mode) in Chapter 14.

Saving Template Files

To save current information about pins and design boundary from a template file into yourlayout, follow these steps.

1. From the layout window, choose Design – Gen from Source– .

2. At the bottom of the Layout Generation Options form select Save.



The Save Template File form appears.

3. Click on the directories in the left list box to descend into your file hierarchy until youreach the directory in which you want to store the template file.

The left and right arrows at the right side of the form let you go up and down in the filehierarchy.

4. You can accept the default template filename that appears in the Name field,design_name. lxt or type a template filename you choose.



5. Turn on the sections of the template file you want to save (I/O Pins or Boundary).

6. Click OK.

The data you selected is saved in the template file.

Note: You can also save a template as part of Layout Generation. (see Generating a Layoutwith Components Not Placed (Gen From Source)) or Update Components and Nets (seeUpdating Components and Nets (ECO Mode) in Chapter 14).



Layout Generation Template File Syntax

Layout generation templates generally follow the syntax rules for technology files, but they arenot technology file fragments. Refer to the Technology File and Display Resource FileUser Guide for information about white space, line breaks, case sensitivity, quotation ofarguments, and similar syntax rules.

Templates contain these sections:

■ Boundaries Section

■ I/O Pins Section

A template may contain some or all of these sections.

General Syntax Rules

The following rules apply throughout the template file:

Comments

Begin comment lines with a semicolon (;).

; This is a comment

Layer Names

Specify layer names as either a layer name string or as a list containing the layer name andpurpose.

met1

met2

(metal1 drawing)

Numeric Values

Specify numbers as floating-point or integer values or as expressions based on design rulesin the technology file.

(minWidth metal1)

(minSpacing poly)



Layer names can be omitted if the layer is defined and not ambiguous. When you refer to theminWidth and minSpacing rules without specifying a layer, they must be enclosed inparentheses even though you are not expressing a list.

(minWidth)

(minSpacing)

Points

Specify points as a pair of coordinates, either numbers or expressions. The syntax is

( x y )

For example:

((minWidth met1) (minWidth met1))

((minSpacing met2) 3)

Offset Points

Specify offset coordinates in a sequence of points as a relative shift from another point. Thekeyword D identifies offset coordinates. The syntax is

(D x y )

For example:

(D 3 5)

(D (minWidth met1) 7)

Sequences of Points

Specify a sequence of points as a list of points or offsets.

(0 0) (D 10 0) (D 0 20) (D -10 0)

(D 10 0) (D 0 10) (D -10 0)

If the first item is an offset, the entire list must be composed of offsets.

Polygons

Specify polygons using the polygon keyword followed by a sequence of points. The syntax is

(polygon sequence_of_points )



The last point of the sequence is always connected by an edge to the first one, even if suchan edge does not appear in the sequence. Clockwise and counterclockwise orders are bothacceptable. Polygons characterized by a sequence of offsets (no fixed points) are calledfloating polygons. If a floating polygon is encountered in a context where a non-floatingpolygon is expected, the first point is implicitly set to (0 0) .

The following examples all describe the same polygon

(polygon (0 0) (D 10 0) (D 0 20) (D -10 0))

(polygon (0 0) (D 10 0) (10 20) (D -10 0))

(polygon (0 20) (0 0) (10 0) (10 20))

Rectangles

Specify rectangles using the rectangle keyword and the options in the table below. Thesyntax is

(rectangle options )

No option can appear more than once.

Table 7-3 Rectangle Specification Options

Option Meaning

aspect_ratio X Ratio between width and height. X must be a number.

height H Absolute height of the rectangle. H can be a number or adesign rule.

width W Absolute width of the rectangle. W can be a number or adesign rule.

lowerLeft point Position of the lower-left corner.

upperRight point Position of the upper-right corner.

left X Position of the left side.

right X Position of the right side.

bottom Y Position of the bottom edge.

top Y Position of the top edge.

center point Position of the center of the rectangle.



Rectangles you define without using any of the center , upperRight , or lowerLeftoptions are floating rectangles. The shape of floating rectangles is defined, but not theirabsolute position. If a floating rectangle is encountered in a context where a nonfloating oneis expected, its lower-left corner is implicitly set to (0 0) .

Below are some examples.

(rectangle aspect_ratio 1.1 height 300 lowerLeft (0 0))

(rectangle width 30 height 20 upperRight (375 66))

(rectangle width 100 aspect_ratio 1) floating rectangle

Shapes

A shape is a polygon or rectangle on a particular layer.

(shape (layer layer_name ) (rectangle options ))

(shape (layer layer_name ) (polygon sequence_of_points ))

A shape that is a floating rectangle or a floating polygon is called a floating shape.

Layers can also be defined externally, within the scope of the option using a shape for its owndefinition. A layer defined as part of the shape definition overwrites all external layerdefinitions.

Boundaries Section

The boundaries section defines the shape of the boundary. The syntax is

boundary_section(

[(boundary options )]

)

Boundaries Options

The options are

shape The shape outlining the boundary. By default, the shape is arectangle with the aspect ratio defined by initAspectRatio inthe .cdsenv file. By default, or if the shape is floating, the lowerleft corner is placed at (0 0) .



layer layer_nameThe boundary layer name. The default is prBoundary .

utilization N The area utilization factor. This factor is used to compute theboundary size for rectangular boundaries that do not fully definethe size in the shape options. The value is ignored for polygonalboundaries and for rectangular boundaries whose shape optionsfully specify the dimensions. The default is the value ofinitUtilization in the .cdsenv file.

Below is an example boundary definition:

boundary_section(

(boundary

(shape (layer prBoundary) (rectangle aspect_ratio 1.1))

(utilization 0.25)

)

)

Below is a second boundary example:

boundary_section(

(boundary

(layer ("prBoundary" "boundary"))

(utilization 0.250000)

(shape (rectangle aspect_ratio 1.000000 lowerLeft (0.00.0)))

)

)

I/O Pins Section

The I/O pins section defines the shape and layer of the I/O pins for the new layout. The syntaxis

I/O_section(

[ global_pin_options ]...

[(pin { pin_name | ( pin_name1 pin_name2 ... )}pin_options )]...

[ changes to global pin options ]



[ more pins ]...

)

Every pin entry has one or more pin names, corresponding to net names for which pins aredefined. Pins have one or more options. Global options appear outside of a pin entry andare overridden by corresponding pin-specific options. Changes to global options apply tosubsequent pins (unless the pins each set a value for the corresponding option).

The global options in effect at the end of the I/O pins section apply to all pins not defined inthe template.

Pin Options

The pin options and global pin options are identical, except that you cannot use expressionsthat evaluate to pin-specific values (such as pin width values based on minWidth ) in theglobal options. The following options are available:

(multiplicity N)Number of pins for the given net(s). If N is greater than 1 ,all pins are identical. The default is 1.

(layer layer_name )Layer for these pins. Every geometric pin must have a layerspecification. This option can be used only with geometric pintypes.

(symbolic pin_name )Symbolic pin name. This option can be used only with symbolicpin types.

(shape shape )The pin shape, a floating rectangle. The default shape is afloating rectangle with size equal to the minimum width for the pinlayer. Size can be expressed using device rules, including theimplicit ones, because the layer specification is always providedwith pins. With symbolic pins, it is an error to specify anything butthe width.

(type pin_type )The pin type. Valid values are geometric or symbolic . Thedefault is geometric .



(position pos_spec )The pin position. By default, the pin is placed in the same relativeposition as in the schematic. Valid values for pos_spec are(left) , (right) , (top) , (bottom) , (edge num) , ( xx_value) , ( y y_value) , ( order num) .

You can specify the position as left , right , top , or bottomfor a rectangular region, or as an edge number for any shape ofregion. The edge number num is the lower index of the edge’stwo end points relative to the point ordering when the polygonwas defined (in the case of rectangles, edge 0 is the left, edge 1the top, edge 2 the right, and edge 3 the bottom). Position can,instead of or in addition to an edge position, be (x x_value )and/or (y y_value ) . If overspecified (for example, left aswell as y), the absolute coordinate takes precedence. Theorder specification indicates the ordering along the appropriateedge (0 being left or bottom).

Each of the arguments (pin_name , layer_name , etc.) is a simple argument, which appliesto all the pins denoted by the identifier.

Pin Definition Examples

Below are some pin definition examples:

(pin (net1)

(layer metal1)

(shape (rectangle (minWidth)))

)

(pin "Vdd"

(layer metal1)

(shape (rectangle width 3 height 3))

)

(pin "Gnd"

(layer metal2)

(shape (rectangle aspect_ratio 1.0 width 25))

)



I/O Section Examples

In this example, MET1 is the default layer for pins A, B, and C. MET2 is the default layer for Dand E. All other pins, whether or not they are named in the template, will have MET2(the mostrecent choice) as the default layer when you open the Layout Generation Options form.

(I/O_section

(layer MET1)

(pin A ...)

(pin B ...)

(pin C ...)

(layer MET2)

(pin D ...)

(pin E ...)

)

In the next example, pins A, B, and C are on layer MET1. Their size is the minimum width ofthat layer. Pins Vdd and Gnd are on layer MET2. Their size is 10x10.

All the remaining pins in the cell (one for every net with an I/O terminal) are on POLY. Theirsize is the minimum width of POLY.

(I/O_section

(layer MET1) (minWidth)

(pin (A B C) )

(layer MET2)

(pin “Vdd” width 10 height 10 )

(pin “Gnd” width 10 height 10 )

(layer POLY)

)

Sample Template

boundary_section(

(boundary

(layer ("cellBoundary" "boundary"))

(utilization 0.300000)

(shape (rectangle width 100.000000 lowerLeft (0.0 0.0)))



)

)

I/O_section(

(type "geometric")

(layer ("pdiff" "pin"))

(shape (rectangle width 1.000000 height 1.000000))

(multiplicity 1)

(pin "gnd!"

(layer ("metal1" "pin"))


(position (top))

)

(pin "in"



(position (right) (order 0))

)

(pin "out"



(position (right) (order 1))

)

(pin "vcc!"



(position (bottom))

)

)



Generating a Layout with Components Not Placed(Gen From Source)

To place design elements from the schematic in an empty layout window or to clear the layoutwindow design area so you can start over, follow these steps.

The Layout Generation Options form displays default values each time it opens, it does notcarry over values from the previous entry. If you want to use values from a previous entry, youmust save these values to a template and then use the Load option on the form to open thetemplate and update the fields in the form with the information in the template.

Note: Layout generation does not maintain the value of the lxMaxWidth parameter unlessall device widths and all lxDeviceWidth values are specified consistently; for example, allin meters (10 µm is 1-e-5) or all in user units (10 µm is 10).

1. From the layout window, choose Design – Gen From Source.

The Layout Generation Options form appears. For more information, see the LayoutGeneration Options Form on page 196 .

Note: The Layout Generation Options form always reflects the default settings for the



design, that is, the state of the schematic, not the entries from the previous time the formwas used.

2. In the Layout Generation section at the top of the form, do the following:

a. If you want to generate pins, instances, or a boundary as specified in the schematicor in a template file, check that the options you want(I/O Pins, Instances, Boundary) are turned on.

Note: If you want a label specifying the library, cell and view of your design just insidethe center top edge of the boundary, set the environment variablecreateBoundaryLabel .

b. If you want to recreate the abutment into stacks of MOS transistors or fingers offolded MOS transistors that were changed since you created them with the GenFrom Source command, turn on the Transistor Chaining option. This recreatesthe chains as they existed after Gen From Source with chaining on. The chainsare not moved from their existing positions; missing devices are added in theirproper position in the chain and not under the PR boundary.

c. If there are MOS transistors in the design that you want to divide into fingers, turnon the Transistor Folding option. This option automatically turns on the TransistorChaining option. This option also recreates folded transistors as they were afterGen From Source.

d. If you want to preserve existing many-to-many mapping of devices between theconnectivity source and the layout, turn on Preserve Mappings.

Note: The Preserve Mappings functionality does not report missing devices or shapeswithin a mapped group.

3. In the I/O Pins section, where the names and layers of existing I/O pins are shown(based on information in the technology file), specify any pin values you want to add orchange.

a. For geometric I/O pins, choose the routing layer for pins from theLayer/Master cyclic field. If no routing layers (lxExtractLayers ) are defined inthe technology file, a message box appears telling you so.

b. For symbolic I/O pins, choose the name of a symbolic pin from the Pin Name list ofvalid symbolic pins defined in the technology file. If no symbolic pins are defined inthe technology file, the symbolic option does not appear on the Pin Type cyclic field.

c. If you do not want a pin to appear on the layout, turn off its Create button.



d. To generate name labels for each design element, turn on Pin Label Shape –Label. (You must first turn on the Display Pin Name option on the form associatedwith the layout editor Create – Pin command.)

e. To set the style of the pin labels, click Display Pin Name Option

The Set Pin Label Text Style form appears.

f. Choose the options you want from the Set Pin Label Text Style form and click OK.



4. In the Boundary section of the Layout Generation Options form, if you want Virtuoso XLto draw a boundary, follow these steps.

a. In the Layer field, choose the layer you want to use for the boundary.

b. In the Shape field, choose Rectangle or Polygon.

To specify the dimensions of a rectangular boundary, you can use only two of thefollowing four values: Utilization (%), Aspect Ratio (Width/Height), BoundaryWidth, or Boundary Height. You can also type in the Points field values for theLeft (Y coordinate) side of the boundary and the Bottom (X coordinate) side of theboundary in this format: (0 0) (10 10).

To specify the dimensions of a polygonal boundary, choose Polygon from theShape field and type the X and Y coordinates of each corner of the polygon in thePoints field in the following format. For example, for a rectangle, type: (0 0) (010) (10 8) (8 0) (0 0) .

When you move the cursor in the layout window, the X and Y coordinates of thelocation of the cursor are displayed in the Status Line at the top of the layout window.

should be “dw”PCR266503



5. In the Template File section, to load a template file (an ASCII file containing theinformation entered in this form in a previous session and saved to a file), follow thesesteps.



a. Click Load.

The Load Template File form appears.

This Load Template File form has the same look and functionality as the LoadTemplate File form that you get from the layout window Design – Template – Loadcommand.



b. Click on the directories in the left list box to descend into your file hierarchy until youreach the name of the template file to use.

c. Click on the name of the template file in the right list box to enter it in the Name field.

The left and right arrows at the right side of the form let you go up and down in thefile hierarchy.

d. Click OK.

The values in the file are loaded into the Layout Generation Options form and areused during the design session.

You can set an environment variable, templateFileName , to always load thename of a template you specify as the value of the variable.

6. In the Template File section, to save the information you enter in the Layout GenerationOptions form to a template file (an ASCII file) to use in a later session, follow these steps.



a. Click Save.


b. Click on the directories in the left list box to descend into your file hierarchy until youreach the directory in which you want to store the template file.




c. Accept the default template file name that appears in the Name field,design_name .lxt , or type a template filename you choose.

d. Turn on the sections of the template file you want to save (I/O Pins, Boundary, orPlacement).

e. Click OK.


Note: When you use the Gen From Source command, constraints entered for layoutdevices are preserved. When you use the Virtuoso layout editor commands Design –Discard Edits and Design – Open, however, constraints entered for layout devices arelost unless you first save all changes made to the design.

Caution

Before you click OK in the Layout Generation Options form, rememberthat clicking OK in this form deletes everything in the layout window.

7. Click OK in the Layout Generation Options form.

If you already have design elements in the layout window, a message box warns you thatthis command deletes all layout instances and wiring in the design.

8. Click Yes on the message box.

Virtuoso XL places the device equivalents of the schematic symbols and the pinequivalents of the schematic terminals below the new design boundary.

Virtuoso XL uses a compact placement for the design elements that corresponds to theschematic placement.

If there are no layout instances for components in the schematic, the missingcomponents are reported in a Virtuoso XL Info text window.

Note: If you do not have layout pins for global nets in the schematic and you want to createthese pins in the layout, set the initGlobalNetPins environment variable to t in your.cdsenv file before you start Virtuoso XL.

Note: If you are using inherited connections in your design to assign more than one value toa global net, remember that the netSet properties on schematic instances, which specifythe new value of a global signal, are not copied over with the instance from the schematic tothe layout when you use the Gen From Source, Pick from Schematic, or Update LayoutParameters command.



Mismatched Pins

If a symbol in a schematic has more pins than the corresponding device on the layout,Virtuoso XL generates a warning about mismatched pins.

If you want Virtuoso XL to ignore a pin on an instance in the schematic during layout and notgenerate a warning about mismatched pins for it, follow these steps.

1. Descend into the symbol of the instance and add a Boolean property, named whateveryou choose (for example, unusedPin ) and set to t , on the pin.

2. Add that property name (for example, unusedPin ) as a value in the ignoreNamesenvironmental variable in your .cdsenv file

layoutXL ignoreNames string "unusedPin"

or you can type it in the CIW

envSetVal("layoutXL" "ignoreNames" 'string "unusedPin")

The software will not issue a warning of pin mismatches or missing pins during layoutgeneration or when you run the Check – Against Source or Update – Componentsand Nets command.

Placing Components in a Layout in the Same RelativePosition as in the Schematic (Place from Schematic)

To place all components (or all components you select) inside the design boundary of thelayout window in the same relative position as they are in the schematic, follow these steps.

Caution

If you have already created stacks of transistors manually using theCreate – Pick From Schematic or the Edit – Transistor Chaining or Foldingcommands or the Transistor Chaining and Transistor Folding options onthe Layout Generation Options form (the Gen From Source command),the stacks of chained transistors created will be broken by the Place fromSchematic command, which places transistors in the order they occur inthe schematic

➤ From the layout window, choose Edit – Place from Schematic.

Virtuoso XL automatically moves all the components into the design boundary accordingto the relative locations of the symbols in the schematic.



If some objects in the design, such as pins, are much smaller in size than other objects,such as components, the small objects might not appear in the layout, even though theyhave been moved. You need to zoom in to see these smaller objects.

If there is no design boundary, Virtuoso XL places the devices within a square the sizeof the default boundary (25% utilization).

I/O pins will not move. To move the I/O pins so that they align to the edges of the designboundary use the Placer-Pin Placement command.

Note: When placing components within the design boundary, the Place from Schematiccommand might cause the components to overlap, resulting in shorts. When you create ashort, Virtuoso XL displays a marker over the short.

Virtuoso XL does not compact the layout, so the placement of components might not meetDesign Rule Checker (DRC) or other design requirements.

Constraints entered using the Constraint Editor are not observed by the Place fromSchematic command.

Moving Components from the Schematic into the Layout(Pick from Schematic)

To place devices and/or pins directly from the schematic into the layout, follow these steps.(If your connectivity reference is not a schematic, you cannot use this command.)

1. From the layout window, choose Create – Pick from Schematic.

The first time you open a new design and use this command, the Define ConnectivityReference form appears.

2. If the Define Connectivity Reference form appears, type the library, cell, and view nameof the schematic from which you want to pick elements to place in the layout (if thisinformation is different from the information that appears by default in the form) and clickOK.



The Pick from Schematic form appears.

Placing a Group of Schematic Elements Together

To move a group of components together into the layout in the same relative position as in theschematic, follow these steps.

1. In the Pick from Schematic form, turn on Group As In Schematic.

In this mode, you cannot change the parameters of the components.

2. Select a group of components (or all the components) in the schematic.

If some components in the schematic are already present in the layout, you cannot selectthem; only those components not yet placed can be selected.

3. Turn on the options you want.

Draglines displays rubberbanding lines that connect pins of the object you are movingto pins of the nearest objects.

Constraint Assisted allows objects to be moved only in ways that satisfy the constraintsentered using the Constraint Editor, once the object has satisfied the constraint.



Transistor Chaining allows MOS transistors (or fingers of folded transistors) to beautomatically abutted to form a stack.

Transistor Folding allows MOS transistors to be automatically divided into fingers foroptimum area usage.

NMOSMaxWidth lets you type in the maximum size of the folded NMOS transistor. Thisvalue defaults to the lxMaxWidth value set on the connectivity source component.

Changing this value overwrites the lxMaxWidth value you entered in the EditComponent Type form associated with the Place – Component Types command.

PMOSMaxWidth lets you type in the maximum size of the folded PMOS transistor. Thisvalue defaults to the lxMaxWidth value set on the connectivity source component.


4. To see a list of the components in the schematic that are not yet placed in the layout, clickUnplaced.

The Pick from Schematic Component/Pin List appears.

5. In the list box, click on the names of the devices you want to place.

6. Move the cursor into the layout window and click.



The group of components selected are placed in the layout in the same relative positionas in the schematic.

Only components not yet present in the layout can be placed.



Placing Individual Components

To place individual components from the schematic in the layout, follow these steps.

1. In the Pick from Schematic form, turn on Place Individually.

The Pick from Schematic form changes to let you select individual instances.

2. In the schematic, click on the component or group of components you want to place inthe layout.

To select multiple components, click on the first object to select it and Shift click on theother objects or click and drag over the objects. You can deselect objects with Controlclick.

Selected objects in the schematic remain highlighted until they are deselected or placedin the layout.

You cannot select objects in the schematic if objects with the same name are alreadypresent in the layout.



3. Turn on the options you want.

4. Move the cursor to the layout window.

The component to be placed first is highlighted in the schematic in the color assigned tothe hilite drawing2 layer. Selected instances that have not yet been placed arehighlighted in the color assigned to the hilite drawing layer.

The outline of the component follows the cursor in the layout. Rubberbanding drag lines,showing connectivity to already placed components, follow the component outline.

The Pick from Schematic form changes to show the parameters associated with thecomponent currently being placed.

If the components you selected are pins, the Pick from Schematic form changes toinclude pin options you can choose.

5. Click in the layout where you want to place the component.

The component is created where the image was when you clicked and has theconnectivity indicated in the schematic.

6. If you selected more than one component, without moving the cursor back to theschematic, click to place the other components in the layout.



The instances are placed in the layout at the location where you click. The instancecurrently being placed in the layout is always highlighted in the schematic in the colorassigned to the hilite drawing2 layer. Selected instances that have not yet beenplaced are highlighted in the color assigned to the hilite drawing layer.

You can use the Next and Previous buttons at the top of the Pick from Schematic formto move ahead or back in the order of the list of components you picked.

7. To see a list of all components in the schematic for which there is no corresponding layoutinstance or pin, click Unplaced.

Wires, labels, text, instances with ignore properties, and instances that have alreadybeen placed in the layout are not considered available components and are not shownin this list.

8. Double-click on the name of each device in the list and move the cursor to the layout toplace it.

The Pick from Schematic form changes to show available information about thatcomponent.

Constraints entered using the Constraint Editor are observed while you are using thePick from Schematic command.

9. To exit this command, click Cancel on the Pick from Schematic form.

Note: If you are using inherited connections in your design to assign more than one value toa global net, remember that the netSet properties on schematic instances, which specifythe new value of a global signal, are not copied over with the instance from the schematic tothe layout when you use the Gen From Source, Pick from Schematic, or Update LayoutParameters command.



Abutting Devices Using Pick from Schematic

To use the Pick from Schematic command to abut devices that are set up for abutment,follow these steps.

1. From the layout window, choose Options – Virtuoso XL.

The Virtuoso XL Options form appears.

2. Ensure that the Auto Abutment and Connectivity Extractor options are turned on.

3. Click OK.

4. Set the two environment variables to control how automatic abutment works in yourdesign.

5. From the layout window, choose Create – Pick from Schematic.

The Pick from Schematic form appears.

6. In the schematic, select the instances you want to place.

7. Click on the layout where you want to place the instances.

The software places the selected instances where you click in the order that you selectedthem.

8. Where flight lines indicate abutment is possible, place devices so that the pins overlap.

The devices are abutted.

Cloning Components

Cloning is the ability to replicate a section of the layout that is associated with a section of theschematic in such a way that the new piece of layout material can be placed at more than onelocation in the layout with each part preserving the hierarchical structure of the design. Youcan clone devices, pins, and (if selected from the layout window) interconnect structures suchas wires and paths made of shapes.

Cloning differs from copying in that cloned structures include connectivity information.

The connectivity structure of the section being copied needs to match the cloned copies in

■ Topological structure

■ Instance master



■ Instance parametersThe section of the schematic or layout that is used as a template for the cloning is calledthe source, and the section of the schematic that is to be implemented by copying thesource is the target. The result of copying the source to implement the target structure isthe clone.

To select a section of a design from either the schematic or the layout to be used as thesource for an analogous structure elsewhere in the layout, follow these steps.

1. From the layout window, choose Create – Clone.

The CIW and the layout window prompt you to select the connectivity source and target.

The Cloning form appears.

2. In the schematic window or the layout window, select the structure you want to copy (theconnectivity source).

The structure you select as a source in the schematic must be implemented in the layout.If you select the source structure from the layout, you can copy shapes and wiring, aswell as instances. As part of the same source, you can select both instances from theschematic and shapes from the layout. Shift click to select more than one object.



For example, in the diagram below, you might select R1, R2, and Q1 as sourcecomponents.

3. Click Conn. Source.

The CIW prints an acknowledgment that a connectivity source was selected.

4. In the schematic, click on the structure(s) you want to use as the target.

You can select more than one target structure to implement using the source.

R1

R2

R6

R7R5

R4

R3

C1

C2

Q2Q1

vcc!

gnd!

in

out



For example, in the diagram below, you might select R4, R5, and Q2 as targetcomponents.

You cannot use elements that already appear on the layout as target structures; thesoftware ignores and does not place them.

If you select components that do not match the structure of the source, thesecomponents are not included in the target structure and are not generated.

5. Click Clone.

The source and the target structures are highlighted in color in the schematic. The CIWlists the elements in the source and the elements in the target.

As you select more than one matching target, the Total Matches count in the Statusarea on the Cloning form updates to show how many areas you have chosen.

The CIW and the layout window prompt line prompt you to click where you want to placethe clone in the layout.

6. Move the cursor to the layout window.

The outline of the layout structure follows the cursor.

7. In the Cloning form, select the placement options (Rotate, Sideways, Upside Down,Highlight/Dehighlight) that affect the placement or appearance of the clone.

8. Click in the layout to place the cloned structure where you want it.

The cloned structure is placed in the layout.

R1

R2

R6

R7R5

R4

R3

C1

C2

Q2Q1

vcc!

gnd!

in

out



9. If you selected more than one target structure, click Next on the Cloning form and movethe cursor to the layout window again to place the next target.

The outline of the layout structure follows the cursor.

Note: You cannot use structures in the layout that use many-to-one mapping as theconnectivity source for cloning. If you select a many-to-one structure to use as aconnectivity source, a warning appears in the CIW explaining the error and the structureis not selected

10. Click in the layout to place the next structure.

The cloned structure is placed in the layout. The Current Match count in the Statusarea on the Cloning form updates to show how many of the clones you have placed outof how many are in the stack..

You can see all clones selected at the same time highlight sequentially by clicking on thePrevious or Next button on the Cloning form.

11. To exit this command, move the cursor to the layout window and press Escape or clickCancel in the Cloning form.

Troubleshooting

If the target cannot be cloned, an outline of the layout structure does not appear and amessage box opens.

You need to check whether



❑ The structure or part of the structure that you selected as the target already existsin the layout, as if, in the example below, R1, R2, and Q1 in the layout were thesource components and R4 (which is already implemented), R5, and Q2 were thetarget components.

❑ The connectivity structure of the source and the target is not the same; for example,if you chose R1, R2, and Q1 as source components and R6, R7, and Q2 as targetcomponents.

❑ The master cell of the source and the target instances are not the same

R1

R2

R4

Q1

R5

Q2

Cannot be placedas clones ofR!/R2/R5combinationbecasue R4 is alreadyplaced.

R1

R2

R6

R7R5

R4

R3

C1

C2

Q2Q1

vcc!

gnd!

in

out



❑ More source components are selected than target components; for example, if youselected R1, R2, and Q1 as source components and selected only R4 and Q2 fortarget components

❑ The properties of the source and target instances are not the same; for example, youcould not use R1 and R2 in this diagram to clone R4 and R5 because theirresistance value properties are different.

R1

R2

R6

R7R5

R4

R3

C1

C2

Q2Q1

vcc!

gnd!

in

outr=5Kr=5K r=5K

r=5K r=10Kr=5K

R1

R2

R6

R7R5

R4

R3

C1

C2

Q2Q1

vcc!

gnd!

in

outr=10Kr=5K r=5K

r=2.5K r=2.5Kr=5K



The target instance can have properties that are in addition to the properties of thesource instance, but the target instance must have all the same properties with thesame values as the source instance has. In the example below, you can use R1, R2,and Q1 as source components to clone R4, R5, and Q2 because the targets havethe same properties and values as the sources, even though one of the targets hasadditional properties.

You can assign the property lxIgnoredParams to source instances withproperties that are different from the target instance properties, so that the sourceinstances can be cloned successfully as target instances.

Cloning Using Multiple Cellviews

You can place a clone in a different layout from the one in which you selected the source onlyif

❑ You select the all the source objects from the layout from which you started theClone command (or the corresponding schematic)

❑ The second layout has the same connectivity source as the first layout

To clone an object in one layout cellview into another layout cellview that has the sameconnectivity source, follow these steps.


R1

R2

R6

R7R5

R4

R3C1

C2

Q2Q1

vcc!

gnd!

in

outr=5Kr=5K r=5K

r=5K r=2.5Kr=5K

l=5w=3



2. In the layout window from which you started the Clone command (or the ccorrespondingschematic), select the structure you want to copy (the connectivity source).

3. Click Conn. Source.

4. In the schematic, click on the structure(s) you want to use as the target.

5. Click Clone.

6. Move the cursor to the layout window in which you want to place the clone.

The connectivity source for this layout must be the same as the connectivity source forthe layout from which you strted the clone command.

7. Click in the layout to place the cloned structure where you want it.

If you select source objects from more than one layout cellview, an error message appearstelling you that you can select source object only from a single layout view, the one from whichyou started the Clone command.

Using Correspondence Points

Correspondence points are matching pairs of locations in the schematic. You definecorrespondence points to help you locate the structures you want to clone. Once you definethe correspondence points, they are highlighted in bright colors.

You select pairs of items—R1 and R7—for example, to be stored in a correspondence pointsfile, a standard text file containing net and device names. You can create any number of fileswith different names and then specify in the Correspondence Points form which one you want.

Creating Correspondence Points

To create a correspondence points file, follow these steps.




The Cloning form appears.

2. Turn on Correspondence File.

The Correspondence File field becomes active.

3. If you want to use a file other than the default file, type the name of the correspondencefile you want to create.

4. Click Create.

The Correspondence Pairs form appears.

5. The Working File field displays the name of the correspondence points file displayed inthe Cloning form.

6. Click Add.



The Add Correspondence Pairs form appears.

7. Type the component names or click Set By Cursor and select in the schematic thenames of the two components you want to correspond.

8. Click Apply.

The information is added to the end of the correspondences file (lvs_corr_file ) orother file you specified. Information at the end of the file (the most recent information)overrides any correspondence points information earlier in the file.

Displaying Correspondence Points

To display the correspondence points that you have entered in the correspondence points file,follow these steps.

1. On the Correspondence Pairs form, click Display.

The Display Specific Correspondence Components form appears.

2. Turn on Source or Target to choose the point you want to display.



3. Type, or click in the schematic or layout, to specify the name of the point you want todisplay.

4. Click Apply.

The correspondence points you specified are highlighted in the schematic.

To display all the points in the correspondence points file

➤ In the Correspondence Pairs form, click Display All Pts.

All the correspondence points in the correspondence points file are highlighted in theschematic.

To remove the highlighting on all the points in the correspondence point file

➤ In the Correspondence Pairs form, click Clear All Pts.

The highlights are removed from correspondence points in the schematic.

Removing Correspondence Points

1. To remove correspondence points, in the Correspondence Pairs form, click Remove.

The Remove Correspondence Components form appears.

2. Choose whether you want to remove the Source or Target point.

3. In the Name Of Point field, type the name of one of the correspondence points.

4. Click Apply.

The correspondence points are removed from the bottom of the correspondence file.

If a correspondence point has several corresponding points, all of its correspondencepoints are removed.




Add Correspondence Pairs Form on page 190

Cloning Form on page 191

Correspondence Pairs Form on page 192

Define Connectivity Reference Form on page 193

Display Specific Correspondence Components Form on page 194

Import XL Netlist Form on page 195

Layout Generation Options Form on page 196

Load Template File Form on page 199

Pick from Schematic Form on page 200

Remove Correspondence Components Form on page 203

Save Template File Form on page 95

Set Pin Label Text Style Form on page 205

Startup Option Form on page 206



Add Correspondence Pairs Form

Name in Connectivity Source lets you type the name of the connectivity point you want tobe the source when you click Apply.

Name in Connectivity Target lets you type the name of the connectivity point you want tobe the target when you click Apply.

Set By Cursor lets you indicate by clicking on a point with the cursor the name of the pointyou want added when you click Apply.



Cloning Form

Options

Draglines enables rubberbanding lines showing the closest possible connections tonets.

Constraint Assisted turns on any constraints entered through the Constraint Editor.

Status

Total Matches shows how many components or structures were chosen as targetstructures for cloning.

Current Match shows how far along in the number of total matches to be placed thetarget currently being placed is.

Correspondence File activates the Correspondence File field, to let you type in a namefor a correspondence file, if you do not want to use the default name, lvs_corr_file.

Create opens the Correspondence Pairs form, which lets you add correspondence points.

Rotate rotates the component or structure to be placed 90 degrees counterclockwise.

Sideways mirrors the component or structure to be placed on the Y axis (flips it horizontally).

Upside Down mirrors the component or structure to be placed on the X axis (flips itvertically).

Conn. Source lets you indicate by clicking in the schematic the components or structuresthat you want to be the sources for cloning.

Clone lets you indicate by clicking in the schematic or layout the component or structures thatyou want to be the targets for cloning.

Highlight puts a highlight on each pair of correspondence points.



Correspondence Pairs Form

Working File lets you accept the default name of the Correspondence Points File(lvs_corr_file ) or type a different name.

Add opens a form that lets you add correspondence points to the Correspondence PointsFile.

Remove opens form that lets you delete correspondence points from the CorrespondencePoints File.

Display opens a form that lets you display individual correspondence points from theCorrespondence Points File.

Display All Pts opens a list box that shows all the correspondence points in theCorrespondence Points File.

Clear All Pts clears all correspondence points from the Correspondence Points File.



Define Connectivity Reference Form

Source specifies the connectivity source for the design.

Schematic indicates that a schematic is the connectivity reference for the design.

Netlist indicates that a netlist is the connectivity reference for the design.

None indicates that there is no connectivity reference for the design.

Library defaults to the name of the library in which the layout was opened. You can type ina different library name.

Cell lets you type in the name of the cell you want to use as a connectivity reference.

View defaults to schematic . You can type in a different view name.

Browse displays the Library Browser, which lets you click on names to fill in the form. Evenif the Library Browser is already open, you must click Browse if you want the names youclick on to appear in the form.

Sel by Cursor lets you specify the schematic or layout to use by clicking in the open cellviewwindow.

Top Cell (appears only if you choose Netlist as the source) lets you enter the top cell of thenetlist.



Display Specific Correspondence Components Form

Identify Connectivity

Source sets the software to display the connectivity point identified as the source whenyou click Apply.

Target sets the software to display the connectivity point identified as the target whenyou click Apply

Name Of Point lets you type the name of the point you want displayed when you click Apply.

Set By Cursor lets you indicate by clicking on a point with the cursor the name of the pointyou want displayed when you click Apply.



Import XL Netlist Form

Netlist File specifies the name of the file to use as a netlist.

Copy copies the imported netlist file to the destination library location.

Link links the imported netlist file to the destination library location.

Move moves the imported netlist file to the destination library location.

Mapping File specifies the name of a file that contains netlist-to-layout mapping information;for example, a netlist resistor named r1 mapping to the layout cell name res. The mappingfile must follow a predetermined structure.

Library specifies the name of the library in which you want to put the netlist.

Cell specifies the name of the cell in which you want to put the netlist.

View specifies the view name in which you want to store the netlist.

Browse opens the Open File form if your cursor is in the Netlist File field or the MappingFile field. From the Open File form, you can choose any file to which you have access. If yourcursor is in the Library or Cell or View fields, the Browse button opens the Library Browserform, from which you can choose a library, cell, and view.



Layout Generation Options Form

Layout Generation

Generate:

I/O Pins places all the pins specified in the Layout Generation Options form.

Instances places all the instances in the schematic that do not have Ignore propertiesattached to them.

Boundary generates a design boundary using the layer and size information you specify inthe Boundary section of this form.

Transistor Chaining enables the abutment of ordered lists of MOS transistors into stacksand places them in the design.

Transistor Folding enables the division of MOS transistors into sections if necessary tominimize design area and places them in the design. When transistor folding is turned on,transistor chaining is automatically turned on also.

Preserve Mappings , if turned off, ignores previous many-to-many, many-to-one, and one-to-many mappings.

I/O Pins

Add a Pin adds a pin to the I/O Pins section of the form and to the layout after you click OK.

Apply Pin Defaults applies to all pins the default values shown in the form on the top pinrow, labeled Defaults.

Hide Disabled Pins removes from the form the information about pins for which you haveturned off the Create button. When you click this button, the button text changes to ShowDisabled Pins.

Show Disabled Pins adds to the form the information about pins for which you have turnedoff the Create button. When you click this button, the button text changes to Hide DisabledPins.

Net Name specifies the name of the net to which the pin belongs.

Pin Type lets you specify the type of pins to be placed.

Geometric specifies the layer on which you want to place the pins from the Layer/Master cyclic field below.



Symbolic lets you choose the name of a symbolic pin cell from the Layer/Master cyclicfield. If there are no symbolic pins defined in the technology file, this option is notavailable. If you choose this option, the Width field disappears (because symbolic pinsare square).

Layer/Master lets you choose

■ The layer for geometric pins.The default is the current drawing layer if it is defined as lxExtractLayer in thetechnology file. Otherwise, the default is the first layer defined as lxExtractLayer ,and the cyclic field offers only the conducting layers. If no layers have been defined aslxExtractLayer , the cyclic field shows all valid layout layers.

■ The master for symbolic pins.If there are no valid symbolic pins defined in the technology file, none are shown in thecyclic field and the Symbolic Pin Type option is not available.

Width specifies the width for each pin. The default is the minWidth property value set forthe current layer in your technology file.

Height specifies the height for each pin. The default is the minWidth property value set forthe current layer in your technology file.

Num specifies how many instances of this pin to create. If you type 0 in this field, the pin isnot created.

Create , when on, specifies which of the pins listed on the form (based on pins shown in theschematic) are to be placed on the layout.

Create Pin Labels puts the names of the pins on the layout.

Display Pin Name Option opens the Set Pin Label Text Style form, which allows you to setthe size, font, style, justification, and orientation of the label lettering and the drawing or pinlayer on which the labels are shown.

Boundary

Layer specifies the layer on which you draw the cell boundary. The default is the entry layerdefined by the initBoundaryLayer environment variable. The default is the boundaryentry layer.

Shape lets you set the shape to Rectangle or Polygon.

If you set Shape to Rectangle, you can set any two of the following values to define the sizeof the cell boundary.



Utilization (%) specifies the percentage of area within the cell boundary that you wantto fill. The default is 25%.

Aspect Ratio W/H is the width-to-height ratio of the design boundary. For example, avalue of 1 specifies a square boundary, 0.5 specifies a boundary twice as high as it iswide, and 2 specifies a boundary twice as wide as it is high. The default is 1.

Boundary Width specifies the width of the design boundary. The default is the size ofthe last boundary or 10 .

Boundary Height specifies the height of the design boundary. The default is the sizeof the last boundary or 10 .

With Shape set to Rectangle, if you do not want the design boundary’s left and bottom sideslocated at the default position, you can enter new values in the Left and Bottom fields.

Left lets you enter a value on the X axis to situate the left side of the rectangle.

Bottom lets you enter a value on the Y axis to situate the bottom of the rectangle.

If you set Shape to Polygon, the form changes to let you define the number and length ofthe sides

Points is a field that lets you enter the points where the sides meet. For example the formatfor a rectangle is: (0 0) (10 0) (10 10) (0 10)

Template File

Load opens the Load Template File form, which lets you specify a file that contains storedlayout generation options to use in the current design session.

You can set an environment variable, templateFileName , to always load the name of atemplate you specify.

Save opens the Save Template File form, which lets you specify a new file in which to savecurrent layout generation options that you can use in future design sessions.



Load Template File Form

Name lets you specify the name of a template file.

Filter lets you filter the name of the files.

Load sections lets you include separate parts of the template file or, if neither of thesechoices is active, lets you use only the information about instances from the template file.

I/O Pins specifies using the I/O pins information from the Gen From Source LayoutGeneration Options form in the template file.

Boundary specifies using the boundary information from the Gen From Source LayoutGeneration Options form in the template file.

Existing data lets you choose between current and saved data.

Merge combines the values in the template file with the values currently shown in theform.

Replace overwrites the values from the template file with the values currently shown inthe form.



Pick from Schematic Form

Placement

Group As In Schematic lets you move a group of components together into the layoutin the same relative position as in the schematic. In this mode, you cannot change theparameters on the components.

Place Individually lets you move each component individually.

Note: Folding and chaining options are not availabe when using the Place Individuallyoption. Interactively fold and chain devices using Edit-Transistor Folding and Edit-Transistor Chaining.

(Options

Draglines , when active, displays rubberbanding lines that connect pins of the object youare moving to pins of the nearest objects.

Constraint Assisted , when active, allows objects to be moved only in ways that satisfythe constraints entered using the Constraint Editor, once the object has satisfied theconstraint.

Transistor Chaining , when active, allows a set of MOS transistors (or fingers of foldedtransistors) to be automatically abutted to form a stack. Transistors to be abutted must be setup for abutment first.

Transistor Folding , when active, allows MOS transistors to be automatically divided intofingers for optimum area usage. When Transistor Folding is active, Transistor Chaining isautomatically made active at the same time; Transistor Folding does not operateindependently from Transistor Chaining.

NMOSMaxWidth , when Transistor Folding is active, lets you type the maximum sizeof the folded NMOS transistor. This value defaults to the lxMaxWidth value set on theconnectivity source component.


PMOSMaxWidth , when Transistor Folding is active, lets you type the maximum sizeof the folded PMOS transistor. This value defaults to the lxMaxWidth value set on theconnectivity source component.




Unplaced opens a form displaying a list of each component in the schematic for which thereis no corresponding instance or pin in the layout.

When the Place Individually option is active, the form adds the following four fields fordisplaying information about the components you select for placement.

LibName displays the name of the library of the component you select from the list ofunplaced components or from the schematic.

CellName displays the cell name of the component you select from the list of unplacedcomponents or from the schematic.

ViewName displays the view name of the component you select from the list of unplacedcomponents or from the schematic.

InstName displays the instance name of the component you select from the list ofunplaced components or from the schematic.

When a component is selected, the form adds additional fields, depending on the componentand its attributes.

When a pin is selected, the form displays the following pin creation options.

Terminal Name displays the name of the pin first in line to be placed

Type lets you choose the type of pin to place

Rectangle Pin lets you create a rectangular pin

Symbolic Pin changes this form to let you create symbolic pins

Create Label attaches a label, showing the terminal name, to the pin.

Display Pin Name Options opens the Set Text Style form, which lets you set the font,height, justification, and orientation of the pin name.

I/O Type assigns a property used by routers to identify the direction of the signal into or outof this pin. The signal can be input, output, inputOutput (bidirectional), switch (carries dataeither in or out, but not simultaneously), or jumper (passes data through this pin).

Access Direction assigns a property used to identify the part of the pin to which routers canconnect routing. The access direction can be top, bottom, left, right, any, or none.

When a device is selected, the form displays properties set for that device.

Rotate rotates the component 90 degrees counterclockwise.



Sideways mirrors the component on the Y axis (flips it horizontally).

Upside Down mirrors the component on the X axis (flips it vertically).



Remove Correspondence Components Form

Identify Connectivity

Source sets the software to remove the connectivity point identified as the source whenyou click Apply.

Target sets the software to remove the connectivity point identified as the target whenyou click Apply.

Name Of Point lets you type the name of the point you want removed when you click Apply.

Set By Cursor lets you indicate by clicking on a point with the cursor the point you wantremoved when you click Apply.



Save Template File Form

Name lets you specify the name of a template file.

Filter lets you filter file names.

Save sections lets you specify what types of information you want to save in the templatefile or, if none of the choices are active, use only the information about instances from thetemplate file.

I/O Pins specifies saving the I/O pin information from the Gen From Source LayoutGeneration Options form in the template file.

Boundary specifies saving the boundary information from the Gen From SourceLayout Generation Options form in the template file.



Set Pin Label Text Style Form

Height sets the height of the label in user units (usually microns).

Font sets the text style of the label. The choices are euroStyle, gothic, math, roman,script, stick, and swedish.

Text Options

Drafting prevents the label from being rotated more than 90 degrees.

Overbar is a display option that determines how text strings containing underscorecharacters are displayed in a layout window.

When the overbar is disabled (default), the software displays underscore characters ( _) as part of the text string. When the overbar is enabled, the software interpretsunderscore characters ( _ ) in the text string name as toggle switches that control whereoverbars begin and end. Overbars appear above the text string, as shown in theexamples.

Layer sets the drawing layer on which the labels appear.

Pin Layer sets the pin layer on which the labels appear.

Justification sets the location of the label origin. The origin appears as a small square onthe label when you place or select it. The choices are lowerLeft, centerLeft, upperLeft,lowerCenter, centerCenter, upperCenter, lowerRight, centerRight, and upperRight.

Orientation lets you specify the orientation of the labels. The choices are R0 (no rotation),R90 (rotate 90 degrees), R180 (rotate 180 degrees), R270 (rotate 270 degrees), MX(flipped upside-down), MY (flipped sideways), MXR90 (flipped upside-down and rotated 90degrees), and MYR90 (flipped sideways and rotated 90 degrees).

Text String Appears in Design Window As

_abcde abcde

ab_cde abcde

_abc_de abcde

ab_cd_ef_gh_ij abcdefghij



Startup Option Form

Create New opens the Create New File form to let you type the name of a new layout viewfor your Virtuoso XL design.

Open Existing opens the Library Browser to let you choose the name of an existing layoutview for your Virtuoso XL design.



8Editing Your Layout with Virtuoso LayoutAccelerator

This chapter shows you how to use the Virtuoso® layout accelerator (Virtuoso XL) to edit theplacement of components in the layout and how to add additional components. This chapterdiscusses the following topics:

■ Identifying Incomplete Nets on page 209

■ Moving Objects Manually in the Virtuoso Layout Accelerator on page 213

■ Aligning Objects on page 217

■ Swapping Components on page 219

■ Permuting Component Pins on page 220

■ Using Device Locking on page 223

■ Using Automatic Spacing on page 225

■ Using Interactive Device Abutment on page 227

■ Setting Component Types on page 228

■ Using Transistor Chaining on page 233

■ Using Transistor Folding on page 236

■ Adding Pins to a Layout on page 241

■ Assigning Pins to a Net on page 243

■ Maintaining Connectivity When Editing a Flattened Pcell on page 245

For information about defining pin groups for external connections (must-connect groups),see “Using Connectivity” (Chapter 12) in the Virtuoso Layout Editor User Guide.

For information about using constraints to restrict the placement of objects, see thedocumentation for the Cadence constraint editor.


Virtuoso Layout Accelerator User GuideEditing Your Layout with Virtuoso Layout Accelerator




Identifying Incomplete Nets

To see flight lines (lines that show uncompleted electrical connections between componentterminals, pins, and shapes in each net), follow these steps.

Note: Turn off the connectivity extractor by

■ Turning off the Connectivity Extractor option in the Layout XL Options form

■ Setting the extractEnable environment variable to nil in the .cdsenv file

you will not be able to see flight lines.

1. From the layout window, choose Connectivity – Show Incomplete Nets.

The Show Incomplete Nets form appears.



Flight lines appear in the layout window. Whether all incomplete nets or only a subset ofthem are shown with flight lines depends on the setup of the Show Incomplete Netsform when the command was last used or when the design was last saved. The defaultis for all incomplete nets to be shown with flight lines.

Note: You can set an environment variable, showIncNetEnable , that causes flightlines to appear as soon as the design is opened. The default setting for this variable isnil , so flight lines showing incomplete nets do not appear until you choose the ShowIncomplete Nets command.

The Show Incomplete Nets form reports how many incomplete nets there were in thedesign when the Show Incomplete Nets command was initiated.

Virtuoso XL shows all flight lines by default, but you can use the Show Incomplete Netsform to make the display show only the flight lines for the nets you specify or to filter bynet name the names of the nets shown.

2. Select the nets to be displayed by clicking on their names in the Incomplete list of netsor by typing the names in the type-in field. You can click on multiple net names ordeselect selected names by using Control click. You can select a range of names inthe list by clicking on the top name and then clicking on the bottom name with Shiftclick.

3. Click Apply.

Flight lines for the nets whose names are highlighted in the list of nets are displayed inthe layout. The Show Incomplete Nets form reports how many incomplete nets there arein the design and how many are displayed.



Note: In the Complete list box you can type in partial or complete names of nets to behighlighted. The nets will be highlighted the moment the net becomes incomplete. You mustclick Apply or OK to highlight the nets.

Zooming In on Flight Lines

1. To zoom in on the flight lines that are displayed, click Zoom.

The flight lines and their surroundings are shown enlarged as much as possibledepending on how many flight lines are shown.

2. To zoom in on each flight line in turn, click Individual Flight Line Segments.

Arrows appear on the form to let you cycle forward or backward through the displayedflight lines.

Virtuoso XL updates flight lines automatically each time you move a component and make orremove a connection.



Assigning Colors to Incomplete Nets

By default, Virtuoso XL uses the colors you assigned to the Layer Selection Window (LSW)entry layers y0 – y9 to show flight lines. If there are more than 10 incomplete nets in thedesign, the colors recycle. When you choose Show Incomplete Nets, the colors used arethe ones assigned when the command was last used or when the design was last saved.

To assign colors other than the default colors to the flight lines you specify, follow these steps.

1. In the Incomplete nets list box, select the names of the nets whose color you want tochange.

2. In the color choice cyclic field, select the color you want the nets to be.

3. Click Set Color.

The color of the net changes to the color you specified.

To turn off flight lines in the layout window,

➤ From the layout window, choose the Connectivity – Hide Incomplete Nets command.

Note: If editing commands run slowly while the Show Incomplete Nets command is active,use the Incomplete Nets form to turn off the display of incomplete nets on all the nets exceptthe nets you are working on.

Hide Incomplete NetsShow Incomplete Nets



Moving Objects Manually in the Virtuoso LayoutAccelerator

To move objects (devices, pins, or shapes) in the layout window, follow these steps.


The layout window prompts you to select an object to move.

2. Click on the object you want to move in either the layout or the schematic.

The object is highlighted in both the schematic and layout windows. An outline of theobject appears in the layout window and follows the cursor until you click in the layoutwindow to place the object.

Drag lines show connections from pins of the selected object to pins of the nearestinstance or the nearest I/O pin.

The layout window prompts you to click on the new location in the layout where you wantto place the selected object.

3. Click on the location where you want to place the object.

The object moves to the new location.

Note: If you select a component in the layout or the schematic before you choose theMove command, Virtuoso XL highlights the corresponding component in the schematicor layout.

4. Click on the next object you want to move or press Escape to cancel the command.

Note: Using the Move command cancels any existing commands in the current or in otherwindows.

Moving Objects Using Move Options

When you move objects, you can use the Move form to change

■ The layer of the object you select

■ The angles at which you can move the object

■ The presence of drag lines on the object as you move it

■ The orientation of the object you select

■ The use of placement constraints



■ The ability to move members of constrained groups individually or together

To use the Move options form to place components, follow these steps.


2. Press F3.

The Move form appears. The Display Draglines and Constraint Assisted Controloptions appear on the Move form only when you are running Virtuoso XL.

3. If you want to change the angle at which you can move an object (any angle, diagonal,orthogonal, horizontal, vertical), choose the angle you want from the Snap Modecyclic field.

4. If you want to change the layer on which a shape is drawn, turn on Change To Layerand choose a new layer from the cyclic field.

The layer is updated when you move the cursor into the layout window.

5. If you want to turn the drag lines off or on for an object you move, turnDisplay Draglines off or on.

Constraint Assisted Control



Drag lines connect pins on the object to the nearest pins on another object on the net.When you move the object closer to a different object on the same net, the linesreconnect to the new object. These drag lines appear only in Virtuoso XL.

Note: Disabling Display Draglines can speed up the action of the Move command.

6. To move groups of components bound by placement constraints as a unit or individually,turn on together or individually.

If a group of components you move is affected by placement constraints, thoseconstraints are obeyed during the duration of the Move command.

If a single component you move is subject to an unsatisfied Distance, Fixed, or Grouping(with a fence) constraint, and you move it across a coordinate that satisfies theconstraint, the component snaps to that coordinate.

Components restricted by Alignment or Symmetry constraints do not snap to coordinateswhen you move them, but if their constraints have already been satisfied, you can movethem only in ways that do not break the constraints.

In the case of a group constraint with a fence, the Move command lets you move thedevice until it is inside the fence; after that, you cannot move it outside the fence.

7. To turn off the use of placement constraints for the components you move, turn onignore.

8. To change the orientation of the object, click on the button describing the orientation youwant (Rotate, Sideways, or Upside Down).

The orientation of the object changes when you move your cursor into the layout window.

Note: When you use the Edit – Stretch command with Virtuoso XL running, theDisplay Draglines and the Constraint Assisted Control options also appear on the



Stretch form and work the same way.

Setting the Move Form to Appear Automatically

To set the Move form, or other options forms, to appear each time you use the Movecommand (without having to press F3) follow these steps.

1. From the CIW, choose Options – User Preferences.

The User Preferences form appears.

2. Click Options Displayed When Commands Start.

3. Click OK.

The Move form appears each time you choose the Move command.



Aligning Objects

To align two or more objects (devices, pins, or shapes), follow these steps.

1. From the layout window, choose Edit – Other – Align.

The Virtuoso XL Alignment form appears. The layout window prompts you to select theobject to which you want to align other objects.

2. In the Align Using cyclic field, choose the object center, object edge, or layer edge orcenter to use as a reference.

If you choose layer edges or centers, the form adds a Layer to use for alignment cyclicfield showing the layers to let you specify the layer.

3. In the Direction cyclic field, choose horizontal or vertical.

4. If you want Virtuoso XL to space objects evenly when they are aligned, turn on ApplySeparation and specify a minimum separation distance in the Separation field.

5. From the layout window, select the object (the reference) to which you want to align otherobjects.

A crosshair cursor appears over the object or layer you select.

Crosshair cursor



6. Click on the objects you want to align to the reference.

Virtuoso XL aligns each object as you click on it, separating the objects by the separationvalue you chose.

Note: The Align command does not read spacing information in the technology file;therefore, you might create shorts with this command. When you create a short, Virtuoso XLdisplays a marker over the short.

Note: The Align command does not obey user-defined constraints.

If you do not turn on Apply Separation, the software does not separate the objectsevenly.

7. To undo the alignment of an object, press the Back Space key.

Using this key, you can undo all the alignments you made.

Click here

Click here.

Overlap marker



8. To finish aligning one set of objects without exiting the command, click Next.

9. To align another set of objects, repeat steps 2 through 6.

10. To reset the values in the form to the default values, click Last.

11. To end the command, press Escape .

Swapping Components

To swap the location of two components in the layout window, follow these steps.

1. From the layout window, choose Edit – Other – Swap Components.

2. Click on the first component in the layout window.

Virtuoso XL prompts you to select a second component.

3. Click on the second component in the layout window.

Virtuoso XL switches the locations of the components you selected. Virtuoso XL retainsthe orientation of the component associated with the position.

4. To undo the swap, from the layout window choose Edit – Undo.

To begin a newalignmentsequence,click Next.

To reload thevalues used forthe previousalignmentsequence,click Last.

npn1

npn1

npn2 npn2



5. To swap another two components, choose Edit – Other – Swap Components again.

Virtuoso XL does not move the connections to the components. If swapping componentscauses shorts, markers show where the shorts are. If swapping components causes openconnections, flight lines show the open connections.

The Swap Components command does not allow you to swap components that are partof a satisfied constraint (unless the swap maintains the constraint).

Permuting Component Pins

Virtuoso XL lets you permute (exchange the connectivity or net connections of) the pins of acomponent.

Pins to be permuted

■ Must belong to different nets

■ Must first be defined as permutable terminals

When the Auto Permute Pins option is active (the default setting) in the Virtuoso XL Optionsform, Virtuoso XL automatically permutes pins in a component if doing so corrects a shortcaused by routing when the routing was done interactively (using auto-abutment) or donewhile moving or stretching a shape (or using any operation that changes connectivity).

To change the setting of the Auto Permute Pins option, follow these steps.

1. From the layout window, choose Options – Layout XL.



The Layout XL Options form appears.

2. Turn on Auto Permute Pins.

3. Click OK.

Virtuoso XL automatically permutes the pins of a single component when doing soremoves a short, as shown below. In the diagram below, two pins belonging to differentnets (A and B) create a short when they are touching each other. If these pins arepermutable, and reversing the pins of one component connects the two pins that are onthe same net (B), Virtuoso XL permutes them.

Virtuoso XL also automatically permutes the pins of two components at the same timewhen doing so removes a short, as shown below. In the diagram below, two pins

Auto Permute Pins option

Before pins are permuted After pins are permuted

A B CBAB CB

marker showing short



belonging to different nets (A and C) create a short when they are touching each other.If these pins are permutable, and reversing the pins of both components connects thetwo pins that are on the same net (B), Virtuoso XL permutes them.

Permuting Pins Manually

To manually permute pins within a component, follow these steps.

1. From the layout window, choose Connectivity – Permute Pins.

Virtuoso XL prompts you to select a pin.

2. Click on the first pin in the layout window.

Virtuoso XL prompts you to select a second pin.

3. Click on the second pin in the layout window.

Virtuoso XL switches the net connections of the pins you selected. If flight lines aredisplayed, the flight lines change to show the new nets assigned to the pins.

Note: This command is modal; that is, you can continue to select sets of pins to permutewithout going back to the command again each time.

4. To undo the permutation, from the layout window, choose Edit – Undo.


A B CBAB C B

marker showing short


A

B A

B



The pins return to their original net connection in the layout.

5. To cancel the command, press Escape .

Note: Any pin previously connected to a path, polygon, rectangle, or component pin cannotbe permuted.

Checking Permutation Information

To see information about permuted pins, follow these steps.

1. From the layout window, choose Connectivity – Permute Pins.

2. Press F3.

The Permutation Information form appears.

If the pins you select do not permute, this form also tells you why.

Using Device Locking

To lock devices in their current positions in the layout (set temporary fixed constraints), so thatthey cannot be moved during interactive or automatic placement, follow these steps.

Cannot permute these two pins due to the constraint of permuteRuleNo permutation for pin C (net:vcc!) and pin B (net:AB)!



1. In the layout window, select the devices to lock.

2. From the layout menu, choose Edit – Other – Lock Selected.

The locked devices can no longer be moved by the Move or Stretch commands.

If the selected devices are constrained by other fixed constraints, a message windowasks you to approve overwriting those constraints.

Fixed constraints for the selected devices appear in the constraint editor and theConstraint Status Browser Window if they are open.

When you save the design, a dialog box asks you if you want to convert the lockeddevices into permanent fixed constraints.

Click OK to convert the locks to fixed constraints.

To delete the locks on the devices you locked, follow these steps.

1. In the layout window, select the devices to unlock.

2. From the layout menu, choose Edit – Other – Unlock Selected.

The temporary fixed constraints are removed from the locked devices and they can thenbe moved by the Move or Stretch commands.

You can also remove these temporary locks using the Constraint Editor by following thesesteps.

1. In the Constraint Editor window, click on the Fixed category to show the individualconstraints.

2. Middle-click and hold over the name of the device to unlock.

3. From the pop-up menu that appears, choose Delete.

The locked devices are no longer locked in position. The names of the locked devicesdisappear from the Fixed constraint category in the Constraint Editor window and in theConstraint Browser.



Using Automatic Spacing

You can assign automatic spacing properties to pins of instances so that if these pins are ondifferent nets or the pins cannot abut for any reason (for example, they are not assignedabutment properties), the software automatically separates the instances by the distance andin the direction you specify.

You can use the layout editor user interface to enter properties on the pins in the same waythat you enter the permuteRule properties.

The properties to set automatic spacing are listed below.

To add the access direction to the pin:

property value type valid values

----------------- ---------- ----------------------------

vxlInstSpacingDir skill list one or more of the followingstrings in the list:

"left" "right" "top" "bottom"

To add the spacing rule to the pin:

property value type valid values

----------------- ---------- ----------------------

vxlInstSpacingRule floating number greater than 0

pt number

If you want automatic spacing to apply to Cadence® SKILL language or technology fileparameterized cells (pcells), you can enter these properties in SKILL to add the spacingproperties to the pins.

If you want automatic spacing to apply to standard cells, you can also use the layout editor toenter properties on the pins.



If the vxlInstSpacingRule value is different for two pins affected by Auto Space, thelarger of the two values is used; if the value is defined for only one of two pins affected byAuto Space, the defined value is used.

➤ To activate automatic spacing, turn on Auto Space in the Layout XL Options form (onis the default).

with Auto Space turned off

0.6

vxlInstSpacingDirvalue = rightvxlInstSpacingRulevalue = 0.6

vxlInstSpacingDirvalue = leftvxlInstSpacingRule value = 0.5

with Auto Space turned on

vxlInstSpacingDirvalue = right, leftvxlInstSpacingRulevalue = 0.6

vxlInstSpacingDirvalue = right, leftvxlInstSpacingRule value = 1.0

1.0



Using Interactive Device Abutment

To abut two devices that are set up for abutment, follow these steps.

1. From the layout window, choose Options – Virtuoso XL.

The Virtuoso XL Options form appears.

2. Ensure that the Auto Abutment and Connectivity Extractor options are turned on.

3. Move an instance so that one of its instance pins touches the instance pin of anotherinstance.

If the two pins are on the same net, the instances are automatically abutted.

If the two pins are on different nets but auto-permutation of one or both of these pins willbring two pins in the same net into contact, the pins are automatically permuted and thetwo instances are abutted.

After the abutment takes place, the alterations to the cell that you specified in the pcellabutment parameters take place.

The abutment system moves only one instance to abut two cells. Of two instances thatcan be abutted, it chooses to move

1. A selected cell over a cell that is not selected

2. A cell that is not already abutted over a cell that is already abutted



Setting Component Types

You control how components are assigned to rows, and their chaining and folding parameters,by defining component types. The Component Description Format (CDF) parameter thatholds the placement parameters and type assignments is lxComponentType . You set thelxComponentType parameter using the Edit Component Types form associated with theDesign – Component Types command.

Important

Do not assign a type to more than one component master.Do not edit lxComponentType directly with the CDF Editor.

About Component Types

Component types are part of the library or cell information for cells in which components areplaced. You can define component types at the library level, if all cells in the library share thesame types, or you can define component types for the individual cells that will contain theplaced components.

The purpose of component types is to identify the NMOS and PMOS transistor cells and settheir parameters for device chaining and folding.

MOS Transistor Stacking and Folding Parameters

MOS transistors that are candidates for chaining and folding need to be identified in the EditComponent Types form described in the Defining Component Types form (and have certainparameter values set) before you generate layout.

Use the following parameters in the NMOSor PMOStype definitions to control device stackingand folding during placement. You must set the lxDeviceWidth and lxMaxWidthparameters; the other parameters are optional.

Note: Terminal names are not case sensitive.

lxDeviceWidth The name of the transistor width parameter on the device mastercell. The default name must be w. If you use a different name forthe width, set this parameter to the correct name. This parameterneeds to be set even if the devices will not be folded.



lxMaxWidth The maximum width beyond which devices of type NMOS andPMOS must be automatically folded. This parameter needs to beset even if the devices will not be folded.

This value applies globally to all devices within the scope of thecomponent type definitions (the library containing the currentcell, or just the current cell). You can override this value using thelayout generation commands Gen from Source and Pick fromSchematic. In the Placement Style form, you can overridelxMaxWidth by setting PMOS Width Threshold and NMOSWidth Threshold.

Caution

Virtuoso XL cannot accurately enforce the value of lxMaxWidth unlessall device widths and all lxDeviceWidth values are specifiedconsistently; for example, all in meters (10um is 1-e-5) or in all in userunits (10um is 10).

lxSourceName A list of instance terminal names corresponding to the MOStransistor source terminal. The default names are source andS. If you use different names, define this parameter and set itsvalue. For example: ("src" "sour") .

lxDrainName A list of drain terminal names. The default names are drain andD.

lxGateName A list of gate terminal names. The default names are gate and G.

lxBulkName A list of bulk terminal names. The default names are bulk and B.

lxActiveLayer The diffusion layer for NMOS and PMOS devices.

Defining Component Types

Setting the component types in this form sets the lxComponentType parameter.

1. Select Design – Component Types.



The Edit Component Types form appears.

2. From the Scope radio buttons, choose the scope of the component types you want tocreate:

❑ The entire library

❑ The current cell



3. In the Type field, do one of the following:

❑ Type in a name for a new type and click Add.

Typical types for a MOS device library might include NMOS, PMOS, andCAPACITOR. Type names may be any string.

Important

Type names must be upper case.

❑ Select a type from the cyclic field.

4. Populate the Components in Type list by doing one of the following:

❑ Highlight the cells in the Cells in Design list and select the >>> button to movethem into the Components in Type list.

❑ Select the cells in the layout and click Add Selected Components to move theminto the Components in Type list

Or, if you have not already generated layout for the design, and the Cells in Design listis incomplete or empty,

a. Type the first library and cell name in the Cells in Design field, surrounded bydouble quotation marks:

"MYLib Mycell"

b. Select the >>> button to move the cell into the Components in Type list.

c. Repeat as needed.

Important

Do not assign a component master to more than one type.

5. In the Edit parameters cyclic field, select the name of the first placement parameter youwant to set for the cells in this type. See “Setting Component Types” on page 228 formore information.

6. Fill in the value.

7. Select the next parameter and set its value.

Continue until you have set all of the required parameters and all of the optionalparameters you wish to set.



8. Set the value of Component Class to NMOS or PMOS for MOS transistors, or toSTDCELL or FILLER for those elements, or to Undefined otherwise.

9. Click Apply at the top of the form to complete the type definition.

To define additional types, repeat Step 3 through Step 9.

Modifying a Component Type

Use the Edit Component Types form to change component type definitions.

Note: Be sure that the scope of the types you are editing (library or cell) is appropriate. It ispossible to modify a component type at a narrower scope than the one with which it wascreated (changing library-wide type definitions for just one cell, for example). This might notbe the result you want.

1. Select Design – Component Types.

The Edit Component Types form appears.

2. Choose the scope of the component types you want to edit.

3. Choose a type.

4. (Optional) Highlight masters or instances in the Components in Type list and select<<< to remove them from the type.

5. (Optional) Select a parameter in the Edit Parameter field, and type a new value.

6. Check that Component Class is set to the correct value.

7. Select Apply to save your changes.



Using Transistor Chaining

Transistor chaining is the process by which a list of MOS transistors (or the fingers of foldedtransistors) can be abutted with one another in a specified order. Chaining helps reducelayout area and capacitance.

Transistors to be chained must be set up for abutment.

Transistors to be chained must have a property named lxComponentType set on their cellor library. This property stores their attributes. You must set this property on the cell or libraryusing the Edit Component Types form associated with the Design – Component Typescommand. For complete information about setting the lxComponentType parameter, seeSetting Component Types on page 228

You can chain transistors automatically during layout generation or interactively during layoutediting.

To chain transistors interactively, follow these steps.

1. From the layout window menu, choose Edit – Transistor Chaining.

The Transistor Chaining form appears.

2. Select in the layout window the transistors to chain or click Add Cell ListBox to see thelist of transistors available for chaining.



The list box appears in the Transistor Chaining form.

3. Select the transistors to chain from the list box.

Note: You can also preselect transistors from the layout window before you choose theTransistor Chaining command.

4. Click Apply.

The selected transistors are highlighted in the layout. The layout window prompts you toselect a destination point in the layout window.

5. Move the cursor into the layout window.

The transistors appear as the image of a transistor stack that follows the cursor.

Folded transistors are stacked with the number of fingers as defined.

Stacks consisting of only NMOS or only PMOS transistors are aligned by the bottomedge. If you use the Gen From Source command to create a cluster consisting of both



an NMOS and a PMOS transistor, the PMOS is placed on the top, aligned to the loweredge, and the NMOS is placed below it, aligned to the upper edge.

To change the vertical orientation of such stacks, use Move – Upside Down.

6. Click on the layout window where you want to place the chained transistors.

The transistors are placed where you click.

If you want to remove one or more transistor from the stack, follow these steps.

1. Select the transistor(s) you want to remove.

2. Choose Edit – Move.

3. Click where you want to place the transistor.

The transistor is placed where you click in the layout window.

PMOS Stack

NMOS Stack

Before transistor chaining After transistor chaining

Before removing transistor from chain After removing transistor from chain



Using Transistor Folding

You can use the Transistor Folding command to interactively divide a transistor or atransistor stack (an abutted group of MOS transistors) into two or more fingers, layoutinstances with terminals all connected in parallel to the same nets. Folding transistors andstacking them allows you to change their aspect ratio for design efficiency. Folding a transistorstack triggers rechaining of the stack.

Transistors to be folded must have a property named lxComponentType to store theirwidth attributes set on the cell. You must use the Edit Component Types form associated withthe Design – Component Types command to set this property on the cell. Using this form,you can define lxDeviceWidth , the MOS device gate width parameter used to edit thetransistor folding (required), and lxMaxWidth , the maximum transistor width (optional). Formore information about setting these parameters, see Setting Component Types on page 228

You must have the environment variable mfactorSplit set to t in a setup file for thedesign, or the Fold Transistors command does not work.

To fold one or more transistors, follow these steps.

Note: You can preselect the transistors you want to fold in the layout or schematic window. Ifyou select a transistor that has already been folded, you must select it from the schematic orselect all of its fingers at the same time in the layout.

1. Choose Edit – Transistor Folding.

The Set Transistor Folding form appears.



If you did not preselect any transistors, no transistor-specific information is shown in theform until you select at least one.

If you preselected transistors to fold, the name of first one you selected is shown in theTransistor Name field.

The width of the transistor, as specified in the schematic, is shown in the TransistorWidth field.

2. For the selected transistor, type in the Number of Fingers field the number of fingersinto which you want it divided.

The Set Finger Widths option button appears on the form.

3. To set the finger widths to unequal widths, click Set Finger Widths.



The form changes to let you enter the finger widths.

You can add new fingers with the Add Finger button, delete fingers with the Deletebutton opposite each finger, and assign the same width (dividing the total width of thetransistor by the number of fingers) to all the fingers with the Same Width button.

Note: Interactive folding might overwrite the default lxMaxWidth parameter; by usingthe specifications you supply. For example, if you fold the transistor in too few fingers, thefingers might end up longer than the lxMaxWidth parameter you must specify using theEdit Component Types form associated with the Design – Component Typescommand. Automatic folding always respects the lxMaxWidth parameter.

4. Type the finger widths you want.

6.0

M12



5. If you do not want the fingers that are created to be chained (abutted in a stack), turn offChain Fingers.

6. Click Apply.

7. Move the cursor into the layout window.

A representation of the fingers of the transistor follows the cursor in the layout window.

8. Click in the layout where you want to place the transistor fingers.

The transistor fingers are placed where you click.

If you have selected more than one transistor, you can press the Next or Previousbuttons to move to another transistor. You must click Apply to save the changes to atransistor before clicking Next or Previous.

Note: When the Fold Transistors command is active, you cannot select any pcell that hasa fingering value set to greater than 1.

Note: If you enter an lxMaxWidth parameter that would yield a device with more than 999fingers (for example, a device width of 2 and lxMaxWidth of1 µ, which could result in adevice folded in 2 M fingers), the Command Interpreter Window (CIW) prints a warning anddoes not fold the device. You can still fold such a large device manually.



Adding Instances to a Layout

To add an instance not present in the schematic to the layout, you can add the instance to theschematic and connect it to a net, as explained below, or you can add it to the layout usingthe layout editor Create Instance command and connect it with the Virtuoso XL UpdateComponents and Nets command.

Note: The schematic must be opened in edit mode.

To add an instance not present in the schematic to the layout, follow these steps.

1. In the schematic window, choose Add – Instance.

The Add Instance form appears.

2. In the Library field, type the library name of the new instance.

3. In the Cell field, type the cell name of the new instance.

4. In the View field, type the view name of the new instance.

5. In the Names field, type the instance names (if any).

6. Move the cursor to the schematic.

The outline of the instance follows the cursor.



7. Click in the schematic where you want to place the instance.

The instance is placed in the schematic.

8. To connect the instance to a net, use the schematic window Add – Wire command.

9. When you have finished adding instances to the schematic, from the layout window,choose Connectivity – Update – Components and Nets.

A dialog box asks whether you want to extract the schematic.

10. Click Yes.

Virtuoso XL extracts the schematic and adds the instance to the layout.

Note: If you have a large design and are only adding a few instances, it saves time to use theConnectivity – Update – Device Correspondence to update each instance rather thanusing Connectivity – Update – Components and Nets to update the whole design.

Note: If the instance does not need to be connected to a net, add it directly to the layout andadd the lvsIgnore property to it.

Adding Pins to a Layout

Pins occurring in both the schematic and the layout must have identical names. If you addpins that are not in the schematic to the layout, Virtuoso XL maintains their connectivity in thelayout. To add a pin to the layout, follow these steps.

1. In the Layer Selection Window (LSW), choose the layer on which you want to create thepin.

2. From the layout window, choose Create – Pin.



The Create Shape Pin form appears.

3. In the Terminal Names field, type the terminal name for the pin.

The pin name must match the name of an existing net in the schematic. You can createmore than one pin with the same name.

4. In the I/O Type section, choose the appropriate I/O type.

Note: To create a pin for a net that is not on the schematic (a feedthrough, for example),give the pin a new name.

5. In the layout window, click to place one corner of the pin; then click to place the oppositecorner of the pin.

The pin appears on the layout window.

Note: Do not place pins where you do not want to make a connection. For example, donot create a pin on poly that covers the gate area of a FET.

If Show Incomplete Nets is on, flight lines show the pin connected to the net.

Note: You can also add pins defined with shapes. You can use any layer purpose for pinshapes. Pins made as large as possible make routing easier.



Assigning Pins to a Net

If you place instances in a layout that does not have a connectivity source (a schematic ornetlist), the software does not connect them to any net unless you specifically assign theinstance pins to a net using the Assign Nets command.

You can also use this command to connect a new instance to an existing net in a design thathas a connectivity source.

To assign the pins of an instance that you place in a layout to a net that you specify, followthese steps.

1. Place the new instances that you need in the layout using Create – Instance.

2. Choose Connectivity – Show Incomplete Nets.

3. Choose Connectivity – Assign Nets.

The layout window and the CIW prompt you to select a pin to add to a net.

4. Click on a pin in one of the new instances you have placed.

You can use Shift click or click and drag to select multiple pins to be added to the samenet. You can use Control click or click and drag to deselect multiple pins you haveselected in this step.

The pin you select is highlighted. The layout window and the CIW prompt you to select anet to add the pin to.

5. Click on a pin that is connected to the existing net you want to add the pin to.

The flight lines representing that net are extended to show that the pin is added to thenet. The CIW lists the name of the pin and the name of the net it was connected to.

The layout window and the CIW prompt you to select another pin to add to a net.

6. Display a list of all the nets in the layout by pressing F3.



The Assign Nets form appears listing all the nets in the layout.

Nets with names that begin with le_ex_ belong to the new instances you placed in thedesign. After you assign all the pins of these new instances to existing nets, the softwaredeletes the le_ex_ nets from the form and the layout.

7. To add a pin you selected in the layout to a net listed in this form, click on the name ofthe net in the form and then click Apply.

The flight lines representing that net are extended to show that the pin is added to thenet.

8. To exit this command, press Escape .



Maintaining Connectivity When Editing a Flattened Pcell

To edit a parameterized cell (pcell) from a layout in which it is a component, you need to usethe layout window Design – Hierarchy – Edit in Place command. However, Virtuoso XLcommands are turned off while the Edit in Place command is active, so connectivitybetween the pcell and the layout of which it is a part can be lost.

To maintain this connectivity when you edit a pcell, make a new cell, edit it, and reconnect itto the original layout. To do so, follow these steps.

1. In the layout, select the instance you want to edit.

2. From the layout window, choose Edit – Hierarchy – Make Cell.

The Make Cell form appears.

3. In the Library field, type the name of the library of your design.

4. In the Cell field, type the same cell name as the master.

5. In the View field, type a unique view name (for example, layout.new ).

6. Click Apply.

The software creates the new cell.

7. In the layout window, select the new instance you want to edit.

8. In the layout window, choose Design – Hierarchy – Edit in Place.

9. Choose Edit – Hierarchy – Flatten.



The Flatten form appears.

10. Set Flatten Mode to one level.

11. Turn on Flatten Pcells.

12. Turn on Preserve Pins.

13. Click OK.

14. Make the necessary edits to the cell.

Note that this cell is no longer a pcell.

15. Choose Design – Hierarchy – Return.

A dialog box asks you if you want save your changes.

16. Click Yes.

17. If you do not have the Show Incomplete Nets command active, choose Connectivity– Show Incomplete Nets.

The flight lines show that there is no connectivity to the instance you just edited.

18. Choose Connectivity – Update – Device Correspondence.

19. Click on the symbol for the instance in the schematic.

20. Click on the new instance in the layout.

The connectivity is updated.

To use this layout for other instances of this cell, you can edit the Component DescriptionFormat (CDF) for the cell and set the stopList property to layout.new layout . Forother instances, you can use the Virtuoso XL command Connectivity – Update – ChangeInstance View to pick between views while maintaining connectivity.




Assign Nets Form on page 247

Edit Component Types Form on page 248

Move Form on page 250

Set Transistor Folding Form on page 251

Show Incomplete Nets Form on page 252

Stretch Form on page 254

Virtuoso XL Alignment Form on page 255

Assign Nets Form

Create enters in the list of net names the new net name you type in the entry field.

Delete deletes from the list of net names the name you type in the entry field or select in thelist of net names if no objects are attached to that net.

The entry field above the list of net names has a search mechanism that highlights in the listbox the net name you type in the field.



Edit Component Types Form

The Edit Component Types form lets you create and modify placement component types forlibraries or cells.

Scope radio buttons let you set the scope of the component types you are defining.Components that you place in the cells encompassed by the scope share the component typedefinitions you create in the lower part of the form.

Lib assigns these type definitions to the library containing the current cellview.

Current assigns these type definitions to the current cellview only.

Type is the name of a component type. Enter new type names in this field, or click on typenames in the cyclic field to select them for editing.

Add creates a new type with the name shown in the Type Name field.

Delete immediately removes the type in the Type Name field from the types defined for thecurrent scope. If you delete a type accidentally, you can select Cancel to discard all of yourchanges in the Edit Component Types form.

Add Selected Components adds the instances currently selected in the layout window tothe Components in Type list. Use this button to select which instances should be inwhich types.

Important

You cannot use this command to define chaining and folding parameters forinstances. All instances of a master must share the same parameter values, andyou must define those values on the master cell (by including the master in theComponents in Type list).

Cells in Design lists all of the masters with instances placed in the layout. If you have notyet generated layout, this list would be empty. You can add masters to the list by typing aquoted library and cell name in the type-in field. The syntax is:

"MYLib Mycell"

Components in Type lists the masters and instances belonging to the current Type.

>>> moves the selected components to the Components in Type list.

Delete Component deletes components that you have hightlighted in the Components inType list field.



Edit parameters is a cyclic field containing the names of the required and optionalplacement parameters. the name of a parameter shared by the cells in a type. Enter newnames in this field, or click on parameter names in the list box to select them for editing. Forinformation about each parameter, see “MOS Transistor Stacking and Folding Parameters”on page 228

Component Class lets you identify MOS transistors suitable for chaining, folding, and theAssisted MOS placement style. For MOS transistors, set this field to NMOS or PMOS asappropriate or set STDCELL or FILLER for those design components.. For all other devices,set this field to Undefined.

You can have multiple devices assigned to the NMOS and PMOS component types. Thiswould typically be the case for multiple voltage designs.



Move Form

Snap Mode controls the direction in which you can move the object.

Change To Layer , when on, lets you move a shape to another layer. Choose the new layerfrom the cyclic field, which displays all the available valid layers.

Display Draglines , when on, displays rubberbanding lines that connect pins of the objectyou are moving to pins of the nearest objects.

Constraint Assisted Control allows objects to be moved only in ways that satisfy theconstraints entered using the constraint editor.

together moves preselected objects in the layout as a group.

individually moves preselected objects in the layout individually.

ignore specifies that constraints have no effect on objects in the layout when they aremoved.

Rotate rotates the component 90 degrees counterclockwise.

Sideways mirrors the component on the Y axis (flips it horizontally).

Upside Down mirrors the component on the X axis (flips it vertically).

anyAngle (default)

diagonal orthogonal horizontal vertical



Set Transistor Folding Form

Transistor Name displays the name of the first transistor you selected.

Transistor width as specified in the schematic displays the value of the width propertyof the transistor in the schematic.

Number of Fingers lets you enter the number of fingers (divisions) into which you want tofold the transistor. Entering a value in the Number of Fingers field causes the appearanceof the Set Finger Widths option button.

Set Finger Widths , when turned on, changes the Set Transistor Folding form to include newfields that let you enter the width of each finger.

Chain Fingers , when active, allows the software to abut the fingers into stacks.

Total Width displays the total value of the all widths you enter in the Width fields.

Add Finger adds another Width field to the form to let you enter the width of an additionalfinger.

Same Width sets all the values in the Width fields to the same width (totaling the samevalue as specified in the schematic, unless you override that value in the entries you make inthe Width fields).

Width lets you enter a separate width for each finger.

Delete removes the Width field and decreases the number in the Number of Fingers fieldby 1.



Show Incomplete Nets Form

Cellview displays the library, cell, and view name of the layout window on which the ShowIncomplete Nets form is focused.

Class displays class names in the list boxes and prepares the search fields for class names.

Net displays net names in the list boxes and prepares the search fields for net names.

Color choice cyclic field:

Cycle lets the software assign the next y0–y9 entry layer in the color choice cyclic fieldto the next flight line you choose.

The y1–y9 entry layers let you assign one single color for all the flight lines. You cannotassign the y0 layer as a single color for all flight lines because it is the default layer.

As Is keeps the colors currently assigned from the y1–y9 entry layers in the color choicecyclic field.

Set Color sets the color of all incomplete nets highlighted in the Incomplete list box andhighlighted in the layout window to the drawing layer color shown in the color choice cyclicfield.

Search lets you type one or more net or class names (separated by a space) to behighlighted in the Incomplete or Complete list boxes and in the layout window. You cannotuse the wildcard character (*) in this field, but typing the initial characters of net nameshighlights all names in both lists beginning with the specified character(s).

Incomplete

The type-in field lets you type partial or complete names of nets to be highlighted in theIncomplete list box and displayed in the layout window (as long as they are incomplete) whenyou click Apply.

The list box lets you select the names of nets you want to display or to which you want toassign a color. You can use Control click to select more than one or to deselect selected netnames.

Select All displays flight lines for all incomplete nets in the design when you click Apply.

Select from Display lets you click on pins and instances in the layout window to selectthem and displays them when you click Apply.

Less truncates the form so that it does not display the Complete nets list box or theZoom features; the button label changes to More.



More expands the truncated version of the form to include the Complete nets list boxand the Zoom features; the button label changes to Less.

Complete

The type-in field lets you type in partial or complete names of nets to be highlighted in theComplete list box and displayed in the layout window (only if they become incomplete) whenyou click Apply. This capability lets you mark nets of critical importance so that they showup if their connectivity is lost.

The list box lets you select the names of nets you want to display or to which you want toassign a color. You can use Control click to select more than one or to deselect selected netnames.

Clear All Selections removes the display of flight lines for all incomplete nets in thedesign when you click Apply.

Create Class opens the Create/Edit Net Class form to let you create net classes.

Zoom enlarges the flight lines and the area around them.

All Displayed Flight Lines enlarges as much of an area as possible around all the flightlines.

Individual Flight Line Segments enlarges as much of an area as possible aroundindividual flight lines. This option displays the zoom arrows.

Zoom arrows (--> and <--) display each net individually in the order listed in the Displayfield.

To zoom out again after viewing individual flight line segments, in the Zoom section, selectAll Displayed Flight Lines, then in the Incomplete section, click Select All, and thenclick Zoom.

The list box at the bottom of the form tells how many incomplete nets are in the design andhow many incomplete nets are displayed.



Stretch Form

Snap Mode controls the direction in which you can move the object.

Lock Angles , when on, prevents you from changing the angle of a corner or edge as youstretch it.

Display Draglines , when on, displays rubberbanding lines that connect pins of the objectyou are moving to pins of the nearest objects.

Use “ignore” for Stretchable Pcells reminds you to choose the ignore option in theConstraint Assisted Control section when you are working with stretchable pcells because, ifConstraint Assisted Controls are active, you cannot use the stretch handle to stretch pcells.

Constraint Assisted Control allows objects to be moved only in ways that satisfy theconstraints entered using the constraint editor.

together moves preselected objects in the layout as a group.

individually moves preselected objects in the layout individually.

ignore specifies that constraints have no effect on objects in the layout when they aremoved.

anyAngle (default)

diagonal orthogonal horizontal vertical



Virtuoso XL Alignment Form

Align Using indicates how objects are aligned.

BBox center aligns the centers of object bounding boxes. (The device bounding boxexcludes the area of an attached label.)

BBox edge aligns the left, right, top, or bottom edges of object bounding boxes.

layer center aligns the centers of the shapes on the current layer. If there are no shapeson the current layer, Virtuoso XL aligns the centers of the object bounding boxes.

layer edge aligns the left, right, top, or bottom edges of the shapes on the current layer.If there are no shapes on the current layer, Virtuoso XL aligns the edges of objectbounding boxes.

origins aligns the origins of the objects.

Direction defines the alignment direction for the BBox center, layer center, and originsalignment options. Direction is not available for the BBox edge and layer edge options.

horizontal aligns objects in the X direction.

vertical aligns objects in the Y direction.

Layer to use for alignment is a cyclic field showing the layers defined in your technologyfile. Use this field to specify the layer to use for aligning by layer edge or center.

Separation defines the distance (in user units) to maintain between aligned shapes. You canset this value to a negative number to overlap instances.

Apply Separation separates the selected objects by the number of user units in theSeparation field.



9Stretching Parameterized Cells inVirtuoso XL

This chapter contains a brief overview about stretchable parameterized cells (pcells) and howto stretch them with the Virtuoso® layout accelerator (Virtuoso XL). For a more detaileddescription of stretchable pcells, see “Stretchable Parameterized Cells” in the VirtuosoRelative Object Design User Guide.

The topics in this chapter are:

Introduction on page 257

Stretching a Contact Array in a Pcell Instance on page 258

Stretching Multiple Handles on page 262

Selecting a Handle Assigned to Multiple Parameters on page 264

Setting Environment Variables for Stretchable Pcells on page 265

Troubleshooting on page 265


Virtuoso Layout Accelerator User GuideStretching Parameterized Cells in Virtuoso XL

Introduction

A stretchable pcell is a SKILL-based pcell created with one or more stretch handlesassigned to one or more of its parameters. A stretch handle is a relative object design (ROD)point handle that is assigned to one or more pcell parameters within the pcell code. Oninstances, stretch handles are displayed as small diamonds.

You can change the value of a parameter by starting the Stretch command, selecting thestretch handle assigned to the parameter, and moving the handle. Although it might appearthat you are stretching the instance or objects within the instance, you are really graphicallyupdating the value of the parameter(s) associated with the selected handle. Graphicallystretching a pcell instance has the same result as editing its parameters using the EditProperties form.

For more information about ROD point handles, see “Handles on ROD Objects” in theVirtuoso Relative Object Design User Guide.

When you select a stretch handle, and the pcell definition contains information to be displayedfor that handle, the system displays the information next to the upper-right corner of the pcell.The information is usually the name and value of the parameter to which the handle isassigned. In the example below, the handle is assigned to the width parameter of the pcell.

You can drag a stretch handle in the direction of the X or Y axis, depending on how the stretchhandle is defined in the pcell code.

As you drag a handle, the system displays an outline showing how the pcell is changing. Also,according to the frequency defined for regenerating the pcell, the system updates theassociated parameter, regenerates the pcell, and displays the updated information.

pcell Stretch handles onpcell instance

pcell

width = 10.0

Display information

width



Note: You cannot undo stretching a pcell instance.

In the example below, the handle assigned to the width parameter is stretched to the rightto make the pcell wider.

Stretching a Contact Array in a Pcell Instance

The steps below show how to select a stretch handle on a contact array inside the instanceof a transistor pcell and stretch it.

For a detailed description of the sample transistor pcell, see “Stretchable MOS Transistor” inthe Virtuoso Relative Object Design User Guide.

For more complex MOS code examples, see the Sample Parameterized Cells Installationand Reference.

In this example, you want to make room for routing over the diffusion, so you need to reducethe number of contacts in the right-hand contact array to one by stretching the array. Thereare two different ways to do this: area selection or point selection. For both methods, youstart the Stretch command before selecting a handle. Both selection methods aredescribed below; follow the steps in one of them.

pcell

width

Stretching the handle assigned to thewidth parameter

width = 12.5



Stretching Using Area Selection

1. From the layout window, choose Edit – Stretch.

The system automatically changes to Partial Selection mode and prompts you to selectthe figure to be stretched.

2. Click the left mouse button and drag to create a selection box around the stretch handleat the top of the right-hand contact array.

The system highlights the pcell instance to show that it is selected and prompts you toenter a reference point for the stretch.

3. Specify a reference point by clicking on or near the selected handle.

Any information defined for the selected stretch handle appears next to the pcellinstance.

The system prompts you to enter a new location for the stretch.

4. Move the cursor to above the bottom contact in the right-hand contact array.

Select the top stretch handle.

rightcov = 1



As you move the cursor, the system updates the display information and displays anoutline showing how the pcell is changing as a result of the stretch.

5. End the stretch by clicking above the lower contact. In the example, click when thedisplay information says rightcov = 0.25 .

The transistor pcell instance now looks like this:

6. Exit the Stretch command by pressing Escape .

Stretching Using Point Selection

1. To make sure that no objects are selected, click in the background, outside of the pcellinstance.

Point selection might not work well if you are zoomed out.

2. Zoom in so that the pcell instance fills the window.

Click here.

rightcov = 0.25

X



3. Move the cursor outside of the pcell instance.


The system automatically changes to Partial Selection and prompts you to select thefigure to be stretched.

5. Click on the stretch handle at the top of the right-hand contact array.

You must click within one snap grid to select a stretch handle.

Note: If you have trouble selecting a stretch handle, try turning off the Gravity On optionon the Layout Editor Options form.

Any information defined for the selected stretch handle appears next to the pcellinstance.

The system prompts you to enter a new location for the stretch.

Click here.

rightcov = 1



6. End the stretch by clicking above the lower contact. In the example, click when thedisplay information says rightcov = 0.25 .



Stretching Multiple Handles

You can select two or more handles to stretch at the same time. The system processes eachhandle in the sequence in which the handle-to-parameter assignments appear in the pcellcode definition. The results of the stretch depend on how the handles affect their associatedpcell parameters. For a description of the results of stretching multiple handles, see“Stretching Multiple Handles” in the Virtuoso Relative Object Design User Guide.

Note: When multiple stretch handles occupy the same point, and you select the point (or oneof the handles on it), all stretch handles on the point are selected.

Click here.

X

rightcov = 0.25

X



To select and stretch both contact arrays in the sample transistor pcell instance, do thefollowing:


2. Click the left mouse button and drag to create a selection box around the stretch handlesat the top of both contact arrays.

3. Enter a reference point by clicking on or near a selected handle.

The system displays information for both selected handles next to the pcell.

Select both stretch handles.

leftcov =1rightcov = 1



4. Move the cursor to above the bottom contact in either contact array and click to end thestretch.



Selecting a Handle Assigned to Multiple Parameters

A stretchable pcell can have a handle that is assigned to two or more different parameters.When you stretch the handle, the results of the stretch can affect all of the associatedparameters.

For information on the results of stretching a handle assigned to multiple parameters, see“One Handle Assigned to Multiple Parameters” in the Virtuoso Relative Object DesignUser Guide.

Click here.

leftcov = 0.25rightcov = 0.25

X



Setting Environment Variables for Stretchable Pcells

You can set the following environment variables to influence what the system does when youstretch a handle:

updatePCellIncrement

displayStretchHandles

stretchHandlesLayer

constraintAssistedMode

For information about these environment variables, see “Specifying Environment Variablesfor Stretchable Pcells” in the Virtuoso Relative Object Design User Guide.

Troubleshooting

If you have trouble seeing, selecting, or stretching handles, see one of the following:

■ Pcell Stretch Handles Are Not Visible

■ Difficulty Selecting Pcell Stretch Handles

■ Difficulty Stretching Pcell Handles

■ Cannot See Objects Inside Pcell During Stretch



10Using the Virtuoso Custom Placer

This chapter shows you how to use the Virtuoso® custom placer to automatically placetransistors, devices, and cells in both block and cell-level designs. This chapter discusses thefollowing topics:

■ Overview on page 267

■ Setting Up the Virtuoso Layout Accelerator for Placement on page 270

■ Placement Constraints on page 276

■ Placement Parameters and Component Types on page 279

■ Setting the Placement Style on page 289

■ Running the Placer on page 307

■



Virtuoso Layout Accelerator User GuideUsing the Virtuoso Custom Placer

Overview

The Virtuoso® custom placer is an automated solution for placing transistors, devices, andcells in both block and cell-level designs. This is a generic placer that can be used for a varietyof placement styles. You control placement using topological and geometric constraints.

You begin placement by generating layout connectivity and circuit components with theVirtuoso layout accelerator (Virtuoso XL) layout generation commands. The connectivitysource can be either a Virtuoso schematic composer design or a CDL netlist.

Main Features

The maine features of the Virtuoso custom placer are the following:

■ Re-entrant automated batch placement capability within the Virtuoso Layoutenvironment

■ Connectivity and constraint -driven placement to achieve overall shortest wiring length

■ Supports a wide variety of placement styles automatically

❑ Row-based MOS

❑ Row-based standard cell

❑ Area-based analog

❑ Supports any combination of the above placement styles concurrently

■ Manual floor planning capabilities to partition placement

■ Accelerates engineering change orders

■ Placement constraints supported:

❑ Distance

❑ Alignment

❑ Grouping

❑ Symmetry

❑ Fixed

■ Automatic row generation for both device- level MOS and standard cells designs

■ Automated pin placement positioning user interface



❑ Assigns pins to any edge of placement boundary

❑ Supports ordered and unordered pins

❑ Provides the ability to fix pin positions

❑ Place groups of pins at any given spacing

❑ Multiple pins of the same net

Place Menu Command Summary

The Virtuoso XL Place menu contains these commands:

■ Pin Placement, which opens the Pin Placement form

Use this command to specify pin location constraints.

■ Placement Style, which opens the Placement Style form

Use this command to generate row information for component placement.

■ Placer, which opens the Auto Placer form

Use this command to run the automatic placer.

■ Show Congestions and Hide Congestions, which toggle the display of congestedareas on the layout

■ Rules – Open Rules, which opens the Open Place & Route Rules form

Use this command to open the placement rules from an ASCII file or the technology file.

■ Rules – New Rules, which opens the New Place & Route Rules form

Use this command to create new placement rules.

Other Commands Used with the Virtuoso custom placer

■ Design – Component Types, which opens the Edit ComponentTypes form

Use this command to update your library with information to guide the placement ofcomponents in rows, and to define parameters for MOS device chaining and folding.



Placement Styles

For row-based MOS transistor-level placement:

■ Diffusion sharing is optimized through both automatic and interactive (with the Pick fromSchematic command) transistor chaining during layout generation. Maximizing diffusionsharing minimizes the diffusion gaps in the generated layout

For standard cell placement:

■ You can place custom and standard cells in single or multiple rows. Rows can be eitherhorizontal or vertical.

Figure 10-1 Custom Cells Aligned to Top, with Same Rail Pitch but Different Heights

There are two modes of row definition: user-defined (manual) and component-assisted. Inuser-defined mode, you define the geometry of a series of rows and specify how to align andorient components in the rows. In component-assisted mode, the application defines rowgeometries for you based on area utilization goals and other design goals you specify. Thisallows the user to adjust various aspects of the design to explore different scenarios.

Note: Row-based is the most structured of all the placement styles. You define specificcomponent types to only be placed with these rows. The devices are constrained within therow to certain orientations and alignments.

Area-based is the least restrictive of the placement styles. Area placement does not requirecomponent types or other constraints. The Virtuoso custom placer will place devices withinthe placement boundary and work to reduce the overall wire length between the devices. Atthe same time individual constraints that have been placed upon the devices are honored.With area-based placements the Virtuoso custom placer has the freedom to place devicesanywhere within the placement boundary unless devices have been locked down outside ofthe placement boundary. Without individual constraints on devices or groups of devices, theplacer’s only objective is to reduce overall wire length and to achieve a balanced placement.Devices will tend to spread out using all the area allowed for placement.

Row Shape



The placement task for row-based designs typically involves these steps (explained in moredetail in “Setting the Placement Style” on page 289 ):

1. Create component types to use in assigning devices to rows.

2. For MOS device-level designs, set the parameters for device chaining and folding.

3. (Optional) Generate layout data from the schematic for critical components with theinteractive command Pick from Schematic. Make a preliminary placement of thecritical components using the object- editing commands. If critical components are handplaced to their final placement, they can be “locked” in place during automatic placementto preserve the preplacement.

4. Generate layout and a preliminary placement for the remainder of the design using GenFrom Source if you did not perform Step 3, or otherwise use Update Componentsand Nets.

5. Define rows for placement.

You can use component assisted mode only, a combination of assisted and user-defined,or just user-defined.

6. Assign component types to the appropriate rows.

7. Align objects to their respective rows.

Part of defining rows is to check that the component type, alignment, and orientation areset properly.

8. Specify the orientation of components with rows.

9. (Optional) Set confinement, grouping, and other constraints.

10. Place and constrain pins using the Place – Pin Placement command.

11. Run the automatic placer with the Place – Placer command to generate a placement.

12. (Optional) Update constraints and run Place – Placer again.

13. Repeat Step 12 as needed to further refine the placement.

Setting Up the Virtuoso Layout Accelerator for Placement

This section describes some variables you may want to set and some design style decisionsyou should make before you begin working with the placer.



Identifying the Placement Translation Rules

The Virtuoso custom placer and the Virtuoso custom router both use a rules file to define howdata should be translated between the Cadence design framework II (DFII) environment andthe placement and routing environment. In general, the router requires more elaboratetranslation rules than the placer (because the router needs to know more about the designand use of routing resources). Rules you create for the router should work properly,unmodified, with the placer too.

Cadence recommends that you have a separate translation rules file for placement purposes.You will want to translate only the minimum amount of data. Extra data not used by theVirtuoso custom placer will dramatically affect the placer’s performance, especially withmixed design styles.

Note: For CMOS device level designs, diffusion layers must be translated in order for VCPto chain devices.

Placement translation rules can be stored in the technology file or in a separate ASCII file.Specify the ASCII file in the Auto Placer form.

rulesFile The name of the rules file. If you do not set this variable, thetranslator uses the rules in the technology file. If the rules are notpresent in the technology file a warning message appearsindicating that you will have to provide a rules file.

Setting Cadence Design Framework II Environment Variables

To permit the placer to properly handle permutable pins, set the UNIX environment variableCDS_Netlisting_Mode as follows:

setenv CDS_Netlisting_Mode Analog

or

setenv CDS_Netlisting_Mode Compatibility

If you do not have permutable pins in your design, and make no other use of CDF data, youcan get faster netlisting performance by setting CDS_Netlisting_Mode to Digital :

setenv CDS_Netlisting_Mode Digital



Setting Environment Variables for the Router and Placer

Some of the .cdsenv file variables that you might set to control the Virtuoso custom routercan disrupt operation of the placer:

■ The enableAutoImport variable must be set to on by default. Check for this line inyour .cdsenv file:

iccTranslator enableAutoImport boolean t

■ The exportVersion variable, if set, must be set to the current version of the placer.The system also checks the obsolete UNIX environment variable ICC_VERSION. Thelarger of the two values is used. To avoid problems, do not set ICC_VERSION orexportVersion . If exportVersion is set in your .cdsenv file, check that it is set asfollows:

iccTranslator exportVersion int 5

Note: Several placement environment variables have equivalent variables to control theVirtuoso custom router. Placer variables always override their router equivalents duringplacement.

Several optional variables let you control the placement process. You will not need to changethese variables.

saveAsLibName The library name for the placed cellview. The default is thesource library name.

saveAsCellName The cell name for the placed cellview. The default is the sourcelayoutXL.placement allowRotation boolean t

saveAsViewName The view name for the placed cellview. The default is the sourceview name.

The example below sets all of the placement .cdsenv variables to their default values:

congestionMapLayers Controls the layers that are used for congestion. The default isstring “((layer1 purpose1) (layer2 purpose2)) .You can define up to ten layers.

globalPlacement boolean t

openWindow boolean nil

optimizePlacement boolean t

runTime cyclic "moderate"



vcpConductorDepth int 2

vcpKeepoutDepth int 2

rowGroundLayer string ""

rowGroundName string ""

rowGroundWidth float 1.0

rowPowerLayer string ""

rowPowerName string ""

rowPowerWidth float 1.0

rowSupplyPosition cyclic "Outside"

rowMOSSupplyPattern cyclic "N-P-P-N"

rowSTDAllowFlip boolean t

rowSTDSupplyPattern cyclic "G-P-P-G"

rowSTDInitOrient cyclic "R0"

rowMOSAlignment cyclic "Inside"

rowHorizontalAlignment cyclic "Center"

rowVerticalAlignment cyclic "Center"

rowHorizontalOrientations string "(R0 MY R180 MX)"

rowVerticalOrientations string (R90 MXR90 MYR90 R270)"

rowComponentTypes string "ALL"

Setting MOS Chaining and Folding Parameters

You can set several.cdsenv parameters to control MOS device folding and chaining.



lxDeltaWidth The parameter to correct for the effective width of foldedtransistors. The effective total width is defined as

Weff = M (W + lxDeltaWidth)

where M is the number of fingers and Wis the identical width ofeach transistor.

lxWidthTolerance The allowed device width variation for folding. The default is(0.0 0.0) . Provide a list of two positive numbers as the value.The first value in the list is the absolute value of the negativetolerance; the second is the positive tolerance.

lxAllowPseudoParallelNetsEnables detection of pseudo-parallel nets (nets with only twodevices connected and those devices are folded into the samenumber of fingers) if set to t . The default is nil .

To see the significance of pseudo-parallel nets, consider asymmetric series of N-transistors, A and B, tied in a series pull-down chain to ground, as shown in the following figure.

Both A and B are folded into two legs, with A1, net_PP, and B1connected in series to ground, and likewise A2 and B2connected in series to ground, with both pairs in parallel. Thenodes between A1 and B1 and between A2 and B2 are



electrically equivalent. In reality no current passes through thatconnection and it need not physically be made.

The Assura™ Diva® verification tool understands pseudo-parallelconnections and does not report incomplete nets in suchsituations.

lxStackPartitionParametersSets the device stacking partition parameters. The value is a listof two items. Use the values (-1 -1) to let Virtuoso XL decidehow to handle each stack. The default values are (1 8) .

The first value controls how far up in the hierarchy Virtuoso XLlooks for opportunities to abut devices starting from the leafnode. A value of 1 permits abutment of devices within the samegate only. A value of 2 permits abutment of any devices with thesame parent 2 levels from the leaf node. Higher values permitabutment with devices at progressively higher levels of thedesign hierarchy.

The second value sets the maximum number of devices in astack.

The example below sets all of the device chaining and stacking parameters to their defaultvalues.

layoutXL lxDeltaWidth float 0.0

layoutXL lxWidthTolerance string "(0.0 0.0)"

A

B

Original circuit

A1

B1

A2

B2

net_PP

A1

B1

A2

B2

Folded circuit withpseudo-parallel connection

Equivalent Folded circuit withpseudo-parallel net removed



layoutXL lxAllowPseudoParallelNets boolean nil

layoutXL lxStackPartitionParameters string "(1 8)"

Defining the Boundary Layer (Placement Region)

The boundary shape defines the placement region. You specify the name of the boundarylayer-purpose pair at several points in the placement and routing design flow. It is importantthat you identify this layer-purpose pair consistently. You identify the boundary layer in theboundary translation rules for the Virtuoso custom router, and you create the boundary shapeeither with the layout generation commands or by drawing a shape. When you draw theboundary layer shape, or when you define it during layout generation, be sure to use the samelayer-purpose pair that you specified in the translation rules.

The boundary layer shape must be a single rectangle or polygon. If the boundary layerconsists of more than one shape, or a nonorthogonal shape, the translator exports theenclosing bounding box as the boundary.

Note: The default layer-purpose pair in the translation Rules Editor isprBoundary drawing . The default layer-purpose pair during Virtuoso XL layout generationis also prBoundary drawing .

Using Auto-Abutment During Placement

Auto-abutment, if enabled in Virtuoso XL, is automatically performed during layout generationfor assisted MOS. In order to use auto-abutment,

■ Your components (including your MOS device parameterized cells) need to be set upcorrectly with abutment properties

For an example of such a parameterized cell, see the spcnmos and spcpmos devices inthe sample parameterized cells library. For more information, see the SampleParameterized Cells Installation and Reference.

■ Auto-abutment needs to be enabled in the Layout XL Options form

For more information, refer to Chapter 6, “Setting Up Device Abutment.”

Placement Constraints

Placement constraints let you control the placer. There are a variety of constraints that youset using several different parts of the Virtuoso XL user interface, including



■ The constraint editor, which you open with the Tools – Constraint Editor command inthe Command Interpreter Window (CIW)

Some of the procedures in this chapter suggest that you set certain types of constraints atcertain points in the design flow, but generally this is not a strict requirement. You canconstrain any device in the layout at any time, except while the placer is running. For example,you can use the placer iteratively, setting increasingly strict constraints as you refine theplacement.

Types of Placement Constraints

You can set the following constraints for placement:

■ Distance

■ Alignment

■ Grouping

■ Symmetry

■ Fixed

Important

The Pin Placement form and Edit-Other-Lock Selected command not theconstraint editor should be used for constraining pins. The constraint editor and thePin Placement form, if used interchangeably, can report constraints incorrectly.

For more information about constraints, see the Constraint Editor User Guide.

Distance Constraints

The placer will honor distance constraints between two devices. When using the nearestedge option two devices or more can be constrainted. Devices can be constrained in the X orY direction but not both. In addition the placer will align the devices in the orthogonal direction.

Grouping Constraints

A confinement constraint restricts a group of components to a rectilinear region (“fence”). Youcan optionally exclude all other, or specified, components from the fence.

The placer moves instances as necessary to implement confinement constraints even if theyare not properly positioned in the preplaced view.



To create a confinement constraint,

➤ Use the constraint editor to create a grouping constraint with a fence.

Symmetry Constraints

The placer implies an order between the pairs involved in the constraint. For example, if Q1and Q2 are constrained along the horizontal edge, then the constraint implies that Q1 is belowthe edge and Q2 is above.

Firm Grouping Constraints

A firm grouping constraint (also called a firm group or hard fence) preserves the relativeposition and spacing of a group of components.

To create a firm group,

➤ Use the constraint editor to create a grouping constraint and choose Preserve RelativePosition.

Soft Grouping Constraints

A soft grouping constraint keeps a group of components close together somewhere within thecell boundary, but it does not constrain the group itself to a particular location.

The placer moves instances as necessary to implement soft group constraints even if theyare not properly positioned in the preplaced view.

To create a soft grouping constraint,



➤ Use the constraint editor to create a grouping constraint with the cell boundary as thefence.

Pin Position Constraints

Pin constraints assign pins to a fixed location or to a particular edge and optionally order thepins along each edge according to your specification. You can also specify fixed spacing fora group of pins ordered and aligned to an edge.

To create pin constraints,

➤ Choose Place – Pin Placement in the Virtuoso XL window.

If you set pin positions with this command and later move the pin with the Movecommand, the pins are returned to the positions you set originally during placement.

Placement Parameters and Component Types

You control how components are assigned to rows, and their chaining and folding parameters,by defining component types. The CDF parameter that holds the placement parameters andtype assignments is lxComponentType . You set the lxComponentType parameter usingthe Edit Component Types which appears when you choose Design – Component Types.

Grouping constraints with PreserveRelative Position

group

Grouping constraints with aFence

fence



Defining Component Types

Important

For row-based placement styles, defining component types is mandatory.

The purpose of defining component types is twofold:

■ To identify PMOS and NMOS devices to enable chaining and folding

■ To identify groups of devices for row-based placements

Note: Currently there is no need to define component types for devices that will be placed byarea. Only assign component types for devices that will be placed within rows.

Component types are part of the library or cell information for cells in which components areplaced. You can define component types at the library level, if all cells in the library share thesame types, or you can define component types for the individual cells that will contain theplaced components. This allows you to define a set of types common to all designs in a libraryand override these for a selected set of designs.

Devices are placed within the prBoundary regardless of their component type unless;

■ Devices have been locked in place

■ The Place Selected Objects Only option is specified in the Auto Placer form.

Important

If the placer does not place a component in the rows, verify that thelxComponentType parameter has been assigned to the component and that therow definition allows for that particular component type to be placed.

MOS Transistor Chaining and Folding Parameters

MOS transistors that are candidates for chaining and folding need to have thelxComponentType parameter set with certain values. You set the lxComponentTypeparameter using the Edit Component Types form.

Important

Do not edit lxComponentType directly with the CDF Editor.



Important

Use the following parameters in the NMOSor PMOStype definitions to control devicechaining and folding during placement. You must set the lxDeviceWidth ,lxMaxWidth , lxDeviceType , and lxActiveLayers parameters; the otherparameters are optional.

Note: Terminal names are not case sensitive.

lxDeviceWidth The name of the transistor width parameter on the device mastercell. The default name is w. If you use a different name for thewidth, set this parameter to the correct name.

lxMaxWidth The maximum width beyond which devices of type NMOS andPMOS will be automatically folded when folding is enabled. If youdo not set this parameter, devices are not folded.

This value applies globally to all devices within the scope of thecomponent type definitions (the library containing the current cellor just the current cell). You can override this value using thelayout generation commands Gen from Source and Pick fromSchematic. In the Placement Style form, you can overridelxMaxWidth by setting PMOS Width Threshold and NMOSWidth Threshold.

Caution

Virtuoso XL cannot accurately enforce the value of lxMaxWidth unlessall device widths and all lxDeviceWidth values are specified consistently;for example, all in meters (10um is 1-e-5) or in all user units (10um is 10).

lxSourceName A list of instance terminal names corresponding to the MOStransistor source terminal. The default names are source andS. If you use different names, define this parameter and set itsvalue. For example: ("src" "sour") .

lxDrainName A list of drain terminal names. The default names are drain andD.

lxGateName A list of gate terminal names. The default names are gate and G.

lxBulkName A list of bulk terminal names. The default names are bulk and B.



lxActiveLayer Required spacing between components (NMOS or PMOS)diffusion layer.You must enter the layer purpose pair for theactive layer of the given MOS device type. The Placement Styleform uses the layer purpose pair to look up from the technologyfile the spacing rules between diffusion layer and MOS devicesand use it to seed the defined spacing type in fields on theAssisted MOS form. The Update Estimate command forAssisted MOS placement takes the spacing rule betweenadjacent MOS device chains into account, yielding moreaccurate estimates.

Caution

If the Component Class is set to either PMOS or NMOS, and no value hasbeen set for lxActiveLayer, a dialog box will appear informing you that thelxActiveLayer must be set.

Component Class This must be set to either NMOS or PMOS to allow the Virtuosolayout accelerator and the Virtuoso custom placer to identify theP and N MOS device types for folding, chaining, and assistedMOS operations.

Defining Components Types

1. Choose Design-Component Types.

2. In the Edit Component Types form, specify that the properties will be set for the Librarylevel or Cell level.

3. In the Types field, type the name of the type you will be using.

Types are user defined.

4. Click Add to add the type to the Type cyclic field.

Once a type is displayed in the Type cyclic field you cannot specify which cells will beassign that component type.

5. From the Cells in Design list box, select the cells by library/view name and click thearrow button to move them to the Components in Type list box.

6. Specify from the cyclic at the bottom of the form the “Component Class” the group of cellsbelongs to.

Undefined



PMOS

NMOS

STDCELL

FILLER

Component classes PMOS, NMOS, STDCELL, and FILLER will all be evaluated bycomponent-assisted row generation. Use PMOS/NMOS if you are running MOScomponent-assisted row generation. Use STDCELL if your running Standard Cellcomponent-assisted row generation. Use both if your using a combination of placementmodes.

Note: Choose Undefined if the device is none of the others.

For component-assisted row generation, you should have component types and thecomponent class assigned to cells. Otherwise those cells will not be included in theautomated row generation.

7. For PMOS and NMOS types specify values for lxDeviceWidth and lxMaxWidth forchaining and folding to occur.

8. Optionally, for PMOS and NMOS supply the following properties if they are different fromthe default names.

xSourceName

lxDrainName

lxGateName

lxBulkName

Caution

Although the Edit Component Types form will allow you to assign a cellto multiple component types this may lead to confusion and shouldprobably be avoided.

Pin Placement

You use the Place – Pin Placement command and the Pin Placement form to assign pins to:

■ Assign fixed constraints

■ Align pins to any boundary edge (supports rectilinear boundaries)



■ Assign specific pin ordering for groups of pins

■ Place pin groups with any given pin pitch spacing

■ Expand/collapse iterated bus pins (Q<7:0> = Q<7>, Q<6>, Q<5>, etc.)

■ Handle multiple pins on the same net (just like Virtuoso layout accelerator), gnd.1 gnd.2gnd.3)

■ Report pins and their assigned locations

Note: This Pin Placement form reflects all pins currently in the design.

When you click OK or Apply in the Pin Placement form, the pins move to the locations youspecify.

You can also assign instance pins to rows, by including particular pin instances in acomponent type. Use the Add Selected Components button in the Edit Component Typesform to do this.

Important

If pins are not assigned to and edge and/or location, the pins will be placedanywhere on the prBoundary.

Assigning Pins to an Edge

To specify the edge along which one or more pins should be placed,

1. Choose Place – Pin Placement.

Important

A boundary must exist in the layout window. A warning will appear in the CIWindicating that you cannot edit pin placement without a place and route boundaryshape. To generate a boundary, use the Design-Gen From Source command.



The Pin Placement form appears.



2. Select an edge in the Position pins cyclic field or choose Select boundary edge inlayout and then click on the edge or pin in the layout cellview.

You can also select an edge from the Position Pins cyclic field. The Position Pinscyclic field shows a listing of polygonal edges by their number. For example, thePosition Pins cyclic field would identify edges as “on boundary edge 2”.Boundary edges are numbered by the order in which they were created.

3. Select one or more pins in the Pins Not Preplaced list box.

Click to select a single pin or Shift-click or Control-click to select a range of pins. You canalso select pins in the layout window to highlight them in the Pins Not Preplaced listbox.

Pin selection from the Pin Placement form is different than standard object selection.

If you have iterated bus pins, you can choose to expand or collapse the bus by selectingthe bus (example: A<7:0>) and toggling the Expand button. This will expand the bus intoindividual pins, which can then be individually placed with different parameters.

4. Use the arrow buttons to the right of the Pins Not Preplaced list box to move the pinsto the Ordered pins or Unordered pins list boxes.

5. If you have ordered pins, use the Move up, Move down, and Swap buttons to arrangethem in the appropriate order. Pins are placed in the order listed, either top to bottom orleft to right depending on the edge orientation.

6. Click OK to apply the pin assignments to the current edge and close the form, or clickApply to apply the pin assignments to the current edge and select the next edge in thePosition pins field and repeat Step 2 through Step 5.

Note: Pins will not move to the boundary you assigned them to until you click OK orApply.



7. Click View Placed Pins to see a list of placed pins and the ordering, fixed, and pitchinformation you have assigned so far The information displayed in the Placed PinPositions form reflects what has been set from the Pin Placement form..

Assigning Pins to a Fixed Position

To assign pins to a fixed position within or on the boundary,

1. Choose Place – Pin Placement.

The Pin Placement form appears.

2. Select the pins in the Pins Not Preplaced list box and use the arrow button to movethem to the Ordered pins list.

You can also select pins in the layout window to highlight them in the Pins NotPreplaced list box.

3. Select one pin in the Ordered pins list box.

4. In the Fixed at X= and Y= fields, specify the pin position coordinates you want for thatpin.

You can also fix pins from within the Pins Not Preplaced list box. If the pin is fixed andnot ordered, the fixed pin is not accounted for in figuring the spacing of ordered pins.

5. Click Apply.



The pin moves to the specified position in the layout. The Committed Position labelshows its position coordinates. Coordinates refer to the center of the pin.

6. Repeat Step 3 through Step 5 for each fixed pin.

You can click Default to return all pins to their unplaced positions below the designboundary.

You can also fix pin locations by moving the pin to the exact location and then fixing the pin.

1. Choose Edit-Move and move the pin to the desired location.

2. In the Pin Placement list box select the pin from the Pins Not Preplaced or Orderedpins listbox.

The coordinates are updated in the Fixed at X= and Y= fields.

3. Click Apply or OK.

Assigning Spacing Between Pins

To set the exact distance between two or more ordered pins, or between the pins of a bus(iterated) pin using the Pin Placement form,

1. Move the pins to the Ordered pins list box.

2. Highlight the pins whose spacing you want to specify.

3. Specify the distance in the Pin Pitch field.

4. To list the pins of a bus (iterated) pin individually in the Ordered pins list box so that youcan assign spacing to them individually, select the pin in the Ordered pins list box andclick Expand in the Iterated Pins section.

If you specify spacing between a pin and an iterated pin, the software applies the spacebetween the last pin of the iterated pin and the individual pin.

5. Click Apply.

The pin moves to the position specified.

Pin pitch values are only enforced if two pins are adjacent on an edge, even if spacing isset between two non-adjacent pins.

You will receive a warning in the CIW if the pitch for the pins cannot be satisfied. Alsonotice that the pins have not moved.



Setting the Placement Style

You define where in the layout you want to place transistors and other design elements withthe Place – Placement Style command and the Placement Style form.

Note: You assign components to rows based on their component type. Before you can setthe row placement style, you or the library developer must first define the component typesfor placement.

There are two row definition modes for the Placement Style form: Component-Assisted andUser-Defined.

■ The component-sssisted mode automates typical styles of MOS and standard cellplacement

■ The user-defined mode offers greater flexibility but less automation and supports bothtransistor- and cell-level placement

Component-Assisted MOS Placement

The Component-Assisted MOS row definition mode helps you define rows that fit your areabudget. You can change the independent design variables that constrain the row shapes andobserve their effect on area utilization and folded transistor widths.

Limitations

The component-assisted mode restricts the placement style to the most typicalarrangements. There are a few limitations that are not present in the user-defined rowdefinition mode:

■ All rows must be horizontal or vertical



■ All rows have the same width and span the entire placement region

■ Each row contains either NMOS or PMOS devices but not both and not any othercomponent types

■ The number of N and P rows is the same

■ There is a regular arrangement of alternating N and P rows that follows one of thesepatterns:

❑ NP

❑ PN

❑ NPPN

❑ PNNP

■ All rows have the same device alignment relative to the devices in adjacent rows: inside,outside, or center

■ All rows have the same permitted device rotation and mirroring

■ The rows must be entirely contained within the boundary region

If any of these limitations is not acceptable, you can either

■ Define the rows in the user-defined mode

■ Define the rows as completely as possible using the component-assisted mode and thenrefine the definitions in the user-defined mode

■ Use assisted mode on either standard cell or MOS, but not both at the same time.

About Calculated Values

For both NMOS and PMOS transistors, the system calculates the number of transistors andthe minimum, maximum, and average transistor widths. To update the displayed values, afteraltering variables, select Update Estimate.

The system also calculates the normalized percentage of horizontal and vertical areautilization for the placement region. (In other words, a value of 100% in the Horizontal fieldmeans that the entire width of the placement region is used by the devices). If there are toomany devices to fit within the placement region, rows may overlap or extend outside theplacement region. In this case, one or both of the Region Utilized values at the bottom ofthe form (Horizontal and Vertical) may be greater than 100%.



Using the Component-Assisted MOS Mode

To use the Component-Assisted row definition mode,

1. Choose Place – Placement Style.

The Placement Style form appears

2. Click the Component-Assisted option opposite Row Definition.

3. Click the MOS option under Component-Assisted.



4. Click Show All Row Data to expand the form that lists the rows and their specificationsand updates.

5. In the Placement Region Properties section of the form

❑ Define the size and location of the placement region using the Estimate Area Bycyclic field and choosing Minimum Rows Needed, Number of Rows, HorizontalUtilization (%), Vertical Utilization (%) or Minimum Row Space.

The placement region should be contained within the boundary. For example, youmight restrict assisted placement to the lower part of the boundary, leaving the upperpart available for manual placement. Or, you might leave space around theperiphery for routing.

❑ Type the dimensions of the row(s) in the Width and Height fields.

❑ Type the X and Y coordinates of the location where you want the row in the Originfields.

You can see the X and Y coordinates of the cursor position in the status line at thetop of the layout window. If you do not type any coordinates, the new row is placedat the lower left corner of the design boundary.

❑ Specify the placement region manually in the layout window, click Draw Region.

The layout window prompts you to point at the first corner of the region’s rectangle.



❑ Click Clear Region to remove the region created by the Draw Region option.

6. The row properties are automatically updated.

Note: If rows are already defined, click on the row that you want to edit in the Show All RowData section of the Placement Style form. The Row properties are updated in the Name field.

7. Set the orientation (Direction) of the row(s).



8. In the Supply Properties section of the form, if applicable,

❑ Choose a layer and type values in the Net Name and Width fields for power andground.

The layers are valid layers that are not used as vias or contacts.

❑ In the Pattern cyclic field, choose a pattern for the alternating N and P rows.

❑ In the Position cyclic field, choose where the rows should go (Inside, Outside, orCenter).

9. In the Component Properties section of the form,



❑ In the Alignment cyclic field, choose Inside, Outside, or Center.

Note: Alignment is by the origin of the instance.

❑ Set the alignment of the component(s).

❑ Type in the minimum width (Width Threshold) and required diffusion spacebetween components within the row (Diffusion Spacing) for the PMOS and NMOStransistors.

10. Click Update Estimate to calculate the row count, area utilization, device count, anddevice widths.

N-row

P-row

P-row

N-row

P-row

N-row

Inside (NPPN pattern)

P-row

N-row

Outside (NP pattern)

P-row

N-row

Center



The system regenerates folded transistors using the new values. The Statistics sectionat the bottom of the form is updated with the percentage of the region utilized and widthinformation about the PMOS and NMOS components.

11. Evaluate the device counts against the need to generate equal numbers of P and N rows.Evaluate the area utilization based on routability considerations. If necessary, changethe Number of Rows or PMOS Width Threshold or NMOS Width Threshold forfolding. Click Update Estimate to update the calculated estimates.

Important

This command enables Virtuoso XL transistor chaining and folding even if you haveturned off these options in the Layout Generation Options form.

If necessary, redefine the placement region and begin again with Step 4.

Note: After you click Update Estimate, if you make extensive changes to device foldingand chaining choices (either through automatic layout generation or interactive devicefolding), the estimates you calculate in Step 10 may become invalid.

12. Click Apply to save your row definitions.

Caution

When you click Ok or Apply in the Placement Style form, the originallayout is regenerated.

Using the Component-Assisted Standard Cell Mode

To use the Component-Assisted row definition mode,




The Placement Style form appears

.

2. Click the Component-Assisted option opposite Row Definition.

3. Click the Standard Cell option under Component-Assisted.

4. Click Show All Row Data to open a list box in the form that lists the rows and theirspecifications and updates whenever you click Apply. (lxActiveLayer is a manualway to set this variable)

5. In the Estimate Area section of the form,

❑ Define the size and location of the placement region using the Estimate Area Bycyclic field and choosing Minimum Rows Needed, Number of Rows, HorizontalUtilization (%), Vertical Utilization (%), or Minimum Row Space.

The placement region should be contained within the boundary. For example, youmight restrict assisted placement to the lower part of the boundary, leaving the upperpart available for manual placement. Or, you might leave space around theperiphery for routing.


❑ Type the X and Y coordinates of the location where you want the row in the Originfield.



You can see the X and Y coordinates of the cursor position in the status line at thetop of the layout window. If you do not type in any coordinates, the new row is placedat the lower left corner of the design boundary.

❑ To specify the placement region manually in the layout window, click Draw inLayout.

The layout window prompts you to point at the first corner of the region’s rectangle.

6. In the Row Properties section of the form

❑ Type the name of the row(s) to be designed in the Name field.

❑ Set the orientation (Direction) of the row(s).

❑ If you want to use filler cells that you have defined in the Edit Component Types formbetween the other cells in the row, click Use Filler Cells and type the names of thefiller cells into the field or click Choose Types and choose the names of the fillercells from the list that appears in the Choose Component Types form.

7. In the Supply Properties section of the form

❑ If applicable, choose a layer and type values in the Net Name and Width fields forpower and ground nets.



❑ In the Pattern cyclic field, choose a pattern for the alternating ground and power (Gand P) rows.

8. In the Spacing field, type in the spacing you want between the rails.

9. Click Update Estimate to calculate the row count, area utilization, device count, anddevice widths.

The system regenerates transistors using the new values. The Statistics section at thebottom of the form is updated with the percentage of the region utilized.

10. Evaluate the device counts against the need to generate equal numbers of P and G rows.Evaluate the area utilization based on routability considerations. If necessary, changethe Width or Height fields or PMOS Width Threshold or NMOS Width Thresholdfields for folding. Click Update Estimate to update the calculated estimates.

Note: After you click Update Estimate, if you make any changes to rowdefinitions(either through automatic layout generation or interactive device folding), theestimates you calculate in Step 10 will become invalid.

PG

Vdd

Gnd

GP

Gnd

Vdd

PGGP rails not shared

GPPG shared rails

GP

PG

GND

Vdd

Gnd



11. Click Apply to save your row definitions.

User-Defined Row-Based Placement

The User-Defined mode for row definition lets you define row boundaries flexibly. Forexample, you can draw rectangles to delimit individual rows. Use the manual mode forplacements above the device level or for MOS device placement styles that are notaccommodated in the Assisted MOS mode.

Figure 10-2 on page 300 shows an example of a placement region with four rows. Rows 1and 2, the lower rows, span only half the placement region. Rows 3 and 4 span the entireplacement region.

Figure 10-2 Examples of Rows

Defining Rows Manually

To define rows or columns manually,


The Placement Style form appears.

2. Choose the User-Defined radio button opposite Row Definition.

The MOS and Standard Cell options are grayed out.

3. Click Show All Row Data if you want to see the names and characteristics of the rowsas you create them.

4. Use the fields under Row Properties to define one or more rows.



❑ Type the name of the row(s) to be designed in the Rows field. This is optional.

❑ Set the orientation (Direction) of the row(s).


❑ Type in the number of rows you want in the Num Copies field.

If Num Copies is greater than 1, then this will create an array of rows with the samedevices and attributes at a fixed spacing between adjacent rows.

❑ Type the X and Y coordinates of the location where you want the first row in theOrigin field.

You can see the X and Y coordinates of the cursor position in the status line at thetop of the layout window. If you do not type in any coordinates, the new row is placedat the lower left corner of the design boundary.

❑ In the Spacing field, type the spacing you want between rows.

❑ Specify the component types of filler cells you want to place in the row(s), turn onthe Use Filler Cells option and either type the name of the components in the fieldor click on Choose Types and click on the names in the Choose Component Typesform.

5. In the Component Properties section on the form,

❑ Set the alignment of components with respect to the row(s).

❑ Set the Orientation (allowed orientation of components to be placed in these rows)of the row(s).

Deselect some orientations if necessary so that only the legal orientations areavailable within the row(s).

❑ Click Choose Types and select the names of the cells from the list that appears inthe Choose Component Types form.

6. Click the Create New or the Update button to save the settings for the row(s).

The row(s) appear in the layout window and in the row data list field, if present. TheNumber of Rows indicator updates to show the number of rows in the design.

Drawing Rows

You can define rows by drawing them, one at a time, in the layout window. Select Draw inLayout and define the placement region for assisted MOS or cells.



Redefining a Row

Rows are actual database objects you can move and stretch graphically. To graphically editrows make sure that the Row drawing layer purpose pair is a valid layer and made selectablein the Layer Selection Window (LSW)..

You can delete a row either by graphically selecting it on the layout window and deleting it, orselecting it from the Show All Row data list and selecting the delete button to update the list.

Setting Up Power and Ground Rails

You can define arrays of multiple rows in one step to create alternating rows with the samedefinitions. This arrangement facilitates the layout of power lines. Figure 10-3 on page 302shows a portion of a buffer array with alternating NMOS and PMOS transistors in columns.

Figure 10-3 Alternating Vertical NMOS and PMOS Rows

P-row

N-row

P-row

N-row

P-row

N-row

P-row

N-row

NPPN Array Spacing

NPPN Array Spacing

NPPN Array Spacing

NPPN Array Spacing



To define the placement style for these eight rows, you define two arrays of components. Todefine the PMOS rows, follow these steps:


2. Choose User Defined.

3. Set Num Confine to 4.

4. In the Run Properties area, set the appropriate spacing between the rows in the PMOStype Spacing field.

5. Click on Create New.

Now define the NMOS rows:

1. Set Num Copiesto 4.

2. In the Run Properties area, set the appropriate spacing between the rows in the NMOStype Spacing field.

3. In the Component Properties Area, set alignment, overlap, and type.

The row setup is now complete.

For other arrangements of power lines between rows, you might, for example, need to definearrays of every fourth or eighth row in order to achieve the desired mirroring pattern.

About Horizontal and Vertical Rows

You can define both horizontal and vertical rows for placement. To do this, set the desireddirection as you define each row or set of rows.

Figure 10-4 on page 304 shows how the Width and Height parameters should be set forhorizontal and vertical rows. As this figure illustrates, the Width is measured along thedirection of the rows.



Figure 10-4 Setting Width and Height for Horizontal and Vertical Rows

1. Row direction is Vertical, Width is 10, Height is 4, Spacing is 2.

2. Row direction is Horizontal, Width is 10, Height is 4, Spacing is 2.

About Device Orientation

There is no implied rotation of devices in vertical rows. The Orientation value you specify inthe Placement Style form is always relative to the master cell coordinates. Figure 10-5 onpage 304 shows the undesired result of placing the same device with orientation R0(unrotated) in both a horizontal and vertical row.

Figure 10-5 Rotation of Devices in Vertical and Horizontal Rows

(0,0)(0,0)

1 2

wid

th

height

height

width

UnrotatedMaster



About Device Abutment and Orientation

For MOS row placement, diffusion would be abutted along the row direction as shown inFigure 10-6 on page 305

Figure 10-6 MOS Row with Diffusion Abutted Along the Row Direction

The permitted orientations in the example in Figure 10-6 on page 305 would depend on theorientation of the transistor in its master cell. Assuming that the polysilicon shape is verticalin the master cell for the transistor, for a horizontal row the reasonable orientations would beR0 (unrotated), R180 (rotated 180 degrees), MX (mirrored along the X-axis) and MY(mirrored along the Y-axis). R90 would not be an advisable orientation.

For standard cells, the power and ground rails would run parallel to the row direction, asshown in Figure 10-7 on page 305 .

Figure 10-7 Standard Cells with Power Rails Parallel to the Row Direction

About Space at the End of a Row, and Row Compaction

The placer can abut MOS devices so that rails meet each other. However, when placingstandard or other cells that are not set up for device abutment, the placer does not compactthe rows to ensure that the rails abut.

UnrotatedMasterPermitted Orientations in row: R0, R180, MX, MY

Row Shape



The placer never extends rails to the row boundary. If the cells do not entirely fill the row, youmay need to extend the rails or use filler cells.

Figure 10-8 on page 306 shows standard cells placed within a row. The cells do not abut eachother and the power rails do not extend to the right side row boundary.

Figure 10-8 Row with Extra Space

Choose Component Types Form

From the Placement Style form, the Choose Types button opens the Choose ComponentTypes form. Use this form to identify the component types to place in the currently active rows.



Below the Search button is a list of component types in the current design. Use the mouseto highlight the types you wish to include in the Component Types field of the PlacementStyle form, and then click OK.

Search scrolls the list to the component type name you type into the field. The name mustmatch exactly. You can then highlight the name. This field is useful if you have a long list oftypes.

Running the Placer

You launch the Virtuoso custom placer with the Auto Placer form. The placer runs in batchmode, reporting its status in the Virtuoso XL Placement Status window.

Note: While the placer is running on a cellview, the cellview is switched to read-only modeand you cannot perform edits on it, but you can edit any other cellview. When the placer hasfinished running, the cellview is switched back to edit mode.

After the placer finishes, the placed cellview appears (if you are updating the source view withthe placed view, or if you are creating a new view and chose the Open Window option).

After placement, you can iteratively



■ Lock the position of components whose placement is good

■ Refine the constraints on other components to better guide the placer

■ Rerun the placer as needed to improve the placement results

Prerequisites to Placement

To prepare for placement,

1. Set any necessary UNIX and DFII environment variables before launching the Cadencesoftware.

See “Setting Up the Virtuoso Layout Accelerator for Placement” on page 270 for moreinformation about setting variables.

2. If you only want to place some of the components, select the components to be placedin the cellview window and turn on Place Selected Objects Only.

Running the Placer: Initial Placement

To start the automatic placer and perform an initial placement of the selected components,

1. Choose Place – Placer.



The Auto Placer form appears.

2. Turn on Global Placement.

3. Set the other placement options on the left side of the form, as needed.

4. To save the placed cellview with a different view name,

a. Click Save As

b. Fill in the Library, Cell, and View field..

You can also change the library or cell name, or browse to choose the cellviewname.

5. Click OK or Apply.



After the placer initializes, the status window appears.

Important

The text columns in the Virtuoso XL Placement Status form do not align if a variablepitch font is used. You must use a fixed size text font. The default text font is a fixedsize text font. You can change the text font by using CIW-Options-UserPreference.

The placer moves pins that were not assigned to placement information inside the designboundary and aligns to any boundary edge.

You can use the Edit – Undo command to discard the placement results.

Troubleshooting Placement Results

This section discusses common placement problems and some possible solutions.

Problem: Components were placed with overlaps.

File Help

Starting placement of ( “Overview” “MUS21” “preplaced” ) at Jul 14Device level placement is calledDevice level placement is called

Virtuoso XL Placement Status



Solution: The boundary region or the rows are too small. Redraw the boundary or rows.

Refining Placement Results

To refine the placement results,

■ Set grouping and fixed constraints by choosing Tools – Constraint Editor in the CIW

■ Redefine the row boundaries

■ For MOS transistor-level designs, modify the layout for one or more transistors with theEdit – Transistor Chaining and Transistor Folding commands

Running the Placer: Detailed Placement

To perform a detailed placement after refining the constraints,

1. Choose Place – Placer.

The Auto Placer form appears.

2. Deselect Global Placement.

3. Choose Optimize Placement.

4. Continue as with initial placement, beginning with Step 4.



Showing Congestions

After you have run placement, you can use the Place – Show Congestions command tohighlight areas where design elements are so close together that routing might be a problem.

To show congested areas in your placed desig,

➤ Choose Place – Show Congestions.

The system surrounds congested areas with tiles on different highlight layers showingdegrees of congestion. The layer purpose pairs designFlow drawing throughdesignFlow drawing9 are used to show congestion. Each layer purpose pairrepresents different regions of routing resource utilization. For example, the designFlowdrawing layer purpose pair represents utilization from 0 to 11.111111%. ThedesignFlow drawing1 layer purpose pair represents utilization from 11.111112 to22.222222%, until layer designFlow drawing8 which represents utilization of88.888888%. Layer purpose pair designFlow drawing9 represents 100% utilization.

The command name changes to Hide Congestions.

To remove the highlighting around congested areas in your placed design

➤ Choose Place – Hide Congestions.

The highlighting surrounding the congested areas disappears.

The command name changes to Show Congestions.



Information About Forms

Auto Placer Form


Edit Component Types Form

Pin Placement Form

Placement Style Form (Component Assisted)

Placement Style Form (User-Defined)



Auto Placer Form

Preserve Logical Hierarchy is used with CMOS designs that have been generated withchaining. This option does not work with devices that have been manually abutted becauseclustering needs chaining information.

Place Selected Objects Only places only the objects in the selected set. If this option isnot selected, all objects in the cellview are placed.

Allow Rotation rotates the components as a part of optimization. If this option is turned off,the components are moved, not rotated.

ECO Mode places any components you had left unplaced outside the design boundary butdoes not touch the placement of components that are already placed inside the designboundary.

Global Placement places components without regard to their initial placement. Overlapviolations between components might be ignored. The placer optimizes global objectivessuch as total wire length. Typically, you would select this option the first time you place adesign or to discard previous unsatisfactory placement results.

Optimize Placement performs a detailed placement. This option lets the placer run until theobjective cost is achieved.

Runtime controls how long the optimizer tries to optimize to achieve the best possibleplacement. Choices are quick, moderate, and optimized.

Run Row Spacer optimizes the placement of rows, not the components inside them, forrouting.

Reserve Space For Routing (%) slider lets you indicate the percentage of extra space,above what the components require, you want left for routing.

Insert Filler Cells fills the spaces where there are no components in the rows with the fillercells you defined in the Component Types form.

Define Areas for Instances allows you to define regions for components that do not belongto any row.

Save As lets you specify a new library, cell, and view name for the placed cellview. By default,this option is disabled. If you do not select this option, the current and placed names are thesame and these fields are grayed out.



Important

Be sure to save the placed (output) cellview to disk before translation if you want topreserve any edits that are still in memory.

Edits to the output cellview are not saved to disk automatically before placement. To discardthe changes the placer makes, do not save the output cellview. However, this also discardsany edits in memory. This is true both

■ When you let the placer update the source layout cellview

■ When you specify a different cell or view name, but that cellview happens to be open andmodified in another window

Library sets the new library for the placed cellview.

Cell sets the new cell name for the placed cellview.

View sets the new view name for the placed cellview.

Browse displays a library browser to let you choose the new name.

Open Window displays the placed view in a new window after placement, if it is not alreadydisplayed. Otherwise, the system updates the output view in an existing window.

Rules File lets you type the name of a rules file.

Set File opens the Open File window, which displays the files on your system so that you canchoose a rules file.




Search scrolls the list to the component type name you type into the field. The name mustmatch exactly. This field is useful if you have a long list of types. To select a device or deviceson which you want to perform an action, click on the device you want to select, or hold downControl and click to select more than one device.



Pin Placement Form

Position pins specifies an edge.

Select boundary edge in layout lets you click in the layout to select an edge or pins in thelayout.

View Placed Pins opens the Placed Pin Positions window, which displays a list of all theordered and unordered pins for which you have assigned positions, the side to which they areassigned, the order in which they are assigned, and whether or not they have a fixed positionor spacing assigned to them.

Pins Not Preplaced lists all the pins that have not yet been placed.

Ordered pins lists those pins you have placed on the selected boundary whose relativeordering should be preserved. Pins are placed in the order listed, either top to bottom or leftto right depending on edge orientation. Move pins into this list by clicking on the arrows to theleft of this list. Move pins between this list and the Unordered pins list box using the arrowsbetween the two lists.

The top pin on the list is placed at the top of a vertical edge or the left of a horizontal edge.

Move up moves the selected pins up in the Ordered pins list box.

Move down moves the selected pins down in the Ordered pins list box.

Swap inverts the order of two selected pins in the Ordered pins list box.

Unordered pins lists those pins you have placed on the selected boundary whose order isunimportant. Move pins into this list by clicking on the arrows to the left of this field.

Pin Pitch lets you assign a specific distance between two or more pins highlighted in theOrdered pins list box.

Committed Position shows the location coordinates of a single pin or the last pinhighlighted in the Ordered pins list or Unordered pins list.

Fixed at is active only when you select a single pin from the Pins Not Preplaced orOrdered pins list. To place a fixed pin, select it in one of the list boxand enter values in theX= and Y= fields.

X= specifies the X coordinate of the selected fixed pin.

Y= specifies the Y coordinate of the selected fixed pin.



Note: If you do not enter values for the pin grid fields, the placer places pins on themanufacturing grid. Consequently, unconstrained internal pins are placed on themanufacturing grid. (For more information about grids, see Chapter 2 of the VirtuosoCustom Placement and Routing Preparation Guide.)

Iterated Pins lets you expand or collapse the listing of iterated (bus) pins.

Expand expands the pin lists to show all bits of one or more iterated pins.

Collapse condenses the pin lists to show bus notation for one or more iterated pins.

All performs the expand or collapse function on all the pins in the Ordered pins list box.

Selected performs the expand or collapse function on highlighted pins in the Orderedpins list box.



Placement Style Form (Component-Assisted Placement)

Row Definition lets you select the placement mode of row-based placement.

Component-Assisted lets you define rows with full flexibility for device or cell-levelplacement styles.

MOS lets you specify the MOS devices you want to place so that the software cancompute the number of rows you need for those devices.

Standard Cell lets you describe rows of standard cells you want to place so thatthe software can compute the number of rows you need for the standard cells.

User-Defined lets you quickly define rows any way you want.

Number of Rows shows how many rows you have entered. The number of rows incrementseach time you click Update after adding new rows.

Show All Row Data opens a list field that shows the names and information about the rowsyou have entered.

Update Estimate recalculates the estimated count, width, and utilization values, includingthe Row Count value. The system also regenerates folded transistors. This button isdisabled if the form values have not been modified and there is no need to recalculate theestimates.

Update Rows updates the Number of Rows counter and the information in the Row Datafield.

Delete Rows removes selected rows from the Row Data field.

Estimate Area By: lets you select the method the software uses to calculate the size ornumber of rows to draw (Minimum Rows Needed, Number of Rows, HorizontalUtilization (%), Vertical Utilization (%), Minimum Row Space. Minimum Row Spaceis entered in user units, the other options are unitless.

Choose the parameters in the cyclic fields and then enter numeric values. The default is thewidth and height of the top-level boundary.

Width lets you enter the width of the row you want (larger than the height if you wanthorizontal rows).

Height lets you enter the height of the row you want (larger than the width if you wantvertical rows).

Origin:



X sets the X coordinate of the lower left corner of the lowest numbered row being edited.

Y sets the Y coordinate of the lower left corner of the row.

Draw Region lets you use the mouse to specify the corners of a rectangle in the layoutcellview. The rectangle sets the placement region and the X, Y, Width, and Height fieldsare filled in with the appropriate values.

Clear Region removes the drawn region.

Row Properties:

Name lets you type a name for your row(s). If you do not specify a row name, the defaultrow name is assigned, starting with Row1, Row2, etc.

Direction is the default direction for rows, either Vertical or Horizontal.

Use Filler Cells lets you enter the names of the Filler cells you defined in the EditComponent Type form. (This field does not appear when the Component-Assisted MOSoption is active).

Choose Types displays the Choose Component Types form, which lets you browse thelist of available component types you entered in the Edit Component Type form. (Thisfield does not appear when the Component-Assisted MOS option is active).

Supply Properties lets you specify information for power and ground pins.

Layer lets you specify the layout on which the rows are drawn.

Net Name lets you specify the net to which to which the rows belong.

Width lets you specify the width of the supply rails.

Pattern specifies how N and P devices alternate between rows or how PG and GP cellsalternate when the Component-Assisted Standard Cell option is active.

Position controls the relative position of rails with regard to rows.

PPP

power p-row

n-row

ground

NN N



Spacing controls the distance between the rows. (This field does not appear when theComponent-Assisted MOS option is active).

Component Properties:

Alignment controls the relative alignment of devices in adjacent rows.

Inside aligns the P and N devices are aligned toward each other.

Outside alignment aligns the devices away from each other.

Center aligns the devices with the row center line. (This field does not appear when theComponent-Assisted Standard Cell option is active).

Orientations sets the allowed orientations and rotations for devices. By default, theorientations R0, MY, MX, and R180 are selected.

Width Threshold is the maximum width allowed after MOS device folding is performed.The default value comes from the CDF data for the device. If the threshold value is 0, thevalue of lxMaxWidth you set in the Edit Component Type form is used. (This field doesnot appear when the Component-Assisted Standard Cell option is active).

Spacing sets the minimum spacing required between adjacent MOS chains. This valueaffects the estimation of the number of rows required. (This field does not appear whenthe Component-Assisted Standard Cell option is active).

Statistics:

Region Utilized (%) displays the estimated Horizontal and Vertical area utilizationbased on the width threshold and placement region size.

Count is the number of MOS transistors, after folding.

Max Width is the maximum transistor width.

Min Width is the minimum transistor width.

Avg Width is the average transistor width.



Placement Style Form (User-Defined Placement)

User-Defined lets you quickly define rows for typical MOS transistor-level placement styles.

Number of Rows shows how many rows you have entered The number of rows incrementseach time you click Update after adding new rows.

Show All Row Data opens a list field that shows the names and information about the rowsyou have entered.

Update updates the Number of Rows counter and the information in the Row Data field.

Delete removes selected rows from the Row Data field.

Row Properties:

Name lets you enter a name for your row(s). If you do not enter a row name, the defaultrow name is assigned, starting with Row1, Row2, etc.

Direction is the default direction for rows, either Vertical or Horizontal.

Width is the row width, independent of the row direction. Height should properlyaccommodate this device width.

Height is the row height.

Num Copies lets you define how many copies of the row you want to make.

Origin:

X sets the X coordinate of the lower left corner of the lowest numbered row being edited.

Y sets the Y coordinate of the lower left corner of the row.

Diffusion Spacing is the row-to-row spacing when you are defining multiple rows. Thedefault is 0. This field is inactive when you are editing just a single row.

Use Filler Cells lets you define the filler cells (types) permitted in these rows.

Choose Types displays the Choose Component Types form, which lets you browse thelist of filler cells you have defined. No other types of cells are displayed in the form.

Component Properties:

Alignment sets alignment options for the cells in these rows. Valid values are Top,Bottom (horizontal rows only), Center, Origin, and Any (meaning anywhere within therow boundary, not necessarily in a single row or in any sort of alignment with adjacentdevices in the row).



Orientation sets the permitted orientation and mirroring of cells in these rows, relativeto their unrotated master. By default, all orientations and mirroring are permitted.

Types is a list of groups of cells (types) permitted in these rows. By default, all types areallowed in all rows.

Choose Types displays the Choose Component Types form, which lets you browse thelist of available component types.



11Preparing Your Design for Routing in theVirtuoso Layout Accelerator

This chapter explains how the Virtuoso® layout accelerator (Virtuoso XL) processesconnectivity information and presents several ways to prepare your design for routing. Thischapter discusses the following topics:

■ Understanding Connectivity on page 325

■ Selecting Layers on page 328

■ Connecting Nets on page 328

■ Checking Connectivity with Flight Lines on page 335

■ Checking Connectivity with Markers on page 335

■ Defining Physical Vias on page 338

■ Using the Virtuoso Compactor on a Routed Design on page 343

For information about how to use the Virtuoso custom router to route your design, see theVirtuoso Custom Placement and Routing Preparation Guide.

For information about running the router, see the Online Help (available in PDF format inyour router installation hierarchy).


Virtuoso Layout Accelerator User GuidePreparing Your Design for Routing in the Virtuoso Layout Accelerator

Understanding Connectivity

Virtuoso XL accepts only connections

■ On layers that have been defined in the technology file as lxExtractLayers (andon no other layers)

■ Between two touching shapes or instance pins on the same layers

■ Between two touching shapes or instance pins on different layers if the layers have beendefined in the technology file as equivalent Layers or one of them is defined as aviaLayer

■ Between two layers by means of a contact instance having a pin on each layer and bothpins on the same terminal

metal2

via with pin on metal1 and pin on metal2 on sameterminal

M1_M2metal1

In the technology file:metal1 and metal2 are lxExtractLayers



■ Between two layers by means of a via

Note: By default, Virtuoso XL uses symbolic vias defined in the technology file. You can alsodefine physical vias using the Virtuoso layout editor if you need shapes not supported by thesymbolic via.

metal1

via layer

metal2

In the technology file:metal1 and metal2 are lxExtractLayersvia layer is set to viaLayers



When a connection occurs between wires inside an instance, the connectivity extractorchecks connectivity for as many levels of hierarchy as specified in the Layout XL Optionsform.

To verify that all connections are made in the layout as specified in the schematic, use anAssura® verification product, a Dracula® verification tool, or an Assura hierarchical physicalverification product to run a layout versus schematic (LVS) check on the completed design.

Note: For hierarchical connectivity to work for pcells, the connectivity must be defined on theshapes within the pcell. You can assign connectivity for the pcell shapes by descending intothe pcell and using the Connectivity – Add Shape to Net command. For the non-pcells,you can assign connectivity interactively using the Connectivity – Assign Nets commandor using Cadence® SKILL functions.

The connectivity extractor recognises connectivity only if all the shapes on a net haveconnectivity information. Otherwise, it reports incomplete nets even though the router reportsthat the design is 100% routed.

Caution

Do not use mosaics to make connections in Virtuoso XL. the connectivityextractor cannot use them.

Cell boundary

Pin AValid connection

Valid connection if wires are on the same net

If the wire touches

connected to any instancepin, it creates a shortand generates a marker.

an internal net not

and extraction level is setto greater than 0.



Selecting Layers

To select the layer you want to use to connect design components, do this.

➤ Select a layer in the Layer Selection Window (LSW).

The layer you select appears in the current layer display.

Note: The layout window Create – Path command automatically changes the current layerto the layer of the first pin you select to start the path.

Connecting Nets

To create paths that make the required connections between each device in the layout, youcan use

■ The layout window Create – Path commandThe Create – Path command highlights the net you are wiring in both the schematic andthe layout.

Current layer display



■ Design shapes created by the layout editor: the Create – Rectangle, Create –Polygon, Create – Pin, and Create – Conics commands, which connect two or moredesign elements

■ The Virtuoso custom routerFor information about using the router, see the Virtuoso Custom Placement andRouting Preparation Guide.

Create – Path

Create – Conics – Ellipse

Create – Polygon

Create – Rectangle



Creating Paths

To create paths follow these steps.

1. From the layout window, choose Create – Path.

2. In the layout window, click where you want the first point of the path.

Virtuoso XL highlights the corresponding net in the schematic and the layout.

Note: You cannot start a path where there is a short.

3. Continue clicking points to draw the path..

Virtuoso XL creates the path using the layer of the shape where you click first. If you clickwhere there is no shape, Virtuoso XL uses the layer selected in the LSW.

The default width of the path is the minWidth layer property defined in the technologyfile.

4. To change the width of the path, press F3 to open the Create Path options form andchange the path width on the form.

To erase the segments you draw, press the Back Space key.

If you try to start a path or a shape where there is already a path or a shape on morethan one layer, a dialog box appears that shows you what layers are active and asks youto choose one.

Each click drawsanother segment.

✘✘

✘ ✘

1st click

Press the Return key toclose the path.

The finishedpath appears.

You draw the pathcenterline.

2nd click 3rd click Press Return



5. To complete the path, press Return on the last point.

Note: Do not double-click to end a path. If you have set the layout window Design –Options – Display command to x-first or y-first snap modes, the double-click mightmake a notch in the path, which triggers an error message and can cause errors in masklayout.

6. To change the current entry layer, choose a different layer in the LSW.

The current entry layer in the LSW is updated. The path you create uses the new layer.



Connecting Nets with Path Stitching

You can draw a path that switches from one layer to another, automatically placing anappropriate contact at the point where the layer changes. This is often called “path stitching.”To perform path stitching, follow these steps.

1. While the Create – Path command is active, press F3.

The Create Path form appears.



2. To drop a via from the current layer to a new layer and change the current layer, choosea different layer in the Change To Layer cyclic field.

3. Change any other options as required.

4. On the layout window, click where you want the via placed.

Virtuoso XL places the via between the two layers. The next segment you draw appearson the new layer.

You can then switch back and forth between layers, choosing the new layer from theCreate Path form each time you change layers.



Connecting Nets with Design Shapes

To create design shapes (rectangles, polygons, or conic shapes—circles, ellipses, anddonuts) that you can use to connect devices, follow these steps.

1. From the LSW, choose the layer to use.

2. From the layout window menu, choose the Create command and the design shape youwant (Polygon, for example).

3. If you want to change the angle at which you can move the cursor as you draw thepolygon, press F3.

Note: There are no options forms for the Create – Rectangle command or the Create– Conics commands.

The Create Polygon form appears.

4. Change the Snap Mode to the setting you want.

5. Click to place the first point.

6. Continue clicking points to draw the shape.

Press the Back Space key to undo the previous segment you entered.



7. To complete the shape, press Return .

Note: TheVirtuoso compactor does not compact nonorthogonal shapes or shapes other thanpaths, except for pins.

Checking Connectivity with Flight Lines

To see nets for which connectivity has not yet been made, you can use theShow Incomplete Nets command to turn on flight lines in the layout window. Flight linesshow uncompleted electrical connections between devices in each net. The CommandInterpreter Window (CIW) reports how many uncompleted nets you have.

If you draw a path between two components that completes the connection, the flight linesdisappear. If the path does not complete the connection, the flight lines remain.

➤ To see flight lines in the layout window, from the layout window, choose Connectivity –Show Incomplete Nets.

Checking Connectivity with Markers

Markers are flashing boxes in the layout window that indicate electrical shorts or invalidoverlaps. When the Show Incomplete Nets command is active (flight lines aredisplayed), the markers might be more difficult to see.

Finding Markers

To find markers, follow these steps.

1. From the layout window menu, choose Verify – Markers – Find.

Press the Return key toclose the polygon.

✘1st click

✘

Each click drawsanother segment.

✘✘

2nd click4th click

✘

Click left to entereach point.

3rd click

The finished polygonappears.

Press Return



The Find Marker form appears.

2. Turn on Zoom To Markers.

3. Click Apply.

Virtuoso XL zooms in on the error and warning markers one by one.

Explaining Markers

To find out what each marker means, follow these steps.

1. From the layout window, choose Verify – Markers – Explain.

The layout window prompts you to point at a marker.



2. Click on the marker to explain.

A dialog box appears identifying the location and explaining the short.

3. Click on another marker to explain, or press Escape to exit the command.

Deleting Single Markers

To delete (turn off) a single marker, follow these steps.

1. From the layout window, choose Verify – Markers – Delete.

The layout window prompts you to point at a marker.

2. Click on the marker to delete.

The marker disappears.

3. Click on another marker to delete or press Escape to exit the command.

Deleting All Markers

To delete all the markers, follow these steps.

1. From the layout window, choose Verify – Markers – Delete All.

location: ("overview" "feedbackAmp" "layout")reason: Warning: Overlap between path on layer ‘metal1 drawing’ on net ’vcc!’ and instance ‘|R17’ creates a short.



The Delete All Markers form appears. It lets you choose the type of markers to deleteand the levels of hierarchy from which you want to delete them.

2. Indicate your choices on the form.

3. Click OK.

All the markers disappear.

Defining Physical Vias

If you need vias that have special shapes not supported by symbolic vias or if you need morethan five layers in a via, you can build physical vias using the layout editor.

To define a physical via, follow these steps.

1. From the CIW, choose File – New – Cellview.



The Create New File form appears.

2. In the Library Name cyclic field, choose the library you want.

3. In the Cell Name field, type the cell name you want.

4. In the View Name field, type layout .

5. In the Tool cyclic field, choose Virtuoso or another layout editor.

6. Click OK.

A new layout window appears.

7. Create one via shape.

8. Define one pin on each of the two layers you want to connect.



The two pin names (one on each layer) must be identical and the pins must be createdas rectangles.

9. Select the via in the layout window.

10. Choose Design – Properties.


11. Click Property at the top of the form.

Caution

Do not use these vias as mosaics. The extractor connectivity extractordoes not see them.

Shape defined as pin with name “A” on layer 1

Shape defined as pin with name “A” on layer 2

Via shape



12. The form changes to show properties and include the Add button.

13. Click Add.



14. The Add Property form appears.

15. Use the Add Property form to define the following properties:

❑ The lvsIgnore property as a Boolean with a value of true

❑ The function property as a string with a value of via

16. To add each property, click Apply.



17. The values appear in the Edit Cellview Property form.

18. Click OK.

19. Choose Design – Save.

Using the Virtuoso Compactor on a Routed Design

If you want to compact a routed design with the Virtuoso compactor, remember that if you runthe compactor using the layout window Tools – Compact command, the compactorrecognizes symbolic connections only and it cannot compact all of the physical connectionsrecognized by Virtuoso XL.

If you want the compactor to recognize physical connections, as well as symbolicconnections, you must run the compactor when Virtuoso XL is running and use the layoutwindow Compact – Compact command. You might have to stretch the layout window



horizontally from its Virtuoso XL default size to be able to see the Compact menu on the farright.

To maintain connectivity after compaction if you run the compactor from the Tools menu, youmust use connections made with the Create Path command, use paths with centerlines, andmake sure the centerlines touch the centerlines of other paths to which you want to makeconnections or the connection regions of pins on electrically equivalent layers

The best way to maintain logical connectivity while compacting a Virtuoso XL design is to setthe syPresvOrigNet property on the design to Preserve Net before compacting.

For more information about the syPresvOrigNet property, see “Logical Connectivity” in theVirtuoso Compactor Reference Manual.

Virtuoso XL wire connectionsrecognized by the compactor(symbolic connections)

Virtuoso XL wire connectionsnot recognized by the compactor(physical connections)

Polygons cannotbe used as wires.

Centerlines donot meet.



12Creating Multipart Paths in Virtuoso XL

This chapter shows you how to use the Virtuoso® layout accelerator (Virtuoso XL) to createmultipart paths (MPP) and save an MPP as a template to use again. This chapter discussesthe following topics:

About Creating Multipart Paths on page 346

Flow for Creating Multipart Paths on page 349

Defining the Master Path on page 350

Defining Connectivity for the Master Path on page 354

Adding a New Subpart on page 357

Defining Connectivity for a Subpart on page 370

Editing a Subpart on page 372

Deleting a Subpart on page 374

Creating a Multipart Path in a Cellview on page 377

Saving Multipart Path Values as a Template on page 378

Example: Creating a Guard Ring on page 380

Example of an MPP Template on page 390

Setting the mppTemplate Environment Variable on page 392

Create Multipart Path Forms on page 394


Virtuoso Layout Accelerator User GuideCreating Multipart Paths in Virtuoso XL

About Creating Multipart Paths

You can use the Create Multipart Path command to create paths that are relative objectdesign (ROD) objects. You can create simple one-part paths or complex paths containingseveral parts, such as a guard ring, transistor, bus, or shielded path. A ROD path that consistsof more than one part is called a multipart path.

A multipart path (MPP) consists of a single master path and one or more subparts. Themaster path is the defining object; all subparts are based upon and exist in relation to themaster path. You can define any number of subparts for a multipart path. Subparts can beany or all of the following: offset subpaths, enclosure subpaths, and sets of subrectangles.Also, you can define connectivity for any or all parts of a multipart path.

A ROD multipart path has many advantages over a regular path: you can access it by name,even through levels of hierarchy; you can chop it; and you can establish persistent spatialrelationships between a ROD path and other objects or points (align the ROD path to otherobjects or to a point).

For a complete description of ROD objects and multipart paths, see the Virtuoso RelativeObject Design User Guide.

Note: In the Virtuoso® layout editor, a multipart path (master path and all its subparts) istreated as a single object.

With the Create Multipart Path command, you can do the following:

■ Create a new MPP in the current layout window by

❑ Using the system defaults for the Create Multipart Path form

❑ Modifying the system defaults in the Create Multipart Path form

❑ Choosing an existing template for a specific MPP and using its defaults

❑ Choosing an existing template for a specific MPP and modifying its values

■ Save the values in the Create Multipart Path form as a template to use again later

A template is a set of values that specify a particular object, such as a guard ring. Youcan define as many MPP templates as you wish. The system stores MPP templates aspart of your binary technology library.



About Creating a Multipart Path in a Layout Window

In a layout window, you create the master path for an MPP just as you create a regular path:by clicking to enter a series of points. You define the characteristics of the master path andall of its subparts with the values in the Create Multipart Path form and the ROD Subpartforms. As you draw an MPP in a cellview, you can make changes to the forms and see theresults of your changes immediately, until you double-click to complete the MPP.

Note: You can make as many changes as you want to an MPP using the Create MultipartPath form and the ROD Subpart form prior to entering the last point of your MPP in the layoutwindow. Once you enter the last point, you cannot use these forms to change the MPP. Youcan change a completed MPP using the Edit MPP Path Properties form.

Whenever you are creating a new type of MPP, you might want to save your form values as atemplate so that you can create other MPPs that are the same or similar.

When you first start the Virtuoso XL software, the Template Name field in the Create MultipartPath form is set to New and the values of the other fields are system defaults. For some fields,the system looks at your technology file for the design rule for the layer and, if it is defined,uses it as the default. For example, the system looks for the minWidth rule for the specifiedlayer to use as the default for the Width field. The only required field for a master path is theROD Name field; the only required field for subparts is the Layer field.

You can create an MPP in a layout window using the default values without even opening theform, or you can open the form and change the values. Or you can tell the system to use thevalues from an MPP template that you saved earlier. When you choose an MPP templatefrom the MPP Template cyclic field, the system fills in the rest of the fields in the CreateMultipart Path form and ROD Subpart form with the values specified in the template. For fieldswhose values are not specified in the template, the system assigns the system default values.You can use the template values as they are or modify them as desired.

Note: If you want to define connectivity for any part of an MPP in a cellview, you must openthe form, and in the Connectivity section, type in a net name.

If you want to designate a particular MPP template as your default rather than use the systemdefault values, you can do so by setting the mppTemplate layout editor environment variable.For information about how to set this environment variable, see “Setting the mppTemplateEnvironment Variable” on page 392.

About Saving a Multipart Path as a Template

When you use the Save Template button on the Create Multipart Path form to save the currentform values as a template, the system stores the form values as statements in thelxMPPTemplates subclass within the lxRules class in the temporary version of your



technology library in virtual memory. If you want changes to your technology file to persistbeyond the end of the current editing session, you must save your technology file changes todisk before you end your editing session, thereby updating the binary version of yourtechnology library.

This chapter describes how to define, change, and save MPP templates using the CreateMultipart Path form. Alternatively, you can specify values for an MPP by dumping yourtechnology file to ASCII and editing the lxMPPTemplates subclass section. If you want todefine or change a template by editing the lxRules in your technology file, see“lxMPPTemplates” in the Technology File and Display Resource File SKILL ReferenceManual.



Flow for Creating Multipart Paths

The tasks involved in creating an MPP are shown in a suggested flow below. To see the stepsfor a task, click on the task name.

Optionally, you can save your MPP formvalues as a template.

Defining the Master Path

Adding a New Subpart

Editing a Subpart

Deleting a Subpart

Defining Connectivity forthe Master Path

Defining Connectivity for aSubpart

Saving Multipart PathValues as a Template

You must define the master path. Optionally,you can specify connectivity for it.

Note: You must click OK or Apply inthe ROD Subpart form to completeadding, editing, or deleting a subpart.

Optionally, you can specify any number ofsubparts. You can specify connectivity for anyor all subparts.

Creating a Multipart Path ina Cellview



Defining the Master Path

1. To open the Create Multipart Path form, in the layout window, choose Create –Multipart Path and press F3.

The Create Multipart Path form appears, with most fields filled with system defaultvalues. The values of fields that can default to technology rules might vary depending onwhich layer is current in the Layer Selection Window (LSW). If there is no rule defined inthe technology file, the system uses a system default.

You can use a template to create your MPP or create a new one from scratch.

Note: Templates do not contain net names because each MPP you create from the sametemplate could be on a different net. When you choose a template that contains connectivity,the system displays a message at the bottom of the cellview window prompting you to entera valid net name. You must enter a name in the Net Name field for each part (master pathand/or subparts) that has connectivity. If you click in the cellview window before entering therequired net name(s), the system beeps.

2. For MPP Template, choose the type of MPP you want to create in a layout window ordefine as a template by doing one of the following:

❑ To create a or define an MPP that is not similar to an MPP template in yourtechnology file, choose New.

When you choose New, you need to set the layer and purpose in the LSW to thevalue you want for the master path. If the layer you want is not a valid layer, see



“Changing the Available Entry Layers” in the Virtuoso Layout Editor User Guidefor information about how to add a layer to the LSW.

❑ To create an MPP in the current layout window that is the same as an MPP templatethat is already defined, choose the name of an MPP template.

When you choose an MPP template name, the system changes the current layerand purpose in the LSW to the layer and purpose defined in the MPP template forthe master path. If you want a different layer, change the layer in the LSW.

If the layer specified in the template is not a valid layer, the system displays a dialogbox asking if you want the system to add the master path layer to the LSW. If you donot, the system uses the current LSW layer.

❑ To create or define an MPP similar to an existing MPP template, choose the nameof the MPP template.

Now you can modify the values in the Create Multipart Path form to make themdifferent than the MPP template values.

3. Check the LSW for the current layer and purpose for the master path, and modify it ifdesired.

The ROD Name field specifies a unique name for the ROD object information about theMPP in the layout window. You can access information about the MPP through multiplelevels of hierarchy using this name. The default ROD object name consists of the prefixpath followed by a number.

4. For ROD Name, accept the default system-assigned name or type in a name that isunique in the current cellview.

5. For Choppable, do one of the following:

❑ To make the master path and all subparts choppable, turn on Choppable.

❑ To make the master path not choppable (subparts can be choppable or not), turn offChoppable.

The system ignores the Choppable field when the path has no subparts.

6. For Width, do one of the following:

❑ Type in a positive integer or floating-point number.

❑ To use the minWidth rule for the master path layer from the technology file, do notchange the Width field.

If the minWidth rule for the master path layer is not defined in the technology file,you must type a number or the system displays a warning.



7. For End Type, choose a value. If you want to specify a beginning or ending extension,you must choose variable.

The Offset and Justification fields are interdependent. Justification determines thepart of the master path (master path centerline, left edge, or right edge) that is offset fromthe points you enter (the point list), relative to the direction of the master path. Thedirection of the master path is determined by the sequence in which you enter its points.

8. For Justification, choose one of the following values:

❑ When Offset is 0:

center to make the master path centerline coincident with the point list

left to make the right edge of the master path coincident with the point list

right to make the left edge of the master path coincident with the point list

❑ When Offset is not 0:

center to offset the centerline of the master path from the point list

left to offset the left edge of the master path from the point list

right to offset the right edge of the master path from the point list

9. For Offset, do one of the following:

❑ To make the centerline of the master path coincident with the points you enter, leaveOffset set to 0 and Justification set to center.

❑ To offset the master path from the point list, type a signed integer or floating-pointnumber.

The part of the master path that is offset from the point list is determined by the valueof the Justification field. Whether you enter a positive or negative number dependson where you want the master path in relation to the point list. See Table 1 onpage 352.

For illustrations showing the location of a master path in relation to the point list, see“Examples of Offsetting the Master Path” in the Virtuoso Relative Object DesignUser Guide.

Table 1 Position of Master Path in Relation to Point List

Direction of Point List Segment Positive Offset Negative Offset

Positive along X axis Above Below



10. For Begin Extension, do one of the following:

❑ If you want the master path layer to begin at the first point you enter for the masterpath, leave Begin Extension set to 0.

To specify an extension, the End Type field must be set to variable.

❑ If you want the master path layer to extend beyond the first point you enter for themaster path, type a positive integer or floating-point number.

11. For End Extension, do one of the following:

❑ If you want the master path layer to end at the last point you enter for the masterpath, leave End Extension set to 0.

To specify an extension, the End Type field must be set to variable.

❑ If you want the master path layer to extend beyond the last point you enter for themaster path, type a positive integer or floating-point number.

12. For Connectivity, do one of the following:

❑ If you do not want to define connectivity, leave Connectivity set to None and returnto “Flow for Creating Multipart Paths” on page 349 to continue with the next step inthe flow.

❑ If you want to associate the master path with a net or specify it as a pin, continue tothe next section, “Defining Connectivity for the Master Path” on page 354.

Negative along X axis Below Above

Positive along Y axisLeft Right

Negative along Y axisRight Left

Table 1 Position of Master Path in Relation to Point List

Direction of Point List Segment Positive Offset Negative Offset



Defining Connectivity for the Master Path

You can associate the master path with a net, and you can designate the master path as apin. Changes you make to the Create Multipart Path form immediately affect the master pathin the layout window.

To define connectivity for a master path, do one of the following:

1. To assign the master path to a net, do the following:

❑ For Connectivity, choose Net.

The form expands to show the net connectivity field.

❑ For Net Name, type the name of the net.

You must enter a net name or the system beeps when you click in the cellviewwindow to begin creating the MPP.

You have completed assigning the master path to a net. Return to “Flow for CreatingMultipart Paths” on page 349 to continue with the next step in the flow.

2. To assign the master path to a pin, do the following:

❑ For Connectivity, choose Pin.



The form expands to show the net and pin connectivity fields.


You must enter a net name or the system beeps when you click in the cellviewwindow to begin creating the MPP.

❑ For I/O Type, choose one of the following: input, output, inputOutput, switch, orjumper.

❑ For Access Direction, choose the part(s) of the pin to which routing can beconnected.

❑ Turn on Display Pin Name if you want to create a text-display object to display thenet name for the pin.

Note: If pin names are not visible in the cellview, the Pin Names option in theDisplay Options form is not turned on. To display all pin names, turn on PinNames in the Display Options form.

The system uses the values of four fields to calculate the position of the text-displayobject: Reference Handle, Offset X, Offset Y, and the Justification field on the PinName Display form.

❑ Turn on Display Pin Name Option if you want to set pin name display options, suchas font, height, layer, and justification on the Pin Name Display form. For adescription of the Pin Name Display form, see “Opening the Pin Name DisplayForm” in the Virtuoso Layout Editor User Guide.

❑ For Reference Handle, choose where you want to align the pin name in relation tothe master path or subpart.



You can offset the pin name from the object in the direction of the X and/or Y axis.

❑ For Offset X, type a positive or negative floating-point number to offset the originpoint of the pin name along the X axis from the point specified by Reference Handle.

❑ For Offset Y, type a positive or negative floating-point number to offset the originpoint of the pin name along the Y axis from the point specified by Reference Handle.

You have completed defining connectivity. Return to “Flow for Creating Multipart Paths” onpage 349 to continue with the next step in the flow.



Adding a New Subpart

You can add any number of subparts for the current master path in the layout window. If youwant to use the subpart values again, you need to save them as a template.

1. To specify a new subpart for the current master path, in the Create Multipart Path form,click on the Subpart button.

The ROD Subpart form appears.

2. Click to choose the type of subpart you want to create: Offset Subpath, EnclosureSubpath, or Subrectangle.

The system displays the subpart fields at the bottom of the form. If any subparts of thetype you selected already exist, the system displays one line of information for eachsubpart in the scroll window at the top of the form.

For a description of the information in the scroll window, see one of the following:

Offset Subpath Fields on page 400

Enclosure Subpath Fields on page 402

Subrectangle Fields on page 403

3. To define a new subpart, go to one of the following topics:

Defining an Offset Subpath on page 358

Defining an Enclosure Subpath on page 361

Defining One or More Sets of Subrectangles on page 364



Defining an Offset Subpath

You can define a subpath coincident with an edge of the master path, on the left or right sideof the master path, or overlapping the master path. This is called an offset subpath.

You can specify the width of the offset subpath or let it default to the minWidth rule for thesubpath layer from the technology file. The location of an offset subpath in relation to themaster path depends on the values of the Separation and Justification fields, in relation tothe direction of the master path.

For a detailed description of offset subpaths, see Offset Subpaths” in the Virtuoso RelativeObject Design User Guide.

The offset subpath fields on the ROD Subpart form looks like this:

Set values for the offset subpath section as follows:

1. For Layer, choose the layer for the offset subpath.

2. Turn on Choppable if the master path is set to choppable; otherwise set the offsetsubpath to choppable or not choppable, as you wish.

3. For Begin Offset, type a signed integer or floating-point number to specify the startingedge of the subpath in relation to the starting edge of the master path. A positive numberextends the end of the subpath beyond the end of the master path; a negative numberretracts the end of the subpath from the end of the master path.

4. For End Offset, type a signed integer or floating-point number to specify the endingedge of the subpath in relation to the ending edge of the master path. A positive numberextends the end of the subpath beyond the end of the master path; a negative numberretracts the end of the subpath from the end of the master path.





❑ To use the minWidth rule for the subpath layer from the technology file, do notchange the Width field.

If you do not specify a value and minWidth for the subpath layer is not defined in yourtechnology file, the system uses the width of the master path as a default.

6. For Separation and Justification, type a signed integer or floating-point number forSeparation and choose a setting for Justification, as shown in Table 2 on page 360.

Whether you enter a positive or negative number depends on where you want to definethe subpath in relation to the master path.

For illustrations showing the location of offset subpaths in relation to the master path, see“Examples of Offset Subpaths” in the Virtuoso Relative Object Design User Guide.




❑ If you do not want to define connectivity, leave Connectivity set to None.

❑ If you want to associate the subpart with a net or specify it as a pin, go to “DefiningConnectivity for a Subpart” on page 370.

8. To add the new offset subpath to the window at the top of the ROD Subpart from, clickAdd.

Table 2 Position of Offset Subpath in Relation to Master Path

Separation CenterJustification Left Justification Right Justification

Zero Subpath centerlineon master pathcenterline

Left edge of masterpath coincident withright edge ofsubpath

Right edge ofmaster pathcoincident with leftedge of subpath

Positive number Subpath centerlineon left side ofmaster pathcenterline

Left edge of masterpath on right side ofright edge ofsubpath

Right edge ofmaster path on leftside of left edge ofsubpath

Negative number Subpath centerlineon right side ofmaster pathcenterline

Left edge of masterpath on left side ofright edge ofsubpath

Right edge ofmaster path on rightside of left edge ofsubpath

To add the new offset subpath tothe list, click Add.



The system displays a line of data for the new offset subpath in the scroll window. For adescription of the data, see Table 4 on page 400.

You must click OK or Apply at the top of the ROD Subpart form to make the new offsetsubpath part of the MPP.

9. To save the new offset subpath as part of the MPP, in the ROD Subpart form, click OK orApply.

So far, you are defining a new offset subpath only for the MPP in the current layoutwindow. If you want to add the new offset subpath to an MPP template, you need to saveyour changes to the template.

10. To save your field values as an MPP template, go to “Saving Multipart Path Values as aTemplate” on page 378.

You have completed adding an offset subpath to your MPP. Continue to the next section orreturn to “Flow for Creating Multipart Paths” on page 349 to continue with the next step in theflow.

Defining an Enclosure Subpath

You can define a subpath with its centerline on the centerline of the master path and its widthcalculated using the width of the master path plus a positive or negative enclosure value. Thisis called an enclosure subpath. The enclosure determines by how much the subpath isenclosed by the master path or by how much the master path is enclosed by the subpath.

For a detailed description of enclosure subpaths, see Enclosure Subpaths” in the VirtuosoRelative Object Design User Guide.



The enclosure subpath fields on the ROD Subpart form looks like this:

Set values for the enclosure subpath section as follows:

1. For Layer, choose the layer for the enclosure subpath.

2. Turn on Choppable if the master path is set to choppable; otherwise, set the enclosuresubpath to choppable or not choppable, as you wish.

3. For Begin Offset, type a signed integer or floating-point number to start the edge of thesubpath before or after the starting edge of the master path.

4. For End Offset, type a signed integer or floating-point number to end the edge of thesubpath before or after the ending edge of the master path.

To calculate the width of an enclosure subpath, the system subtracts two times theenclosure value from the width of the master path:

Width of Enclosure Subpath =Width of Master Path - (2 * Enclosure Value)

5. For Enclosure, type an integer or floating-point number for the enclosure of the subpathin relation to the master path.



❑ To define a subpath that is narrower than the master path, type a positive number.

❑ To define a subpath that wider than the master path, type a negative number.

❑ To use the minEnclosure rule for the subpath layer from the technology file, keepthe default.

If minEnclosure for the subpath layer is not defined in your technology file, andyou do not type a value, the system sets the value to zero.

For illustrations showing the location of enclosure subpaths in relation to the master path,see “Examples of Enclosure Subpaths” in the Virtuoso Relative Object Design UserGuide.




7. To add the new enclosure subpath to the scroll window at the top of the ROD Subpartform, click Add.

The system displays a line of data for the new enclosure subpath in the scroll window.For a description of the data, see Table 6 on page 402.

You must click OK or Apply at the top of the ROD Subpart form to make the newenclosure subpath part of the MPP.

8. To save the new enclosure subpath as part of the MPP in the cellview, click OK or Apply.

To add the new enclosure subpath tothe list, click Add.



So far, you are defining a new enclosure subpath only for the MPP in the current layoutwindow. If you want to add the new subpath to an MPP template, you need to save yourchanges to the template.

9. To save your addition to an MPP template, go to “Saving Multipart Path Values as aTemplate” on page 378.

You have completed adding an enclosure subpath to your MPP. Continue to the next sectionor return to “Flow for Creating Multipart Paths” on page 349 to continue with the next step inthe flow.

Defining One or More Sets of Subrectangles

You can define one or more sets of subrectangles in relation to the centerline of any masterpath. A set can contain one or more subrectangles.

You can specify the width and length of the subrectangles or let them default to the minWidthrule for the subrectangle layer from the technology file. You can offset the centerline of thesubrectangles from the master path centerline, and you can offset the edge of the first andlast subrectangles from the ends of the master path.

You can define connectivity for a set of subrectangles. When you specify that a set ofsubrectangles is a pin, each rectangle in the set becomes a pin. In the layout editor, the wholemultipart path (master path and all subparts) is treated as a single object.

The location of a set of subrectangles in relation to the master path depends on the values ofthe Separation and Justification fields, in relation to the direction of the master path.

For a detailed description of subrectangles, see Sets of Subrectangles” in the VirtuosoRelative Object Design User Guide.



The subrectangle fields on the ROD Subpart form looks like this:

Fill in the subrectangle section as follows:

1. For Layer, choose the layer for the set of subrectangles.

2. Turn on Choppable if the master path is set to choppable; otherwise, set thesubrectangles to choppable or not choppable, as you wish.

3. For Begin Offset, type a signed integer or floating-point number to start the firstsubrectangle before or after the starting edge of the master path.

4. For End Offset, type a signed integer or floating-point number to end the lastsubrectangle before or after the ending edge of the master path.

For an MPP, the width of a subrectangle is parallel to the width of the master path.

Width ofmaster path

Width ofsubrectangles



The length of a subrectangle is parallel to the master path centerline.



❑ To use the minWidth rule for the subrectangle layer from the technology file, keepthe default.

If you do not specify a value and minWidth for the subrectangle layer is not defined inyour technology file, the system uses the width of the master path as a default.

6. For Length, do one of the following:


❑ To let the length default to the minWidth rule for the subrectangle layer from thetechnology file, do not change the Length field.

If you do not specify a value, Width is not specified, and the minWidth rule is not definedin the technology file, the system uses the width of the master path as a default.

For each segment, you control the space between rectangles and after the last rectanglewith the two fields Gap and Space. Space determines the minimum distance betweenrectangles. Gap controls where the system places any space that remains after therectangles are placed the minimum distance apart.

When the value of Gap is distribute, the system places subrectangles using the valueof the Space option until there is no space for another subrectangle, then distributes therest of the space as evenly as possible between the subrectangles in multiples of the gridspace specified by the mfgGridResolution rule in the technology file. Any remainingspace is placed after the last subrectangle in the segment.

Length ofsubrectangles



When the value of Gap is minimum, the system places subrectangles using the valueof the Space option until there is no space for another rectangle, then leaves any excessspace after the last subrectangle in the segment.

7. For Gap, choose distribute or minimum.

8. For Space, do one of the following:

❑ Type a positive integer or floating-point number for the distance between the edgesof adjoining rectangles.

❑ To use the minSpacing rule for the subrectangle layer from the technology file,keep the default.

If you do not specify a value and minSpacing for the subpath layer is not defined in yourtechnology file, the system sets the value to zero.

9. For Separation and Justification, type a signed integer or floating-point number forSeparation and choose a setting for Justification, as shown in Table 3 on page 367.

Whether you enter a positive or negative number depends on where you want to definethe set of subrectangles in relation to the master path.

For illustrations showing the location of sets of subrectangles in relation to the masterpath, see “Examples of Sets of Subrectangles” in the Virtuoso Relative Object DesignUser Guide.

Table 3 Position of Subrectangles in Relation to Master Path

Separation CenterJustification Left Justification Right Justification

Zero Center of width ofsubrectangles onmaster pathcenterline

Left edge of masterpath coincident withright edge ofsubrectangles

Right edge of masterpath coincident withleft edge ofsubrectangles

Positive number Center of width ofsubrectangles onleft side of masterpath centerline

Left edge of masterpath on right side ofright edge ofsubrectangles

Right edge of masterpath on left side of leftedge of subrectangles

Negative number Center of width ofsubrectangles onright side of masterpath centerline

Left edge of masterpath on left side ofright edge ofsubrectangles

Right edge of masterpath on right side ofleft edge ofsubrectangles



When you specify that a set of subrectangles is a pin, each rectangle in the set becomesa pin. In the layout editor, the whole multipart path (master path plus all subparts) istreated as a single object.




11. To add the new subrectangle(s) to the scroll window at the top of the ROD Subpart form,click Add.

The system displays a line of data for the new set of subrectangles in the scroll window.For a description of the data, see Table 7 on page 404.

You must click OK or Apply at the top of the ROD Subpart form to make the new set ofsubrectangles part of the MPP.

12. To save the new set of subrectangles as part of the MPP in the cellview, click OK or Apply.

So far, you are defining a set of subrectangles only for the MPP in the current layoutwindow. If you want to add the new set of subrectangles to an MPP template, you needto save your changes to a template.

13. To save your addition in an MPP template, go to “Saving Multipart Path Values as aTemplate” on page 378.

To add the new subrectangle(s) tothe list, click Add.



You have completed adding a set of subrectangles to your MPP. Continue to the next sectionor return to “Flow for Creating Multipart Paths” on page 349 to continue with the next step inthe flow.



Defining Connectivity for a Subpart

You can define connectivity for any MPP subpart by associating it with a net. You can alsodesignate a subpart as a pin. The changes you make do not affect the MPP in the layoutwindow until you click OK or Apply in the ROD Subpart form.

Note: You must type the name of the net in the ROD Subpart form for each subpart that hasconnectivity. If you do not type a name, the subpart is not associated with a net, and thesystem beeps when you click to start creating the MPP in a cellview window.

To define connectivity for a subpart, do one of the following:

1. To assign the subpart to a net, do the following:

❑ For Connectivity, choose Net.

The form expands to show the net connectivity fields.


You must enter a net name for every subpart that has connectivity or the systembeeps when you click in the cellview window to begin creating the MPP.

❑ To apply the net assignment to the subpart of the MPP in the layout window, clickOK or Apply.

You have completed assigning the subpart to a net. Return to “Flow for Creating MultipartPaths” on page 349 to continue with the next step in the flow.

2. To assign the subpart to a pin, do the following:

❑ For Connectivity, choose Pin.



The form expands to show both the net and pin connectivity fields. The pinconnectivity section looks like this:


You must enter a net name for every subpart that has connectivity or the systembeeps when you click in the cellview window to begin creating the MPP.

❑ For I/O Type, choose one of the following: input, output, inputOutput, switch, orjumper.

❑ For Access Direction, choose the part(s) of the pin to which routing can beconnected.

❑ Turn on Display Pin Name if you want to create a text-display object to display thenet name for the pin.

Note: If pin names are not visible in the cellview, the Pin Names option in theDisplay Options form is not turned on. To display all pin names, turn on PinNames in the Display Options form.

The system uses the values of four fields to calculate the position of the text-displayobject: Reference Handle, Offset X, Offset Y, and the Justification field on the PinName Display form.

❑ Turn on Display Pin Name Option if you want to set pin name display options, suchas font, height, layer, and justification on the Pin Name Display form.

For a description of the Pin Name Display form, see “Opening the Pin Name DisplayForm” in the Virtuoso Layout Editor User Guide.



❑ For Reference Handle, choose where you want to align the pin name in relation tothe master path or subpart.

You can offset the pin name from the object in the direction of the X and/or Y axis.

❑ For Offset X, type a positive or negative floating-point number to offset the originpoint of the pin name along the X axis from the point specified by Reference Handle.

❑ For Offset Y, type a positive or negative floating-point number to offset the originpoint of the pin name along the Y axis from the point specified by Reference Handle.

To make all the current values in the ROD Subpart form, including the connectivityvalues, part of the MPP in the layout window, you must click OK or Apply.

❑ To save the subpart values as part of the MPP in the layout window, in the RODSubpart form, click OK or Apply.

The system changes the MPP in the layout window to include the subpart connectivity.

You have completed defining connectivity for the subpart. Return to the topics listed for “Flowfor Creating Multipart Paths” on page 349 to select another topic.

Editing a Subpart

The subparts of an MPP are listed at the top of the ROD Subpart form. You can change anexisting subpart by changing the values for the selected subpart in the ROD Subpart form.

Remember, you must make all edits to subparts before entering the last point of yourMPP in the layout window. You cannot change an MPP after clicking on its last point;instead, you must delete the whole MPP and recreate it. It is safest to save your form valuesas a template before drawing an MPP in your cellview. Then, if you need to edit a subpart,you can recreate the MPP from the template and use the ROD Subpart form to edit thesubpart.

To edit a subpart, follow these steps.

1. In the Create Multipart Path form, click on the Subpart button.




Existing subparts are listed in the scroll window at the top of the form. For a descriptionof the data shown in the window, see one of the following:

Offset Subpath Data in ROD Subpart Form Scroll Area on page 400

Subpart Connectivity Data in ROD Subpart Form Scroll Area on page 400

Enclosure Subpath Data in ROD Subpart Form Scroll Area on page 402

Subrectangle Data in ROD Subpart Form Scroll Area on page 404

2. Highlight the subpart you want to edit.

The system fills in the fields of the ROD Subpart form with the values of the subpart youselected.

3. Change the values in the ROD Subpart form as desired.



4. To make your changes affect the data listed for the subpart at the top of the ROD Subpartform, click Edit.

The system changes the highlighted subpart data to match the new form values.

5. To make your subpart changes affect the MPP in the cellview, in the ROD Subpart form,click OK or Apply.

So far, your changes affect only the MPP in the current layout window. If you want yourchanges to affect an MPP template, you need to save your changes to the template.

6. To save your changes to an MPP template, go to “Saving Multipart Path Values as aTemplate” on page 378.

You have completed editing a subpart. Return to the list of topics for the “Flow for CreatingMultipart Paths” on page 349 to select another topic.

Deleting a Subpart

You can delete any subpart of an MPP. Subparts are listed at the top of the ROD Subpartform.

Remember, you must make all deletions to subparts before entering the last pointof your MPP in the layout window. You cannot change an MPP after clicking on its lastpoint; instead, you must delete the whole MPP and recreate it. It is safest to save your formvalues as a template before drawing an MPP in your cellview. Then, if you need to delete asubpart, you can recreate the MPP from the template and use the ROD Subpart form todelete the subpart.

To replace the values for the highlightedsubpart, click Edit.



To delete a subpart, follow these steps.

1. In the Create Multipart Path form, click on the Subpart button.


Existing subparts are listed in the scroll window at the top of the form. For a descriptionof the data shown in the window, see one of the following:

Offset Subpath Data in ROD Subpart Form Scroll Area table on page 400

Subpart Connectivity Data in ROD Subpart Form Scroll Area table on page 400

Enclosure Subpath Data in ROD Subpart Form Scroll Area table on page 402

Subrectangle Data in ROD Subpart Form Scroll Area table on page 404

2. Highlight the subpart you want to delete.



3. To delete the highlighted subpart from the data listed at the top of the ROD Subpart form,click Delete.

The highlighted subpart is deleted from the list of subparts in the ROD Subpart form.

4. To delete the subpart from the MPP in the cellview, in the ROD Subpart form, click OKor Apply.

The highlighted subpart is deleted from the MPP in the current cellview.

So far, your changes affect only the MPP in the current layout window. If you want toremove the deleted subpart from an MPP template, you need to save the current formvalues to the MPP template, overwriting the old values.

5. To remove the deleted subpart from an MPP template, go to “Saving Multipart PathValues as a Template” on page 378.

You have completed deleting a subpart. Return to the list of topics for the “Flow for CreatingMultipart Paths” on page 349 to select another topic.

To remove the highlighted subpart, clickDelete.



Creating a Multipart Path in a Cellview

After you specify values for the fields in the Create Multipart Path and ROD Subpart forms orchoose an MPP template, you are ready to create an MPP in your layout window.

MPP templates do not contain net names because each MPP you create from the sametemplate could be on a different net. When you choose an MPP template that containsconnectivity, the system displays a message at the bottom of the cellview window promptingyou to enter a valid net name.

Note: When there is connectivity, you must enter the name of the net in the Net Name fieldfor each part (master path and/or subparts) before you begin to create the MPP in the layoutwindow. If you click in the layout window before entering the net name(s), the system beeps.

As you draw an MPP, you can change the values in the Create Multipart Path and RODSubpart forms and see immediate changes to the MPP, until you double-click to enter the lastpoint. After you enter the last point to complete an MPP, you can no longer change that MPPusing the Create forms. You can, however, use the Edit MPP Path Properties form to changea completed MPP.

To draw an MPP in the layout window, follow these steps.

1. Click to enter the first point.

2. Move the cursor to the next point and click.

3. Continue to move the cursor and click to enter points.

4. To enter the last point of the path, either double-click or press Return .

You have completed drawing the MPP in your layout window. Return to the topics listed forthe “Creating Multipart Paths in Virtuoso XL” on page 345 to select another topic.



Saving Multipart Path Values as a Template

Whenever you create a new type of MPP that you might want to use again, you can save thevalues currently in the Create Multipart Path and ROD Subpart forms as a template in yourtechnology library.

Note: When you save MPP form values as a template, the system updates thelxMPPTemplates subclass in the temporary version of your technology library in virtualmemory. If you want your changes to persist beyond the end of the current editing session,you must save the changes to your binary technology library on disk before you exit thesoftware.

To save the current values in the Create Multipart Path form and ROD Subpart forms (if any)as an MPP template in your temporary binary technology library in virtual memory, followtheses steps.

1. In the Create Multipart Path form, click on the Save Template button.

The Save Template form appears.

2. For Template Name, type in a name for the MPP template you want to save. You cannotuse the name New; it is a reserved name.

3. Click OK.

If the name you entered matches the name of an existing MPP template, the systemdisplays a dialog box asking if you want to overwrite the existing MPP template.

4. If the system displays a dialog box, do one of the following:

❑ To replace the existing template with the current form settings, click OK in the dialogbox.

❑ If you do not want to replace the existing template, click Cancel in the dialog boxand change the MPP Template field in the Save Template form to a name that isunique.



Your template has been saved in the temporary version of the technology library in virtualmemory. To make the template part of your binary technology library on disk, you mustsave your technology library changes before you exit the editing session.

If you have not already saved the changes to your binary technology library, the systemdisplays a dialog box when you exit the software asking if you want to save the changes.You can save your template changes to disk then or you can save them to disk now.

5. To save the changes to your binary technology library to disk now, follow these steps.

❑ In the CIW, choose Technology File – Save.

❑ In the Save Technology File form, choose the name of the library you want to saveand click OK.

The system displays a dialog box asking you to confirm that you want to save thetechnology library to disk.

❑ In the Technology File Save form, click Yes.

You have completed saving the MPP values as a template in your binary technology libraryto disk. Return to the topics listed for the “Creating Multipart Paths in Virtuoso XL” onpage 345 to select another topic.



Example: Creating a Guard Ring

The following example shows how to create a guard ring using the Create Multipart Pathcommand. First, you specify values in the Create Multipart Path and ROD Subpart forms,then save your form values as a template, and finally, draw the guard ring in a layout window.The guard ring created in the example looks like this:

You will create the guard ring using the technology data provided in the Cadence® softwarehierarchy. Create the master path as diffusion on the diff layer, an enclosure subpath onthe metal1 layer, and contacts as a set of subrectangles on the cont layer.

1. Find the sample technology file mpu.tf in your installation directory:

❑ To find your installation directory, in the CIW, type instdir

Your system displays the installation directory; for example,

/usr/cadence/tools/dfII

❑ Change to the directory with sample mpu.tf by typing, for example:

cd /usr/cadence/tools/dfII/samples/techfile

2. Start the Virtuoso® layout editor and Virtuoso® layout accelerator software.

3. To access mpu.tf without changing your own technology file, follow these steps.

❑ In the CIW, choose Technology File – New.



❑ For Technology Library Name, type mpu and for Load ASCII Technology File, typempu.tf , then click OK.

4. Open a new cellview by choosing File – New – Cellview from the Command InterpreterWindow (CIW.)

When you choose the Create – Multipart Path command, the system fills the formfields with the default values for the current layer. Therefore, you need to make the layeryou want for the MPP the current layer before you choose the Multipart Path command.

5. In the LSW, set the current layer for the master path to diff .

The system fills the form with default values for the diffusion layer.

6. In the new cellview window, choose Create – Multipart Path and press F3.

Note: Do not enter points until after you finish setting form values for the master pathand subparts.

7. In the Create Multipart Path form, set the values as follows:

MPP Template New

ROD Name guardringA

Choppable off

Width 2.2

End Type flush

Offset 0

Begin Extension 0

End Extension 0

Justification center

Connectivity None



8. Create the metal1 layer as an enclosure subpath by doing the following:

❑ In the Create Multipart Path form, click Subpart.


❑ In the ROD Subpart form, click Enclosure Subpath.

❑ In the Enclosure Subpath fields, set the values as follows:

Layer metal1

Choppable on

Begin Offset -0.2

Enclosure 0.2

End Offset 0.2

Connectivity Pin

Net Name pin1

I/O Type inputOutput

Access Direction Any

Display Pin Name on



Remember, every time you define an MPP part for a cellview and want it to haveconnectivity, you must type a name in the Net Name field. This is also true whenyou use an MPP template. Net names are not saved as part of an MPP templatebecause each MPP in a cellview is usually on a different net.

Note: Optionally, you could click on the Display Pin Name Option button to set values forpin name display options, such as font, height, layer, and justification. This example usesthe defaults.

Reference Handle start0

Offset X 0

Offset Y 0



You must click Add to make the subpath part of the guard ring MPP.

❑ To add the enclosure subpath to the list of enclosure subpaths at the top of the RODSubpart form, click Add.

Now you can see data for the enclosure subpath in the scroll window at the top of theROD Subpart form. It looks like this:

For a description of the data shown in the window, see Table 6 on page 402.

Note: Although you added the new enclosure subpath to the ROD Subpart form, youmust apply your changes to the MPP you are creating by clicking on OK or Apply. Youcan do so now or after you add the contact subrectangles. Clicking on OK or Apply savesall changes you made to all subparts of the MPP.

❑ To save the enclosure subpath as part of the guard ring MPP now, in the RODSubpart form, click Apply.

The ROD Subpart form stays open so you can add more subparts.

9. To create the contacts as subrectangles, do the following:

❑ In the ROD Subpart form, click Subrectangle.



❑ In the Subrectangle fields on the ROD Subpart form, set the values as follows:

When you type -0.6 in the Begin Offset field, the system sets the Width, Length,and Space fields to their defaults, which are the minWidth and minSpacing rulesdefined in the technology file for the cont layer. Also, when you click in the EndOffset field, the system sets End Offset to the same value as Begin Offset, since thatis its default. Accept the default values for the remaining fields in the ROD Subpartform.

You must click the Add button to add the subpart to the list in the form.

❑ To add the subrectangles to the ROD Subpart form, click Add.

Layer cont

Choppable on

Begin Offset -0.6



Now you can see data for the contact subrectangles in the scroll window at the top of theROD Subpart form. It looks like this:

Note: Although you added the new set of subrectangles to the ROD Subpart form, youmust apply your changes to the MPP you are creating by clicking on OK or Apply. Clickingon OK or Apply saves all changes you made to all subparts of the MPP.

❑ To save the contact subrectangles and all other subparts you added, in the RODSubpart form, click OK.

The ROD Subpart form closes.

If you have finished specifying values in the Create Multipart Path and ROD Subpartforms for this MPP, it is a good idea to save the MPP form values as a template now,before drawing the MPP in a layout window. After you enter the last point to complete anMPP, you can no longer change that MPP using the Create forms. However, you can usethe Edit MPP Path Properties form to change a completed MPP.

10. To save all your MPP form values as a template, do the following:

❑ In the Create Multipart Path form, click Save Template.

The Save Template form appears.

❑ For the Template Name field in the Save Template form, type



guardring1

❑ In the Save Template form, click OK.

Caution

When you save an MPP template, the system updates the temporaryversion of your technology library in virtual memory. You still need tosave your changes to your binary technology library on disk before youexit the software, or you will lose your template changes.

When you exit the software, the system displays a dialog box asking if you want to savethe changes to your technology file. You can save your template changes when you exit,or to be safe, you can save them now.

11. To make the changes to the temporary version of your technology file permanent now,do the following:

❑ In the CIW, choose Technology File – Save.

❑ In the Save Technology File form, choose the name of the library you want to save,then click OK.

The system displays a dialog box asking you to confirm that you want to savechanges to the binary technology library on disk.

❑ In the Technology File Save form, click Yes.

You have completed saving the MPP values as a template in your binary technologylibrary. Now you are ready to draw a guard ring in your layout window.

12. To draw the guard ring,

❑ Choose Options – Display and set X and Y Snap Spacing to 0.1 .

❑ Click on the following points. To enter the last point, either double-click or pressReturn.

guardring1



0:0 20:0 20:10 1.1:10 1.1:1.1

If the system beeps, you might be creating a self-intersecting path. The system does notallow you to create a path whose master path centerline intersects itself.

If a guard ring did not appear, check the CIW for error messages. The completed guard ringlooks like this:



Troubleshooting

If you do not see a pin name displayed in the cellview, if might be due to one of the followingconditions:

■ The Pin Names display option might be turned off. To turn it on, in the cellview window,choose Options – Display, click Pin Names, and click OK.

■ You might have forgotten to type a name in the Net Name field for connectivity. In theConnectivity section of the Create Multipart Path form or ROD Subpart form, type in anet name, then click Edit and OK.



Example of an MPP Template

The following guard ring was created as a multipart path (MPP) from a template defined in asample technology library.

The guard ring was created by choosing the Create – Multipart Path command, choosingguardring for the MPP Template field, and clicking on the following four points in a layoutwindow:

0:0 0:5 10:5 10:0.9 0.9:0.9

Here is the corresponding code from the lxMPPTemplates subclass within the lxRulesclass of the ASCII version of the technology file:

;********************************; LX RULES;********************************lxRules(lxMPPTemplates( ;( name [masterPath] [offsetSubpaths] [encSubPaths] [subRects] ) ; ; masterPath: ; (layer [width] [choppable] [endType] [beginExt] [endExt]

; [justify] [offset] [connectivity]) ; ; offsetSubpaths: ; (layer [width] [choppable] [separation] [justification]

; [begOffset] [endOffset] [connectivity]) ; ; encSubPaths:

X

Y



; (layer [enclosure] [choppable] [separation] [begOffset]; [endOffset] [connectivity])

; ; subRects:

; (layer [width] [length] [choppable] [separation] [justification]; [space] [begOffset] [endOffset] [gap] [connectivity])

; ; connectivity: ; ([I/O type] [pin] [accDir] [dispPinName] [height] [ layer] ; [layer] [justification] [font] [textOptions] [orientation] ; [refHandle] [offset]) ; ;(guardring

; master path:(

("diff" "drawing") ; layer-purpose pair1.8 ; widthnil ; choppable

); offset subpath (there is none)

nil ; enclosure subpath

(("metal1" "drawing") ; layer-purpose pair0.2 ; enclosuret ; choppable-0.2 ; separation0.2 ; begin offset

); set of subrectangles

(("cont" "drawing" ; layer-purpose pairnil ; widthnil ; lengtht ; choppablenil ; separationnil ; justificationnil ; space-0.6

; begin offset)

) ; end guardring template ) ; lxMPPTemplates) ; lxRules



Setting the mppTemplate Environment Variable

You can control the default values for the fields in the Create Multipart Path form by settingthe layout editor environment variable mppTemplate .

The system default for mppTemplate is New. When you open the Create Multipart Path formwith mppTemplate set to New, the system sets the MPP Template field to New and theremaining fields to their system default values.

You can change mppTemplate to the name of an MPP template that you saved earlier; thenwhen you open the Create Multipart Path form, the system sets the MPP Template field to thename of the template and uses the template values as defaults for the remaining fields.

Note: When you change the value of the MPP Template field in the Create Multipart Pathform, the system automatically resets the values of all the fields in the form. For example, ifthe MPP Template field is set to New, which is the default, and you change it to the name ofan MPP template, the system resets all fields to the MPP template values. Conversely, if thevalue of the MPP Template field is set to the name of an MPP template and you change it toNew, the system resets all fields to the system defaults.

The following sections describe how to check the current value of mppTemplate and how toset it.

Checking the Value of mppTemplate

To determine the current value of the layout editor mppTemplate environment variable,follow these steps.

➤ In the CIW, type

envGetVal( "layout" "mppTemplate" )

Changing the Value of mppTemplate

You can change the setting of an environment variable in the CIW or in your local~/.cdsenv file. To set the mppTemplate variable, do one of the following:

➤ To change the mppTemplate environment variable temporarily, type the following in theCIW:

envSetVal("layout" "mppTemplate" 'string " your_value ")



where your_value is the new value for mppTemplate , enclosed in quotes. The singlequotation mark in front of string is necessary, so that the system treats the data typeas a symbol, not as a variable. For example:

envSetVal("layout" "mppTemplate" 'string "myMPPTemplate" )

➤ To change the value of the mppTemplate environment variable in your~/.cdsenv file, edit the file, search for mppTemplate , and change the value asdesired.

The default layout environment variable setting for mppTemplate in your ~/.cdsenvfile looks like this:

layout mppTemplate string New"

If you do not have a .cdsenv file in your home directory, you can copy the .cdsenv filefrom the samples directory in your local Cadence hierarchy to your home directory andedit it. Delete the environment variables you do not need.



Create Multipart Path Forms

Create Multipart Path – Master Path Section on page 394

Connectivity Section on page 397

ROD Subpart Form on page 398

Create Multipart Path – Master Path Section

The system uses the current layer in the Layer Selection Window (LSW) as the layer for themaster path. When you choose an MPP template from the MPP Template cyclic field, themaster path layer from the template becomes the current LSW layer. If you want a differentlayer for the master path, change the current layer in the LSW.

MPP Template lets you select a template for a multipart path (MPP) or choose to create anew MPP. The default is New, unless you change the default by setting the layout editorenvironment variable mppTemplate to the name of an MPP template.

New lets you create a new MPP in a layout window or define a new MPP template usingthe values you set in the ROD Create Multipart Path form.

ROD Name lets you assign a ROD object name for a new MPP in the current layout window.The name must be unique in the cellview. If you leave this field blank, the system assigns aunique name consisting of the prefix path , followed by a number. For example, for the firstROD path in the cellview for which you do not specify a name, the system assigns the namepath0 , if unique; for the second, path1 , and so on.

Choppable indicates whether or not the master path can be chopped. This field is valid onlyfor a path that has at least one subpart. When a master path is choppable, all its subpartsmust be choppable. When a master path is not choppable, each of its subparts can bechoppable or not. The system ignores this field for single-part paths. The default is choppable.

Width specifies the width of the master path. It must be a positive integer or floating-pointnumber. If you do not specify the width, the system uses the minWidth rule for the masterpath layer from the technology file. If the minWidth rule is not defined in the technology file,you must specify a width or the system displays an error.

End Type defines how the ends of the master path are created. The default value is flush. Ifyou want to specify a beginning or ending extension, you must choose variable. Subpartsinherit the end type of the master path.

flush creates ends that end at the first and last points of the path.



offset creates ends that extend beyond the first and last points of the path by one halfthe path width.

octagon creates octagonal-shaped ends that extend beyond the first and last points ofthe path by one half the path width.

variable creates path ends that extend beyond or retract from first and last points of thepath by the value you enter in the Begin Extension and End Extension fields.

Offset specifies the distance by which the master path is offset from the points you enter (thepoint list), in relation to the direction of the master path. The direction of the master path isdetermined by the order in which you enter the first and last point of each segment. The Offsetvalue must be a signed integer or floating-point number; the default is 0.

A positive value defines the master path to the left of the point list; a negative value definesthe master path to the right of the point list. For a detailed description about offsetting themaster path, see “About Offsetting the Master Path” in the Virtuoso Relative ObjectDesign User Guide.

Justification defines the part of the master path (the centerline, left edge, or right edge) thatis offset from the points you enter (the point list). Justification is relative to the direction ofthe master path. The direction of the master path is determined by the order in which youenter the first and last point of each segment. The default is center. Together, the Offset andJustification fields determine the location of the master path in relation to the point list.

center specifies that the centerline of the master path is offset from the point list by thevalue you enter for the Offset field.

left specifies that the left edge of the master path is offset from the point list by the valueyou enter for the Offset field.

right specifies that the right edge of the master path is offset from the point list by thevalue you enter for the Offset field.

Begin Extension specifies the distance by which the starting edge of the master pathextends beyond or retracts from its first point. The value must be a zero or a positive integeror floating-point number; the default is 0. This field is ignored unless End Type is variable.

End Extension specifies the distance by which the ending edge of the master path extendsbeyond or retracts from its last point. The value must be a zero or a positive integer or floating-point number; the default is 0. This field is ignored unless End Type is variable.

Connectivity determines whether to associate the master path with a net and whether tomake it into a pin. The default is None. When you choose Net, the Create Multipart Path formexpands to show the net connectivity fields. When you choose Pin, the form expands to showboth the net and pin connectivity fields.



None indicates that you do not want to define connectivity.

Net indicates that you want to associate the master path with a specific net. You musttype a value in the Net Name field.

Pin indicates that you want the master path to be a pin. To define a pin, you must alsospecify a value for the Net Name field.

Save Template opens the Save Template form to let you enter a name for the MPP templateyou are creating. If an MPP template already exists with the same name, the system displaysa dialog box asking if you want to overwrite it. Do not use the name New; it is a reservedname. When you click OK, the system saves the current settings from the Create MultipartPath form, including current values defined for subparts, if any, as a template.

Subpart opens the ROD Subpart form to let you define, change, or delete subparts for theassociated master path. For a description of the ROD Subpart form, see the “ROD SubpartForm” on page 398.



Connectivity Section

When the Connectivity field is set to Net, the following field is displayed:

Net Name specifies the net with which you want to associate the master path or subpart. Thisfield is required. If the net does not exist, the system creates it, using the name you type inthis field. MPP templates do not contain net names, so when you use a template that containsconnectivity, you must display the form and enter a name; if you do not, the system beepswhen you click in a cellview to begin creating the MPP.

When the Connectivity field is set to Pin, both the net and pin connectivity fields aredisplayed in the Connectivity section:

Net Name specifies the net with which you want to associate the master path or subpart. Thisfield is required. If the net does not exist, the system creates it, using the name you type inthis field. MPP templates do not contain net names, so when you use a template that containsconnectivity, you must display the form and enter a name; if you do not, the system beepswhen you click in a cellview to begin creating the MPP.

I/O Type assigns a property used by routers to identify the direction of the signal into or outof the terminal. The default is inputOutput. If the terminal specified in the Net Name fieldalready exists, it must have the same direction type as defined in the I/O Type field. If thedirection type is not the same, the system displays an error in the CIW and no MPP is created.

input allows a signal to come in only.

output allows a signal to go out only.

inputOutput allows signals to go in and out simultaneously (bidirectional).

switch allows a signal to go either in or out, but not both simultaneously.

jumper allows a signal to pass through the net.

Access Direction defines the access directions for the pin. The default is Top, Bottom, Left,and Right. When you choose Any, the Top, Bottom, Left, and Right options remain on.

Display Pin Name defines whether to create a text-display object using the net name andassociate it with the pin you are creating. The default is to not create a text-display object.

Note: The system uses the values of four fields to calculate the position of the pin name:Reference Handle, Offset X, Offset Y, and the Justification field on the Pin Name Display form.

Display Pin Name Option opens the Pin Name Display form to let you set values for howthe pin name is shown, such as the font, height, layer, rotation, and justification. For adescription of the Pin Name Display form, see “Opening the Pin Name Display Form” in theVirtuoso Layout Editor User Guide.



Reference Handle specifies the name of the handle on the master path or subpart to whichyou want to align the pin name. In this context, a handle is a point associated with the objectyou are defining (the master path or a subpart), such as the starting point or ending point ofthe object, or a point on the bounding box of the object. The default is centerCenter. For adetailed description of handles, see “Accessing Handles on ROD Objects” in the VirtuosoRelative Object Design User Guide.

Offset X is a signed floating-point number specifying the distance of the origin of the pinname along the X axis from the point specified by Reference Handle. The default is 0.

Offset Y is a signed floating-point number specifying the distance of the origin of the pinname along the Y axis from the point specified by Reference Handle. The default is 0.

ROD Subpart Form

Scroll Window lets you see a list of the offset, enclosure, or subrectangle subpaths thatalready exist for the MPP you are creating, depending on which of the following you select:Offset Subpath, Enclosure Subpath, or Subrectangle. There is one line of data for eachsubpath of the type selected. Each data element in a line corresponds to a field in the lowerpart of the ROD subpart form. When you click on an existing subpart in the scroll window, thesystem fills the fields in the rest of the ROD Subpart form with the values for that subpart. Youcan add a new subpart, delete an existing subpart, or change the values for an existingsubpart.

Add lets you create a new subpart from the values currently in the ROD Subpart form.

Delete lets you delete the highlighted subpart.

Edit lets you change the values for an existing subpart. Highlight the subpart you want tochange, change the values in the ROD Subpart form, and then click the Edit button. Thesystem replaces the field values of the highlighted subpart with the values currently in theROD Subpart form.

Offset Subpath lets you see one line of data for each existing offset subpath in the Scrollwindow, and lets you create a new offset subpath. To define an offset subpath, click on thisbutton, and the ROD Subpart form expands to show the fields for offset subpaths. For adescription of the offset subpath fields, see “Offset Subpath Fields” on page 400. For adetailed description of offset subpaths, see “About Offset Subpaths” in the VirtuosoRelative Object Design User Guide.

Enclosure Subpath lets you create a new enclosure subpath. To define an enclosuresubpath, click on this button, and the ROD Subpart form expands to show the fields forenclosure subpaths. For a description of the enclosure subpath fields, see “Enclosure



Subpath Fields” on page 402. For a detailed description of enclosure subpaths, see “AboutEnclosure Subpaths” in the Virtuoso Relative Object Design User Guide.

Subrectangle lets you create a new set of subrectangles. To define a set of subrectangles,click on this button, and the ROD Subpart form expands to show the fields for subrectangles.For a description of the subrectangle fields, see “Subrectangle Fields” on page 403. For adetailed description of subrectangles, see “About Sets of Subrectangles” in the VirtuosoRelative Object Design User Guide.



Offset Subpath Fields

Scroll Window at the top of the form lets you see a list of the offset subpaths that alreadyexist for the current MPP. There is one line of data for each offset subpath. Each data elementin a line corresponds to a field in the lower part of the ROD subpart form. The data for anoffset subpath is displayed in the following sequence:

When a subpart has connectivity, the connectivity data is listed in the sequence shown below.When Display Pin Name is equal to t , the following elements correspond to fields on the PinName Display form: Height, Layer, Justification, Font, Text Options, and Orientation.

Table 4 Offset Subpath Data in ROD Subpart Form Scroll Area

Order of Element Corresponding FormField Example

1 Layer ("poly1" "drawing")

2 Width 0.2

3 Choppable t

4 Separation 0.2

5 Justification "center"

6 Begin Offset nil

7 End Offset nil

8 List of connectivityelements, if any

See “Subpart Connectivity Data in RODSubpart Form Scroll Area” on page 400

Table 5 Subpart Connectivity Data in ROD Subpart Form Scroll Area

Order ofElement Corresponding Form Field Example

1 Net Name "pin1"

2 I/O Type "inputOutput"

3 Connectivity = Pin t

4 Access Direction ("left" "right" "top" "bottom")

5 Display Pin Name t

6 Height 1.0



Layer lets you choose the layer-purpose pair for the subpart. The default purpose isdrawing . Choosing a layer-purpose pair for a subpart does not change the current layer inthe LSW.

If the layer-purpose pair you choose is not a valid in the LSW, the system displays a dialogbox asking if you want to add the layer-purpose pair to the LSW. If you agree, the system addsthe layer-purpose pair, but does not change the current layer-purpose pair. If do not want toadd the layer-purpose pair to the LSW, choose a layer-purpose pair that is already in the LSWor the system will use the current layer-purpose pair.

Choppable indicates whether or not the subpart can be chopped. The default is choppable.When the master path is choppable, all of its subparts must be choppable. When the masterpath is not choppable, each of its subparts can be choppable or not.

Begin Offset specifies the offset of the starting edge of the subpath from the starting edgeof the master path.The value must be a signed integer or floating-point number. A positivenumber extends the beginning of the subpath beyond the beginning of the master path; anegative number retracts the beginning of the subpath from the beginning of the master path.The default is End Offset, if specified; otherwise 0.

End Offset specifies the offset of the ending edge of the subpath from the ending edge ofthe master path.The value must be a signed integer or floating-point number. A positivenumber extends the end of the subpath beyond the end of the master path; a negativenumber retracts the end of the subpath from the end of the master path. The default is BeginOffset, if specified; otherwise 0.

Width specifies the width of the offset subpath. The value must be a positive integer orfloating-point number. If you do not specify the width, the system uses the minWidth rule for

7 Layer ("text" "drawing")

8 Justification "centerCenter"

9 Font "stick"

10 Text Options t (for Drafting)

11 Orientation "R0"

12 Reference Handle "start0"

13 Offset X:Offset Y (2.0 3.0)

Table 5 Subpart Connectivity Data in ROD Subpart Form Scroll Area

Order ofElement Corresponding Form Field Example



the offset subpath layer from the technology file. If the minWidth rule is not defined in thetechnology file, the system uses the width of the master path.

Justification specifies from which part of the master path to separate the subpath, inrelation to the direction of the master path. When the value is left, the right edge of thesubpath is separated from the left edge of the master path. When the value is right, the leftedge of the subpath is separated from the right edge of the master path. When the value iscenter, the centerline of the subpath is separated from the centerline of the master path. Thedefault is center.

Separation specifies the distance between the centerline or an edge of the subpath and thecenterline or an edge of the master path, depending on the value of the Justification field. Thevalue must be a signed integer or floating-point number; the default is 0.

Connectivity determines whether to associate the subpart with a net and whether to makeit into a pin. The default is None. When you choose Net, the ROD Subpart form expands toshow the net connectivity fields. When you choose Pin, the form expands to show both thenet and pin connectivity fields.

None specifies that you do not want to define connectivity.

Net specifies that you want to associate the subpart with a specific net. You must type avalue in the Net Name field.

Pin specifies that you want the subpart to be a pin. To define a pin, you must also specifya value for the Net Name field.

For a description of the subpart connectivity fields, see “Connectivity Section” on page 397.

Enclosure Subpath Fields

Scroll Window at the top of the form lets you see a list of the enclosure subpaths thatalready exist for the current MPP. There is one line of data for each enclosure subpath. Eachdata element in the line corresponds to a field in the lower part of the ROD subpart form. Thedata for an enclosure subpath is displayed in the following sequence:

Table 6 Enclosure Subpath Data in ROD Subpart Form Scroll Area

Order ofElement

Corresponding FormField Example

1 Layer ("metal1" "drawing")

2 Enclosure 0.2



Layer is the same as for offset subpaths.

Choppab le is the same as for offset subpaths.

Begin Offset is the same as for offset subpaths.

End Offset is the same as for offset subpaths.

Enclosure specifies the enclosure of the subpath in relation to the master path. To calculatethe width of an enclosure subpath, the system subtracts two times the enclosure value fromthe width of the master path:

Width of Enclosure Subpath =Width of Master Path - (2 * Enclosure Value)

The value must be a signed integer or floating-point number. If you do not specify this field,the system uses the minEnclosure rule from the technology file for the master path layerto the subpath layer. If the minEnclosure rule is not defined in the technology file, thesystem sets the value to zero.

Connectivity is the same as for offset subpaths.

Subrectangle Fields

Scroll Window at the top of the form lets you see a list of the sets of subrectangles thatalready exist for the current MPP. There is one line of data for each set of subrectangles. Each

3 Choppable t

4 Begin Offset 0.2

5 End Offset -0.2



Table 6 Enclosure Subpath Data in ROD Subpart Form Scroll Area

Order ofElement




data element in the line corresponds to a field in the lower part of the ROD subpart form. Thedata for a set of subrectangles is displayed in the following sequence:

When a set of subrectangles has connectivity, the connectivity data is listed in the samesequence as for offset subpaths; see Table 5 on page 400.

Layer is the same as for offset subpaths.

Choppab le is the same as for offset subpaths.

Begin Offset specifies the offset of the starting edge of the first subrectangle from thestarting edge of the master path.The value must be a signed integer or floating-point number.A positive number extends the beginning of the subrectangles beyond the beginning of themaster path; a negative number retracts the beginning of the subrectangles from thebeginning of the master path. The default is End Offset, if specified; otherwise 0.

End Offset specifies the offset of the ending edge of the last subrectangle from the endingedge of the master path.The value must be a signed integer or floating-point number. Apositive number extends the end of the subrectangles beyond the end of the master path; anegative number retracts the end of the subrectangles from the end of the master path. Thedefault is Begin Offset, if specified; otherwise 0.

Table 7 Subrectangle Data in ROD Subpart Form Scroll Area

Order ofElement


1 Layer ("cont" "drawing")

2 Width 0.6

3 Length 0.6

4 Choppable t

5 Separation 0.0

6 Justification "center"

7 Space 0.6

8 Begin Offset -0.6

9 End Offset -0.6

10 Gap "distribute"





Width specifies the width of the rectangle(s). The width is parallel to the width of the masterpath. The value must be a positive integer or floating-point number.

If not specified, the system uses the value of the Length field; if neither is specified, thesystem uses the minWidth rule for the subrectangle layer from the technology file. If theminWidth rule is not defined in the technology file, the system uses the width of the masterpath.

Length specifies the length of the subrectangle(s). The length is parallel to the master pathcenterline.

If not specified, the system uses the value of the Width field; if neither is specified, the systemuses the minWidth rule for the subrectangle layer from the technology file. If Width is notspecified and the minWidth rule is not defined in the technology file, the system uses thewidth of the master path.

Gap specifies the method the system uses to place subrectangles within each segment. Thedefault is distribute. The system always uses the value of the Space field for minimum space

Width ofmaster path

Width ofsubrectangles

Length ofsubrectangles



between subrectangles and calculates the maximum number of rectangles that fit in thesegment. When the value of Gap is distribute, the system distributes the space aroundsubrectangles as evenly as possible, in multiples of the grid space specified bymfgGridResolution . Any remaining space is left after the last subrectangle in thesegment.

When the value of Gap is minimum, the system places subrectangles Space apart until thereis no space for another rectangle, then leaves the excess space after the last subrectangle inthe segment.

Space specifies the distance between the edges of adjoining rectangles. The value must bea positive integer or floating-point number. If not specified, the system uses the minSpacingrule for the subrectangle layer from the technology file. If the minSpacing rule is not definedin the technology file, you must enter a number or the system displays an error in the CIW.

Excess space is distributedevenly around subrectangles.

Excess space is leftat end of segment.



Justification specifies from which part of the master path to separate the subrectangles, inrelation to the direction of the master path. The default is center. When the value is left, theright edge of the subrectangles is separated from the left edge of the master path. When thevalue is right, the left edge of the subrectangles is separated from the right edge of the masterpath. When the value is center, the centerline of the subrectangles is separated from thecenterline of the master path.

Separation specifies the distance between the centerline or an edge of the subrectanglesand the centerline or an edge of the master path, depending on the value of the Justificationfield. The default is 0.

Connectivity is the same as for offset subpaths.



13Checking Design Data in the VirtuosoLayout Accelerator

This chapter explains how to use the Virtuoso® layout accelerator (Virtuoso XL) to check yourdesign as you work. This chapter discusses the following topics:

■ Finding Design Elements (Probing) on page 409

■ Checking Shorts and Opens on page 416

■ Comparing Design Elements and Parameters (Checking against the ConnectivitySource) on page 416



Virtuoso Layout Accelerator User GuideChecking Design Data in the Virtuoso Layout Accelerator

Finding Design Elements (Probing)

Probing lets you select a design element (component, net, or pin) in the layout (or schematic)window to highlight the corresponding element in the schematic (or layout) window.

To probe a design element, follow these steps.

1. From the layout window, choose Connectivity – XL Probe.

The layout window prompts you to point to a design object.

2. Click on a design object in the layout or schematic.

Virtuoso XL highlights the component, pin, or net you select in both the layout and theschematic (if both are open).

If you have multiple layout cellviews open, selecting a design element in one part of acellview pair (a connectivity source and a layout) highlights the corresponding elementin any other implementations of the other part.

For example, if you have several versions of a layout open, selecting R14 in theschematic highlights R14 in each of the layouts of that schematic.

If you want to use the Probe options, press F3.



The Probe Options form appears. For more information about this form see InformationAbout Online Forms in this chapter.

3. In the Object Filter section, turn on Pins, Nets, or Devices to choose the designelements to probe.

You can choose one, two, or all three of these design elements. When you click on adesign element, the Probe Options form displays information about the selected devicein the layout and schematic.

For example, if you click on the Q12 device in the layout, Q12 is highlighted in both theschematic and the layout using the hilite color displayed in the Probe Options formDisplay Layer box and the Probe Options form displays information about Q12.

hilitelayer



dev:(lay)Q12->(sch)Q12

If you want this information to be displayed in the Command Interpreter Window (CIW),turn on Send Messages to CIW.

If you want to create a net class, so that you can probe nets in groups relevant to yourdesign, click the Create Net Class button, which opens the Create/Edit Net Classesform.

You can also set the Show cyclic field to have the list box below display the names of allthe pins, nets, net classes, or devices in the design. You can click on the names in thelist box (instead of clicking on the objects in the design windows) to probe them.

Note: You can change the hilite drawing# layer colors from the Display ResourcesEditor.

4. To add additional elements to the Probe Information list, or to deselect items, holddown the Control key when you click on subsequent elements in the schematic,layout, or Probe form. You can select a range of names in the Probe Options form list byclicking on the top name and then clicking on the bottom name with Shift click.

If Virtuoso XL cannot find the design element in the schematic that corresponds to theone in the layout, you see a question mark (?) at the end of the listing in the form. Thedevice might not exist in the schematic, or the schematic window might be iconified orclosed.

dev:(lay)Q12->(sch)?

If you click on a place where there is more than one design element, Virtuoso XLhighlights design elements in the following order:

1. Pins

2. Nets

3. Devices



If you click on a place where there is more than one of the same kind of design element,a message window opens asking which one you want.

5. In the message window, click on the design element to probe and click OK.

Virtuoso XL highlights the component, net, or pin you choose and displays theinformation in the Virtuoso XL Probe Options form (if open).

Note: If you are cross-probing components bound by one-to-many/many-to-many/many-to-one mapping, probing one component bound by such mapping highlights all the componentsin the mapping group. If you probe an external net of a mapping group, the correspondingexternal net in the other window will be highlighted. Probing an internal net of a mappinggroup highlights the entire mapping group.

Note: If you open a schematic and two copies of the same layout, the Probe commandapplies to both layouts. If you have a schematic and two different layouts open, the Probecommand applies to only the layout from which you selected the command.

Probing Hierarchical Designs

To probe a hierarchical design, follow these steps.

1. Open the layout and schematic (the cell view pair, pair #1) in Virtuoso XL.

2. Select the device to probe.



In the diagram below, the device to probe is an inverter (CV1). It is represented in thelayout as pair of transistors (a flat representation).

3. Choose Design – Hierarchy – Edit in Place.

The schematic of the inverter opens (CV3 in the diagram).

If you select one of the transistors in this schematic to probe, the corresponding transistorin the layout in the level above is highlighted (CV2 in the diagram).

4. In the inverter schematic (CV3), select one of the two NMOS elements.

5. In the schematic window Tools menu, choose Design Synthesis – Layout XL to openthe layout of the inverter (CV4 in the diagram) in Virtuoso XL.

Top: Schematic (CV1) Top: Layout (CV2)

VXL Cellview Pair #1)

Inv: Schematic (CV3) Inv: Layout (CV4)






This creates another cellview pair (pair #2).

6. To descend into the schematic of the inverter, select one of the NMOS elements and fromthe schematic window choose Design – Hierarchy – Edit in Place.

The schematic of the NMOS opens (CV5 in the diagram).

If you probe the transistor in this schematic, the corresponding transistor in the layout inthe level above is highlighted (CV4 in the diagram).

7. In the schematic window Tools menu, choose Design Synthesis – Layout XL to openthe layout of the transistor (CV6 in the diagram) in Virtuoso XL.

This creates another cellview pair (pair # 3). You can probe from NMOS: Schematic backto Top: Layout, Inv: Layout, and NMOS: Layout



Inv: Schematic (CV3) Inv: Layout (CV4)


NMOS: Schematic (CV5) NMOS: Layout (CV6)




Removing Probes

To remove an individual probe from the layout,

➤ Hold down the Control key and click on the probe to delete.

To remove all probes from windows,

➤ Click on an empty space in the layout window.

Exiting the Probe Command

To exit the Probe command,

➤ Click Cancel in the Virtuoso XL Probe Options form or press Escape .

Showing the Options Form

To set the Probe Options form to appear each time you use the Probe command, follow thesesteps.

1. From the CIW, choose Utilities – User Preferences.

The User Preferences form appears.

2. Click Options Displayed When Commands Start.

3. Click OK.

The options form opens automatically the next time you use the Probe command.



Checking Shorts and Opens

To check the number of incomplete nets, short markers, and illegal overlap markers,

➤ From the layout window, choose Connectivity – Check – Shorts and Opens.

A text window opens, displaying in report format the number of incomplete nets, shorts,and illegal overlaps currently in the layout window. This command also reports shortsand opens in nets where pins are weakly connected and must connected.

Note: This command is grayed out and cannot be used when the connectivity extractor isturned off (on the Layout XL Options form).

Comparing Design Elements and Parameters (Checkingagainst the Connectivity Source)

You can check whether

■ All devices in the schematic are present in the layout



■ All devices in the layout are present in the schematic

■ All properties listed for devices in the schematic are associated with equivalentproperties on devices in the layout

To compare design elements and their parameters in the schematic with those in the layout,follow these steps.

1. From the layout window, choose Connectivity – Check – Against Source.

If devices in the schematic are missing in the layout, a Virtuoso XL Info window opensand lists the name of the components. The components are highlighted in the schematic.

If a device that is not on the schematic is present in the layout, it appears with a blinkingmarker.

Note: Check – Against Source does not report missing or extra pins and does notcheck devices with the lvsIgnore property or pins on devices with the ignoreNamesproperty.

npn

npn np

n

npn

npn

npn

npn

in

out

Marker



If a device parameter in the layout is different from the corresponding parameter in theschematic, a text window appears and lists the device names and properties (unless thedevice is ignored).

2. To save the information in an ASCII file or close the window, use the commands on theFile menu in the Virtuoso XL Info window.




Probe Options Form

Object Filter specifies the objects highlighted by the probe command.

Pins specifies that the probe command highlights pins.

Nets specifies that the probe command highlights nets.

Devices specifies that the probe command highlights devices.

Display Layer shows which of the hilite drawing # layers is to be used in the next probedrawn.

Cycle , when turned on, changes the hilite layer to the next color when a new object isprobed. When Cycle is not turned on, the hilite layer does not change to the next color eachtime a new object is probed.

Send Messages to CIW , when turned on, sends the information about the objects probedto the CIW (as well as displaying it in the box at the bottom of the form, when the form is open).

Create Net Class displays the Create/Edit Net Classes form, which allows you to group netsinto classes, so that you can probe nets in groups relevant to your design.

Show displays in the list box the names of the nets, pins, net classes, or devices in the design(depending on which category you select in the cyclic field). When you click on one or moreitems in the list box, the items are probed (highlighted) in the schematic and in the layout andthe name, window, and equivalency information about each item is shown in the display box.When you remove a probe, that information disappears from the display box.



14Updating Design Data in Virtuoso XL

This chapter explains how to use the Virtuoso® layout accelerator (Virtuoso XL) to makedesign changes and update your design as you progress. This chapter contains informationabout the following areas:

■ Updating Components and Nets (ECO Mode) on page 421

■ Updating Layout Parameters on page 427

■ Updating Schematic Parameters on page 429

■ Updating Device Correspondence on page 431

■ Updating the Connectivity Reference on page 433

■ Changing the Device (Instance) View on page 434



Virtuoso Layout Accelerator User GuideUpdating Design Data in Virtuoso XL

Updating Components and Nets(ECO Mode)

You can automatically update the layout to add any devices, pins, or connectivity changes youhave added to the schematic. This operation is sometimes known as Engineering ChangeOrder (ECO) mode.

It is helpful to have Show Incomplete Nets active when you update components and netsso that you can see that the connectivity you want is made.

To update the components and nets in a layout with changes made to the schematic, followthese steps.

1. Extract the schematic by choosing from the schematic windowCheck – Current Cellview.

The schematic editor extracts the connectivity of the design and reports the results in aSchematic Check information window.

2. From the layout window, choose Connectivity – Update – Components and Nets.

Virtuoso XL checks the components and nets in the schematic against the ones in thelayout.

If there are no differences, a message appears in the Command Interpreter Window(CIW) saying that the check has been completed successfully.

If there are differences, the differences are displayed in the CIW.

If devices are found in the layout that are not in the schematic, they are displayed withmarkers.

If devices or pins in the schematic are missing from the layout, the Layout GenerationOptions form opens. For more information about using this form, see the LayoutGeneration Options Form in Chapter 7.



If the I/O Pins option is turned on, the pins shown in the I/O Pins section of the formare those that exist in the schematic but are missing from the layout.

Note: the Layout Generation Options form always reflects the default settings for thedesign; that is, the state of the schematic, not the entries from the previous time the formwas used.

3. In the Layout Generation section at the top of the form,

a. If you want to generate pins, instances, or a boundary as specified in the schematicor in a template file, check that the options you want are turned on.

Note: Update Components and Nets recreates chains and preserves folded devicesas they existed after running the Layout Generation Options with chaining and foldingoptions turned on. Devices that had been chained previously to running UpdateComponents and Nets are moved from their existing positions.

❑ Recreate the abutment into stacks of MOS transistors or fingers of folded MOStransistors that were unabutted since you created them with the Gen From Sourcecommand



❑ Recreate and fold MOS transistors that were unfolded or all fingers of which weredeleted since you created them with the Gen From Layout command

If the Transistor Chaining and Transistor Folding options are off, and you havedeleted all the fingers of a folded transistor, Update Components and Netsgenerates a single device. If you have deleted some of the fingers of a folded device,it creates markers only if fingers in a numbered sequence are missing; otherwise itdoes nothing about missing fingers of folded transistors.

Note:

b. If you want to preserve existing many-to-many mapping of devices between theconnectivity source and the layout, turn on Preserve Mappings.

Note: The Preserve Mappings functionality does not report missing devices or shapeswithin a mapped group.

4. For each pin you want to add, click Add a Pin.

An empty pin row opens.

5. For each pin you want to add in the new pin row

a. In the Net Name column, type in a net name.

b. In the Pin Type cyclic field, choose a pin type.

c. In the Layer/Master cyclic field, choose a layer.

d. In the Width field, specify the pin width.

e. In the Height field, specify the pin height.

f. In the Num field, specify the number of pins you want.

6. For all pins set the Pin Label Shape.

a. Set Label to generate labels for each pin on the text dg layer purpose pair.

b. Set Text Display to generate text for each pin on the text dg layer purpose pair.

To view the text, set the Pin Names option on in the Display Options form.

c. Set None to not generate labels for pins.



7. To set the style of the pin labels, click Display Pin Name Option....

The Display Pin Name Option form appears.

8. Choose the options you want from the Set Pin Label Text Style form and click OK.

9. In the Boundary section of the Layout Generation Options form, if you want Virtuoso XLto draw a boundary, follow these steps.

a. In the Layer field, choose the layer you want to use for the boundary.

b. In the Shape field, choose Rectangle or Polygon.

To specify the dimensions of a rectangular boundary, you can use only two of thefollowing four values: Utilization %, Aspect Ratio (Width/Height), BoundaryWidth, or Boundary Height. You can also type in the Points field values for theLeft (X coordinate) side of the boundary and the Bottom (Y coordinate) side of theboundary in this format: (0 0) (10 10).

To specify the dimensions of a polygonal boundary, choose Polygon from theShape field and enter the X and Y coordinates of each angle of the polygon in the



Points type-in field in the following format. For example, for a rectangle: (0 0) (0 10)(10 8) (8 0) (0 0).

When you move the cursor in the layout window, the X and Y coordinates of thelocation of the cursor are displayed in the Status Line at the top of the layout window.

10. In the Template File section, to load a template file, (an ASCII file containing theinformation entered in this form in a previous session and saved to a file) follow thesesteps.

a. Click Load.

The Load Template File form appears

b. Click on the directories in the left list box to descend into your file hierarchy until youreach the name of the template file to use.

c. Click on the name of the template file in the right list box to enter it in the Name field.


d. Click OK in the Load Template File form.

The values in the template file are loaded into the Layout Generation Options formand are used during the design session.



You can set an environment variable, templateFileName ,, to always load thename of a template you specify as the value of the variable.

11. In the Template File section, to save the information you enter in the Layout GenerationOptions form to a template file (an ASCII file) to use in a later session., follow these steps.

a. Click Save.


b. Click on the directories in the left list box to descend into your file hierarchy until youreach the directory where you want to store the template file.


c. Accept the default template file name that appears in the Name field<design_name.lxt> or type in a template file name you choose.

d. Turn on the sections of the template file you want to save (I/O Pins, Boundary, orPlacement).

e. Click OK.


12. Click OK.

Virtuoso XL puts any missing pins and components below the design boundary andupdates their connectivity.

If a device that has been folded into fingers is missing in the layout, Virtuoso XL recreatesthe device.

If one or more fingers of a device that has been folded into fingers is missing in the layout,the CIW displays a warning that the fingers corresponding to the schematic instance aremissing, but it does not recreate the fingers.

If a parameter regulating the width of the fingers of a folded device has changed in theschematic, it is not changed in the layout by this command. Use the Update LayoutParameters command to implement parameter changes in the schematic that affectphysical implementations in the layout.

Update – Components and Nets preserves many-to-one and many-to-many mappingbetween the connectivity source and the layout cellview.

Note: You can use the Edit – Undo command to undo any changes that you made with theUpdate – Components and Nets command.



Updating Layout Parameters

To update the parameters of instances in the layout to match those in the schematic, followthese steps.

1. From the layout window, choose Connectivity – Update – Layout Parameters.

If you preselected instances, Virtuoso XL checks parameters of those instances in theschematic against their parameters in the layout and updates the layout parameterswhen it finds differences.

If you did not preselect instances, the CIW and the layout window prompt you to selectdevices whose parameters you want to update.

If there is no schematic referenced by the layout, the Define Connectivity Reference formappears. If there is currently a connectivity reference for the layout, that information isdisplayed. You can change the connectivity reference in this form.

Note: Update – Layout Parameters does not update folded devices if their size isdifferent from what is specified in the schematic. Check the size of folded devicesmanually to avoid overriding the specified size.

2. Click OK on the Define Connectivity Reference form.

3. Select a device in the layout or schematic window.

You can use Shift click to select more than one instance. Virtuoso XL highlights theinstance in the layout and the schematic window.

4. Move the cursor to the layout window and press Return .

Virtuoso XL checks parameters of those instances in the schematic against theirparameters in the layout and updates the layout parameters when it finds differences.

5. To see a list of the layout devices, move the cursor to the layout window and press F3.



The Update Layout Device List form appears. For more information about this form, seeChange Inst View Device List Form/ Update Layout Device List Form/ Update SchematicDevice List Form on page 437

6. Click a device name in the Update Layout Device List form to select it.

You can use Control click to select more than one device and to deselect selecteddevices.

7. Click Apply.

Virtuoso XL checks parameters of those instances in the schematic against theirparameters in the layout and updates the layout parameters when it finds differences(unless you have set the ignore or lvsIgnore property on a device).

Information about layout instances that contain properties that are not on their schematiccounterparts is displayed in the Virtuoso XL Info window.

Type the device nameand click the Searchbutton.

The device name ishighlighted.

|P1

Apply



When Virtuoso XL checks or updates any instance, a Virtuoso XL Info window reportsthe updates that were made.

If updating parameters results in a change in the layout, Virtuoso XL updates theconnectivity and indicates any shorts with markers.

Note: Update Components and Nets does not update split transistors if the sizes ofthe resulting transistors are different because such transistors may be the result ofmanual splitting. If the layout figure selected for update is a transistor that has beenfolded, Virtuoso XL displays a message box that says that it is not updating theparameters.

8. Press Escape to exit the command.

Note: If you are using inherited connections in your design to assign more than one value toa global net, remember that the netSet properties on schematic instances, which specifythe new value of a global signal, are not copied over with the instance from the schematic tothe layout when you use the Gen From Source, Pick from Schematic, or Update LayoutParameters commands.

Updating Schematic Parameters

To update the parameters of devices in the schematic to match those in the layout, followthese steps.

Note: You must have the schematic window open in edit mode to use this command.

1. From the layout window, choose Connectivity – Update – Schematic Parameters.

If you preselected instances, Virtuoso XL checks parameters of the selected instancesin the schematic against the parameters of the corresponding instances in the layout and



updates the schematic parameters when it finds differences. A Virtuoso XL Info windowreports the change.

If you did not preselect instances, the CIW and layout window prompt you to selectinstances whose parameters you want to update.

2. Select a device in either the layout or schematic window.

You can use Shift click to select more than one device. Virtuoso XL highlights the devicein the window.

3. Move the cursor to the layout window and press Return .

Virtuoso XL checks parameters of those instances in the schematic against theirparameters in the layout and updates the schematic parameters when it finds differences(unless you have set the ignore or lvsIgnore property on a device).

4. To see a list of the layout devices, move the cursor to the layout window and press F3.

The Update Schematic Device List form appears. For more information about this form,see Change Inst View Device List Form/ Update Layout Device List Form/ UpdateSchematic Device List Form on page 437

5. Select a device name in the Update Schematic Device List form.

You can use Control click to select more than one device.

6. Click Apply.


Apply

Type the net name andclickthe Search button.



Virtuoso XL checks parameters of those instances in the schematic against theirparameters in the layout and updates the schematic parameters when it findsdifferences.

When Virtuoso XL checks or updates any instance, a Virtuoso XL Info window reportsthe updates that were made.

7. Press Escape to exit the command.

Updating Device Correspondence

You can use the Update Device Correspondence command to maintain connectivity in alayout when you want to

■ Apply the connectivity from a symbol in the default schematic to a device in the layout

■ Apply the connectivity from a group of symbols in the default schematic to a device orgroup of devices in the layout (many-to-many and many-to-one mapping)

■ Apply connectivity to devices in a layout from a relevant schematic if you did not useVirtuoso XL to generate your layout

It is helpful to have the Show Incomplete Nets command active when you update devicecorrespondences so that you can see that the connectivity you want is made.

Note: You cannot preselect devices to use with the Update Device Correspondencecommand.

To update connectivity of a device or devices in the layout from a schematic, follow thesesteps.

‘(-0.125 0.125)’



1. From the layout window, choose Connectivity – Update – Device Correspondence.

The schematic window prompts you to click on one or more symbols.

2. In a schematic window, click on the symbols whose connectivity you want to update inthe layout.

Note: If you click on more than one symbol, the connectivity from those symbols isapplied as a group to the device or devices you select in the layout. For example, asshown in the diagram, you might select N1, N2, R1, and R2 in the schematic tocorrespond to the device X in the layout.

3. With the cursor in the schematic window, press Return .

The layout window prompts you to select one or more corresponding objects in the layoutwindow.

4. In the layout window, click on the object or objects to associate with the symbol.

5. With the cursor in the layout window, press Return .

A message such as this one appears in the CIW saying that the connection has beenmade:

Virtuoso XL: Instance ’I1’ in cellView ’overview amp1 layout’ isrenamed ’|R21’.

If the Show Incomplete Nets command is active, flight lines show that the connectionhas been made. If the connection cannot be made, a message box identifies theproblem.

6. To cancel the command, press Escape .

Note: If you have set the ignore or lvsIgnore property on a device or theignoreNames property on a pin and then try to make that device or pin correspond toanother device, Virtuoso XL opens a dialog box asking you to verify the removal of the

Vdd

Gnd

N1net A net B

N2

R1

Vdd

Gnd

net A net BX

R2



ignore or lvsIgnore property.

If you click OK, Virtuoso XL removes the property and sets the two devices tocorrespond. If you click Cancel, Virtuoso XL does not set the devices to correspond.

Updating the Connectivity Reference

In Virtuoso XL, the default schematic is the schematic with the same cellview name as thelayout.

You can change this setup so that you can update your layout using a schematic different fromthe default schematic by following these steps.

1. Choose Connectivity – Update – Source.

The Define Connectivity Reference form appears. For more information about this formsee Define Connectivity Reference Form on page 193

2. Choose Schematic as the connectivity source type.

3. Do one of the following:

❑ Type the name of the library, cell, and view of the device to update in Library, Cell,and View fields.

❑ Click Browse to see the cells available in the Library Browser, and click on a cellname in the Library Browser.

❑ Click Sel by Cursor and then click on an open schematic.



4. Click OK.

Virtuoso XL sets the connectivity reference to the schematic you selected.

Changing the Device (Instance) View

To change the layout view of a device or selected set of devices in a hierarchical design, followthese steps.

1. From the layout window, choose Connectivity – Change Instance View.

The Change Instance View form appears. For more information on this form, see ChangeInstance View Form on page 436

2. Click on the device whose layout view you want to change (or type the name in the DevName field).

To select multiple devices, hold down Shift . You can move from one selected deviceto the next using Next and Previous. The Switch to View Name cyclic field changesto show the device name and available view names for the device displayed in the cyclicfield. A dialog box appears and tells you when you reach the first or last device.

3. From the Switch to View Name cyclic field, select the view name you want.

4. To see all the devices in your layout and the view names available for them, click ListDevices.

The Change Inst View Device List form appears, showing all devices associated with thelayout you have open. For more information on this form, see Change Inst View Device



List Form/ Update Layout Device List Form/ Update Schematic Device List Form onpage 437 .

5. Double-click on a device name.

The device name appears in the Dev Name field in the Change Instance View form.

6. In the Change Instance View form, click Apply.

Virtuoso XL applies the new view name to the device.


Type the device nameand click the Searchbutton.




Change Instance View Form on page 436

Change Inst View Device List Form/ Update Layout Device List Form/ Update SchematicDevice List Form on page 437

Change Instance View Form

Dev Name specifies the name of a device whose layout view you want to change.

common selects multiple devices whose layout view you want to change to a common layoutview. When common is selected, clicking on Apply associates the cell view displayed in thecyclic field to all the devices chosen (the number shown at the bottom of the form).

Switch to View Name changes to include the name of the device you select (Switch cell“res” to View Name) and lets you choose from the cyclic field the cell view to which you wantto attach the device. The choices shown in the cyclic field are set by the stopList variable.If no cell view is associated with the device you choose, this field is not shown.

n of n fields displays the order and number of devices you have chosen to attach to a givencell view. You can enter data in these fields.

List Devices shows the devices present in your layout and the view names associated witheach.



Change Inst View Device List Form/Update Layout Device List Form/Update Schematic Device List Form

The Device List form shows all the devices in the design. Several Virtuoso XL commands usethe Device List form.

To select a device or devices on which you want to perform an action, click on the device youwant to select, or hold down Control and click to select more than one device.

Search finds and selects the names of devices you specify.

You can type in the field to the right of the Search button:

■ A device name

The Device List form highlights the device and scrolls the list to make the device namevisible.

■ A part of a device name (“IN,” for example)

The Device List form highlights all the devices with “IN” as an element in the name (IN3,IN6, IN7, IN12, for example) and scrolls the list to make the first example visible.

■ A regular SKILL expression using part of a device name (“*mos,” for example)

The Device List form highlights all devices with the string “*mos”, (nmos, pmos, forexample) and scrolls the list to make the first example visible.



15Troubleshooting Problems in theVirtuoso Layout Accelerator

This chapter provides information about what to do if unexpected results occur during theVirtuoso® layout accelerator (Virtuoso XL) design process. This chapter covers the followingtopics:

Problems with the Interface

■ Invalid Markers from Previous Software Versions on page 440

■ Options Form Does Not Appear on page 441

■ Virtuoso XL Commands Disappear on page 441

■ Virtuoso XL Performance Is Slow on page 441

Problems with editing

■ Components Move Slowly on page 443

■ Extra Probes Appear on page 443

■ Layout Generation Options Form Does Not Keep Values from the Last Entry on page 443

■ Parameters Not Updated on page 443

■ Schematic Not Editable on page 443

■ Warning to Update Your Design Appears at Startup on page 444

Problems with stretching parameterized cells

■ Pcell Stretch Handles Are Not Visible on page 120

■ Difficulty Selecting Pcell Stretch Handles on page 446

■ Difficulty Stretching Pcell Handles on page 446

■ Cannot See Objects Inside Pcell During Stretch on page 447


Virtuoso Layout Accelerator User GuideTroubleshooting Problems in the Virtuoso Layout Accelerator

Problems with connectivity

■ Connections Not Made on page 448

■ Incomplete Nets Command Does Not Recognize Connected Pins and Nets on page 448

■ Markers for Nonexistent Overlaps and Shorts Appear on page 448

■ Path Ends Not Accepted on page 449

■ Placement and Routing Do Not Run on page 449

■ Virtuoso XL Does Not Recognize Physical Vias on page 450



Problems with the Interface

Invalid Markers from Previous Software Versions

If you are opening layouts you developed with previous versions of Virtuoso software, you canclean up the layout window and get rid of invalid markers.

1. From the layout window, choose Connectivity – Update – Components and Nets.

Virtuoso XL resynchronizes the layout connectivity with the schematic connectivity.

2. From the layout window, choose Verify – Markers – Delete All.

The markers disappear.

3. Choose Design – Save.

4. From the layout window, choose Window – Close.

The layout window closes.

5. From the schematic window, choose Window – Close.

6. The schematic window closes.

7. From the Command Interpreter Window (CIW), choose File – Open.


8. From the Library Name cyclic field, choose the library name of your design.

9. In the Cell Name field, type or select from the Cell Names list the cell name of yourdesign.

10. From the View Name cyclic field, choose the view name of your design.

11. Click OK.

The layout window appears, displaying the updated layout configuration.

12. In the layout window, choose Tools – Layout XL.

The Layer Selection Window (LSW) and the schematic view appear.

Note: If you still have problems, make sure that lxExtractLayers is defined.



Options Form Does Not Appear

When you press F3 to see an options form listing possible choices for a command and thecommand does not have an options form, the message box shown below appears:

If you want the message box to appear every time you press F3 for a command that has nooptions form, click Yes.

If you do not want the message box to appear every time you press F3 for a command thathas no options form, click No.

Virtuoso XL Commands Disappear

You cannot use Virtuoso XL while you are viewing a lower level of a hierarchical design. TheVirtuoso XL commands disappear from the layout window when you descend into ahierarchical design and reappear when you return to the top level.

Virtuoso XL Performance Is Slow

The following considerations can help you optimize Virtuoso XL performance speed:

■ Virtuoso XL is targeted for use in designs with fewer than 10,000 devices. Theperformance of the online extractor degrades substantially beyond that limit.

■ Incomplete net information is updated after every edit. If you have many incomplete nets,Virtuoso XL might take longer to redisplay your design. Consider turning off ShowIncomplete Nets when working on interconnect layers. Use the highlighting features of



the path command or probing to determine connections or display only nets you areworking on or that are relevant to the current task.

■ If you need extra pins in the layout for feedthrough nets or substrate connections,consider adding those after you have completed the main portion of the design. Addingextra pins increases the number of nets the extractor manages and slows Virtuoso XL’sperformance.

■ Define lxExtractLayers only on layers to be used as interconnect during wiringwith Virtuoso XL. Using more layers than necessary causes the extractor to check allshapes on those layers, which slows performance. If you do not have interconnect towells, do not make the well layers lxExtractLayers .



Problems with Editing

Components Move Slowly

If you find that the Move command works too slowly, especially when you have many iteratedinstances, turn off the layout window Connectivity – Show Incomplete Nets command ordisplay only nets that are relevant to the current task.

Extra Probes Appear

To delete unwanted probes in the schematic or layout windows, while the Probe commandis active,

➤ Click on an empty space in the design.

or at any time

➤ Press Control -Shift-L .

Layout Generation Options Form Does Not Keep Values from the LastEntry

The Layout Generation Options form displays default values each time it opens, it does notcarry over values from the previous entry. If you want to use values from a previous entry, youmust save these values to a template and then use the Load option on the form to open thetemplate and update the fields in the form with the information in the template.

Parameters Not Updated

If the parameters are not updated the way you expect, check for the presence of thelxIgnoredParams property on components of your design.

Schematic Not Editable

If you cannot make changes to the schematic,

■ Check that the schematic is editable (the Schematic window Design menu shows theMake Read Only command, not the Make Editable command).



■ Check with your system administrator to be sure you have a license for the Virtuososchematic editor (product 302).

Warning to Update Your Design Appears at Startup

When you open a design in Virtuoso XL and an Info window similar to this

appears, it means that the schematic has been changed after the last time the layout waschanged, so the layout is not the latest version of the design. You can update the layout fromthe changed schematic by using the layout window Connectivity – Check – AgainstSource command and then using either the Connectivity – Update – Components andNets or Connectivity – Update – Device Correspondence commands as needed.

Virtuoso XL Info

The schematic information has changed since this layout was last generatedor updated. To insure a correct layout, you should run Connectivity - Check -Against Source to determined what has changed.



Problems with Stretching Parameterized Cells

Pcell Stretch Handles Are Not Visible

If you cannot see handles on stretchable pcells, the option might be turned off or the stretchhandle layer might not be visible.

You can check whether pcell stretch handles are set to display with the layout editor DisplayOptions form or with the graphic and layout editor environment variabledisplayStretchHandles . The default is to display stretch handles. You cannot stretch ahandle unless it is displayed.

If the Stretch Handles option is turned on, and you still cannot see stretch handles onyour pcell, the layer containing them might not be visible. See “Making the Stretch HandleLayer Visible” on page 446 .

Turning On Stretch Handle Display in the Options Form

To turn on Stretch Handles in the layout editor Display Options form, do the following:

1. Choose Options – Display.

2. In the Display Options form, if necessary, turn on Stretch Handles and click OK.

Turning on Stretch Handle Display in the CIW

To check the current setting of the displayStretchHandles environment variable andchange it if necessary, do the following:

1. Type the following in the CIW:

envGetVal( "layout" "displayStretchHandles" )

If the system returns t , stretch handles are displayed and you can stop. If the systemreturns nil , continue with step 2.

2. Type the following in the CIW:

envSetVal("layout" "displayStretchHandles" ’boolean t)

To see the results of your changes, you need to redraw the window.

3. Choose Window – Redraw.



Making the Stretch Handle Layer Visible

The default layer for stretch handles is y0 drawing . To make that layer visible, do thefollowing:

1. In the Layer Selection Window (LSW), choose Edit – Set Valid Layers.

2. In the Set Valid Layer form, click y0 dg and click OK.

3. In the LSW, click AV to make all layers visible.



Note: If you want to use a different layer for stretch handles, you can change the layer withthe stretchHandlesLayer environment variable.

Difficulty Selecting Pcell Stretch Handles

If you have trouble selecting stretch handles, use area selection rather than point selection ortry turning off the layout editor Gravity On option. To turn off gravity, do the following:

1. Choose Options – Layout Editor.

2. In the Layout Editor Options form, click to turn off the Gravity On option.

3. Try again to select a stretch handle.

Difficulty Stretching Pcell Handles

Before stretching a pcell handle, turn off Constraint Assisted Mode. When you stretch apcell handle with Constraint Assisted Mode on, it looks as if the whole pcell is movingrather than stretching. By default the Constraint Assisted Mode is on.

You can turn off Constraint Assisted Mode in the Layout XL Options form or in the CIW.

1. To set the Constraint Assisted Mode in the CIW, type the following in the CIW:

envSetVal("layoutXL" "constraintAssistedMode" ‘boolean nil)

2. To use the Layout XL Options form to check the current setting of Constraint AssistedMode and change it if necessary, do the following:

❑ Choose Options – Layout XL.

❑ In the Layout XL Options form, turn off Constraint Assisted Mode and click OK.



Cannot See Objects Inside Pcell During Stretch

During a stretch operation, the system automatically displays an outline of the pcell instanceto show how it is changing. To see outlines of the objects inside of an instance during astretch, turn on Drag Enable in your technology file for the relevant layers.

1. In the CIW, choose Technology File – Edit Layers.

2. In the Layer Purpose Pair Editor form, for Technology Library, choose your library.

The system displays the layers defined in your library.

3. For each layer for which you want to turn on Drag Enable, do the following:

❑ Click on the name of the layer.

❑ For Layer Purpose Pairs, click Edit.

The Edit Layer Purpose Pair form appears.

❑ Click Drag Enable and click OK.

4. In the Layer Purpose Pair Editor form, click OK.

A dialog box opens to ask if you want to save your changes to the library (and technologyfile).

You can save your changes now or when you exit the software. If you do not save yourchanges, they are in effect only for the duration of your current editing session.

5. To save your changes now, click Yes in the dialog box.





Problems with Connectivity

Connections Not Made

If the software does not accept an electrical connection you make, make sure that thefollowing information is set in the technology file:

■ Connectivity information in the lxRules class

❑ lxExtractLayers (leConducting in version 4.3.4 and earlier) definesconducting layers

❑ lxNoOverlapLayers (leOverlap in version 4.3.4 and earlier) defines layersthat must not overlap

■ Layer information in the layerRules class

❑ equivalentLayers (leEquivalent in version 4.3.4 and earlier) defines layersthat are electrically equivalent

❑ viaLayers (leEquivalent in version 4.3.4 and earlier) defines layers used forvias and the layers they connect

Also check that the layer properties were set when you made the connection.

Incomplete Nets Command Does Not Recognize Connected Pins and Nets

If a pin is connected to a net but has the lxBlockExtractCheck property on it, theincomplete nets command does not recognize that the pin is connected.

If a layer you use for pcells is not listed in the technology file in the lxExtractLayers list,the incomplete nets command does not recognize incomplete nets noted on that layer.Furthermore, the probe code does not highlight any layer that is not listed in the technologyfile in the lxExtractLayers list.

Markers for Nonexistent Overlaps and Shorts Appear

If there are markers for nonexistent overlaps and shorts in the layout, make sure that theappropriate layer was active when the path was created.

If this does not fix the problem, make sure that the connectivity information(lxExtractLayers and lxNoOverlapLayers ) and layer information(equivalentLayers and viaLayers ) are set correctly in the technology file.



Path Ends Not Accepted

If the software rejects the final segment of a path or wire connection and displays the followingmessage:

➤ Press Return to end a path instead of double-clicking the mouse (do not double-clickto end a path).

or

➤ Set the layout window Design – Options – Display command to a snap mode otherthan x-first or y-first.

When you use the x-first or y-first snap modes, the double-click often makes a notch in thepath, which triggers the error message and can cause errors in mask layout.

Placement and Routing Do Not Run

Virtuoso XL does not let you place or route the elements of a design unless you have definedwhich layers of your layout design are conducting layers.

First or last segment of created path has lengthless than or equal to half the path width.

Notch



If you try to place or route your design before defining the conducting layers, you get an errormessage like this.

Define the layers you want to be conducting layers as lxExtractLayers in the lxRulesclass of the technology file.

Virtuoso XL Does Not Recognize Physical Vias

If you have an existing design in which Virtuoso XL does not recognize physical vias, youneed to add a property with name = “function”, value = “via” to the master cellview of the viaor to the component description format (CDF) for via layout.

There are no ‘lxExtractLayers’ defined in library ‘cmos_test’.

To get Virtuoso XL connectivity, you need to update your technology file.

Close

Virtuoso XL



AVirtuoso XL Command Quick Reference

Listed below are all the commands you can use in the Virtuoso® layout accelerator (VirtuosoXL) with a brief summary of what each command does and a link to more completedocumentation of the command.

Menu Name Command Name Command Function Documented

CIW: File –Import

XL Netlist Imports a CDL netlist touse as a connectivitysource for Virtuoso XL

Chapter 7, “Importing aNetlist for aConnectivityReference”

Design Gen From Source Creates and placesschematic symbolsbelow boundary inlayout

Chapter 7, “Generatinga Layout withComponents NotPlaced (Gen FromSource)”

Design Template –Load From File

Loads pin, boundary,and placementinformation you saved toa file to generate alayout

Chapter 7, “LoadingTemplate Files”

Design Template –Save To File

Saves pin, boundary,and placementinformation to generatelayout to a file for lateruse

Chapter 7, “SavingTemplate Files”

Create Multipart Path Creates relative objectdesign (ROD) multi-partpaths

Chapter 12, “AboutCreating MultipartPaths”


Virtuoso Layout Accelerator User GuideVirtuoso XL Command Quick Reference

Create Pick From Schematic Creates and placesinteractively selectedschematic elements inthe layout

Chapter 7, “MovingComponents from theSchematic into theLayout (Pick fromSchematic)”

Create Clone Copies parts ofschematic or layoutincluding connec-tivityinfo to use as other parts

Chapter 7, “CloningComponents”

Edit Other – Align Aligns layoutcomponents

Chapter 8, “AligningObjects”

Edit Other – SwapComponents

Exchanges the positionof two components

Chapter 8, “SwappingComponents”

Edit Other-Lock Selected Creates temporary fixedconstraints on layoutobjects

Chapter 8, “UsingDevice Locking”

Edit Other-Unlock Selected Removes temporaryfixed constraints fromlayout objects

Chapter 8, “UsingDevice Locking”

Edit Component Types Controls howcomponents are placedin rows, and definestheir chaining andfolding parameters

Chapter 8, “SettingComponent Types”

Edit Transistor Chaining Abuts prepared MOStransistors into stacks

Chapter 8, “UsingTransistor Chaining”

Edit Transistor Folding Splits prepared MOStransistors or stacks intofingers (smaller devicesconnected in parallel).

Chapter 8, “UsingTransistor Folding”

Edit Place From Schematic Places componentsfrom the schematicinside the layoutboundary in the samerelative position as in theschematic

Chapter 7, “PlacingComponents in aLayout in the SameRelative Position as inthe Schematic (Placefrom Schematic)”




Connectivity Assign Nets Assigns instance pinswith or without aconnectivity source orschematic to nets in thelayout

Chapter 8, “AssigningPins to a Net”

Connectivity Show Incomplete Nets Shows flight linesconnecting nets thathave not yet been routed(wired).

Chapter 8, “IdentifyingIncomplete Nets”

Connectivity Hide Incomplete Nets Removes flight linesconnecting nets thathave not yet been routed(wired).

Chapter 8, “IdentifyingIncomplete Nets”

Connectivity XL Probe Highlights the designelement in the layout orschematic when youclick on thecorresponding one inthe other window

Chapter 13, “FindingDesign Elements(Probing)”

Connectivity Permute Pins Switches the position ofpins set up forpermutation within aninstance.

Chapter 8, “PermutingComponent Pins”

Connectivity Check – Shorts andOpens

Reports the number ofincomplete nets, shorts,and illegal overlapscurrently in the layoutwindow.

Chapter 13, “CheckingShorts and Opens”

Connectivity Check – Against Source Reports the devices andparameters in theconnectivity source thatare missing in theschematic

Chapter 13,“Comparing DesignElements andParameters (Checkingagainst theConnectivity Source)”




Connectivity Update – Componentsand Nets

Updates the layout toadd devices, pins, orconnectivity changesadded to the schematic

Chapter 14, “UpdatingComponents and Nets(ECO Mode)”

Connectivity Update – LayoutParameters

Updates parameters ofinstances in the layout tomatch those in theschematic

Chapter 14, “UpdatingLayout Parameters”

Connectivity Update – SchematicParameters

Updates parameters ofdevices in the schematicto match those in thelayout

Chapter 14, “UpdatingSchematicParameters”

Connectivity Update – DeviceCorrespondence

Applies connectivityfrom schematicsymbol(s) to layoutdevice(s); allowsimplementation of oneor many to many or one

Chapter 14, “UpdatingDeviceCorrespondence”

Connectivity Update – Source Allows the connectivitysource for update to alayout to be a schematic,a netlist, or no source

Chapter 14, “Updatingthe ConnectivityReference”

Connectivity Change Instance View Changes the layout viewof a device or devices ina hierarchical design

Chapter 14, “Changingthe Device (Instance)View”

Options Layout XL Sets values of VirtuosoXL environmentvariables

Chapter 5, “SettingEnvironment Variablesin the Layout XLOptions Form”

