Virtual Memory Lee

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ECE3055ECE3055

Computer Architecture andComputer Architecture and

Operating SystemsOperating Systems

Lecture: Memory Subsystem (II)Lecture: Memory Subsystem (II)

OS PerspectiveOS Perspective

Prof. HsienProf. Hsien--Hsin Sean LeeHsin Sean Lee

School of Electrical and Computer EngineeringSchool of Electrical and Computer Engineering

Georgia Institute of TechnologyGeorgia Institute of Technology

BackgroundBackground

Program must be brought into memory and placed

within a process for it to be run

Input queue collection of processes on the disk that

are waiting to be brought into memory to run the

program

User programs go through several steps before being

run


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Binding of Instructions and Data to MemoryBinding of Instructions and Data to Memory

Compile time: If memory location known a

priori, absolute code can be generated; must

recompile code if starting location changes

Load time: Must generate relocatable code if

memory location is not known at compile time

Execution time: Binding delayed until run

time if the process can be moved during its

execution from one memory segment to

another. Need hardware support for addressmaps (e.g., base and limit registers).

Address binding of instructions and data to memory addresses can

happen at three different stages

MultiMulti--step Processing of a User Programstep Processing of a User Program


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Virtual vs. Physical Address SpaceVirtual vs. Physical Address Space

The concept of a virtual (or logical) address space that

is bound to a separatephysical address space iscentral to proper memory management

Virtual address generated by the CPU; also referred to as

virtual address

Physical address address seen by the memory unit

Virtual and physical addresses are the same in

compile-time and load-time address-binding schemes;

virtual and physical addresses differ in execution-time

address-binding scheme

Virtual MemoryVirtual Memory

Virtual memory separation of user logical memory

from physical memory.

Only part of the program needs to be in memory for

execution.

Logical address space can therefore be much larger than

physical address space.

Allows address spaces to be shared by several processes.

Allows for more efficient process creation.

Virtual memory can be implemented via:

Demand paging

Demand segmentation


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Virtual Address SpaceVirtual Address Space

Other Uses of Virtual MemoryOther Uses of Virtual Memory


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Virtual Memory Larger than PhysicalVirtual Memory Larger than Physical

Schematic View of SwappingSchematic View of Swapping


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PagingPaging

Virtual address space of a process can be non-contiguous in

physical address space; process is allocated physical memorywhenever the latter is available

Divide physical memory into fixed-sized blocks called frames (size

is power of 2, between 512 bytes and 8192 bytes)

Divide logical memory into blocks of same size called pages.

Keep track of all free frames

To run a program of size n pages, need to find n free frames and

load program

OS sets up apage tablepage table to translate virtual to physical addresses

Internal fragmentation

VirtualVirtual--toto--Physical Address TranslationPhysical Address Translation

Address generated by CPU is divided into:

Page number (p) used as an index into apage table which

contains base address of each page in physical memory

Page offset (d) combined with base address to define the

physical memory address that is sent to the memory unit


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Transfer of a Paged Memory toTransfer of a Paged Memory to

Contiguous Disk SpaceContiguous Disk Space

Paging ExamplePaging Example


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Paging ExamplePaging Example

Demand PagingDemand Paging

Bring a page into memory only when it is needed

Less I/O needed

Less memory needed

Faster response

More users

Page is needed reference to it invalid reference abort

not-in-memory bring to memory


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Address Translation: Page TableAddress Translation: Page Table

With each page table entry a validinvalid bit is associated(1 in-memory, 0 not-in-memory)

Initially validinvalid but is set to 0 on all entries Example of a page table snapshot:

During address translation, if validinvalid bit in page tableentry is 0 page faultpage fault

1

1

1

1

0

0

0

M

Frame # valid-invalid bit

page tablepage table

Free FramesFree Frames

Before allocation After allocation


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Address Translation ArchitectureAddress Translation Architecture

Page Table When Some Pages ArePage Table When Some Pages AreNot in Main MemoryNot in Main Memory


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Page FaultPage Fault

If there is ever a reference to a page, first reference will trap to

OS page fault OS looks at another table to decide:

Invalid reference abort.

Just not in memory.

Get empty frame.

Swap page into frame.

Reset tables, validation bit = 1.

Restart instruction: Least Recently Used

block move

auto increment/decrement location

Handling Page FaultHandling Page Fault


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What happens if there is no free frame?What happens if there is no free frame?

Page replacement find some page in memory, but

not really in use, swap it out algorithm

performance want an algorithm which will result in

minimum number of page faults

Same page may be brought into memory several

times

Page Table SizePage Table Size

Not all programs will use the entire available address

range

Wasteful to create a page table for every page in the

address range

Page table is in main memory, some systems

provide the following to indicate the size of the page

table for faster checking page table base registerpage table base register

page table length registerpage table length register

However, the size of a linear page table can be still

overwhelmingly large


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Page Table StructurePage Table Structure

Multi-level Paging

Hashed Page Tables

Inverted Page Tables

MultiMulti--Level (Hierarchical) Page TableLevel (Hierarchical) Page Table

Break up the virtual address space into multiple page

tables

Increase the utilization and reduce the physical size of

a page table

A simple technique is a two-level page table


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TwoTwo--Level Paging ExampleLevel Paging Example

A logical address (on 32-bit machine with 4K page size)

is divided into: a page number consisting of 20 bits

a page offset consisting of 12 bits

Since the page table is paged, the page number isfurther divided into:

a 10-bit page number

a 10-bit page offset

Thus, a logical address is as follows:

wherepi is an index into the outer page table, andp2 isthe displacement within the page of the outer page table

page number page offset

pi p2 d

10 10 12

TwoTwo--Level PageLevel Page--Table SchemeTable Scheme


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AddressAddress--Translation SchemeTranslation Scheme

Address-translation scheme for a two-level 32-bit

paging architecture

Hashed Page TableHashed Page Table

Common in address spaces > 32 bits

The virtual page number is hashed into a page table.

This page table contains a chain of elements hashing

to the same location.

Virtual page numbers are compared in this chain

searching for a match. If a match is found, the

corresponding physical frame is extracted.


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Hashed Page TableHashed Page Table

Inverted Page TableInverted Page Table

One entry for each real page of memory

Shared by all active processes

Entry consists of the virtual address of the page

stored in that real memory location, with PID

information

Decreases memory needed to store each page table,

but increases time needed to search the table when a

page reference occurs


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Inverted Page Table ArchitectureInverted Page Table Architecture

Linear Inverted Page TableLinear Inverted Page Table

Contain entries (size of physical memory) in a linear array

Need to traverse the array sequentially to find a match

Can be time consuming

PID VPNOffsetVPN = 0x2AA70

1 0x74094

12 0xFEA001 0x00023

8 0x2AA70

.. . . . . . .

PID = 8

Linear Inverted Page Table

PPNIndex

0

12

0x120C

.. . . . . .

0x120D14 0x2409A

match

OffsetPPN = 0x120D

Physical Address

Virtual Address


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Hashed Inverted Page TableHashed Inverted Page Table

Use hash table to limit the search to smaller number

of page-table entries

OffsetVPN = 0x2AA70PID = 8

Virtual Address

Hash PID VPN

1 0x74094

12 0xFEA00

1 0x00023

8 0x2AA70

.. . . . . . .

0

1

2

0x120C

.. . . . . .

0x120D14 0x2409A

0x0012

Next

---

0x120D

0x00A00x0980

. . . .

. . . .match

Implementation of Page TableImplementation of Page Table

Page table is kept in main memory

Page-table base register (PTBR) points to the start of

the page table

Page-table length register(PRLR) indicates size of

the page table

In this scheme every data/instruction access requires

two memory accesses. One for the page table and

one for the data/instruction.

The two memory access problem can be solved by

the use of a special fast-lookup hardware cache called

associative memory ortranslation look-aside

buffers (TLBs)


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Associative MemoryAssociative Memory

Associative memory parallel search

Address translation (A, A)

If A is in associative register, get frame # out

Otherwise get frame # from page table in memory

Page # Frame #

Paging Hardware With TLBPaging Hardware With TLB


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Effective Access TimeEffective Access Time

Associative Lookup = time unit

Assume memory cycle time is 1 microsecond

Hit ratio percentage of times that a page number is

found in the associative registers; ratio related to

number of associative registers

Hit ratio =

Effective Access Time (EAT)

EAT = (1 + ) + (2 + )(1 )

= 2 +

Memory ProtectionMemory Protection

Memory protection implemented by associating

protection bit with each frame

Valid-invalid bit attached to each entry in the page

table:

valid indicates that the associated page is in the process

logical address space, and is thus a legal page invalid indicates that the page is not in the process logical

address space


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Shared PagesShared Pages

Shared code

One copy of read-only (reentrant) code shared amongprocesses (i.e., text editors, compilers, window systems).

Shared code must appear in same location in the logical

address space of all processes

Private code and data

Each process keeps a separate copy of the code and data

The pages for the private code and data can appear

anywhere in the logical address space

Shared Pages ExampleShared Pages Example


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SegmentationSegmentation

Memory-management scheme that supports user

view of memory A program is a collection of segments. A segment is

a logical unit such as:

main program,

procedure,

function,

method,

object,

local variables, global variables,

common block,stack,

symbol table, arrays

UserUsers View of a Programs View of a Program


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Logical View of SegmentationLogical View of Segmentation

1

3

2

4

1

4

2

3

user space physical memory space

Segmentation ArchitectureSegmentation Architecture

Logical address consists of a two tuple:

,

Segment table maps two-dimensional physical

addresses; each table entry has:

base contains the starting physical address where the

segments reside in memory

limit specifies the length of the segment

Segment-table base register (STBR) points to the

segment tables location in memory

Segment-table length register (STLR) indicates

number of segments used by a program;

segment numbers is legal ifs < STLR


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Segmentation Architecture (Cont.)Segmentation Architecture (Cont.)

Relocation.

dynamic

by segment table

Sharing.

shared segments

same segment number

Allocation.

first fit/best fit

external fragmentation

Segmentation Architecture (Cont.)Segmentation Architecture (Cont.)

Protection. With each entry in segment table

associate:

validation bit = 0 illegal segment

read/write/execute privileges

Protection bits associated with segments; code

sharing occurs at segment level

Since segments vary in length, memory allocation is adynamic storage-allocation problem

A segmentation example is shown in the following

diagram


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Segmentation HardwareSegmentation Hardware

Example of SegmentationExample of Segmentation


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Sharing of SegmentsSharing of Segments

Segmentation with PagingSegmentation with Paging MULTICSMULTICS

The MULTICS system solved problems of external

fragmentation and lengthy search times by paging the

segments

Solution differs from pure segmentation in that the

segment-table entry contains not the base address of

the segment, but rather the base address of apagetable for this segment


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MULTICS Address TranslationMULTICS Address Translation

SchemeScheme

Segmentation with PagingSegmentation with Paging Intel x86Intel x86

As shown in the following diagram, the Intel x86uses segmentation with paging for memorymanagement with a two-level paging scheme


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Intel 30386 Address TranslationIntel 30386 Address Translation

Linux on Intel 80x86Linux on Intel 80x86

Uses minimal segmentation to keep memory

management implementation more portable

Uses 6 segments:

Kernel code

Kernel data

User code (shared by all user processes, using logical

addresses) User data (likewise shared)

Task-state (per-process hardware context)

LDT

Uses 2 protection levels:

Kernel mode

User mode

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