Virtex-II Pro Platform FPGA Documentationebook.pldworld.com/_Semiconductors/XILINX/DataSource CD... · 2002-02-26 · R Virtex-II Pro™ Platform FPGA Documentation • Advance Product

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Virtex-II Pro™ Platform FPGA Documentation

• Advance Product Specification• PPC405 User Manual• PPC405 Processor Block Manual • Rocket I/O™ Transceiver User Guide

March 2002 Release

Virtex-II Pro™ Platform FPGA Documentation www.xilinx.com March 2002 Release1-800-255-7778

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http://www.xilinx.com

March 2002 Release www.xilinx.com 3Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778

Volume 1: Virtex-II Pro™ Platform FPGA Advance Product Specification

Data Sheet Module 1:Virtex-II Pro™ Platform FPGAs: Introduction and Overview

Summary of Virtex-II Pro Features ................................................................................. 39Rocket I/O Features.............................................................................................................. 39PowerPC RISC Core Features.............................................................................................. 39Virtex-II Pro Platform FPGA Technology.......................................................................... 40

General Description ............................................................................................................... 40Architecture................................................................................................................................ 41

Virtex-II Pro Array Overview.............................................................................................. 41Virtex-II Pro Features............................................................................................................ 41

IP Core and Reference Support......................................................................................... 44Hardware Cores .................................................................................................................... 44Software Cores ....................................................................................................................... 44

Virtex-II Pro Device/Package Combinations and Maximum I/Os .................... 44Virtex-II Pro Ordering Information ................................................................................ 45Revision History ...................................................................................................................... 45Virtex-II Pro Data Sheet Modules ................................................................................... 45

Data Sheet Module 2:Virtex-II Pro™ Platform FPGAs: Functional Description

Virtex-II Pro Array Functional Description .............................................................. 47Virtex-II Pro Compared to Virtex-II Devices..................................................................... 47

Functional Description: Rocket I/O Multi-Gigabit Transceiver (MGT) ....... 47Overview ................................................................................................................................ 47Clock Synthesizer .................................................................................................................. 50Clock and Data Recovery ..................................................................................................... 50Transmitter ............................................................................................................................. 50Receiver................................................................................................................................... 51Loopback ................................................................................................................................ 51Elastic and Transmitter Buffers ........................................................................................... 51CRC.......................................................................................................................................... 53Configuration......................................................................................................................... 53Reset / Power Down............................................................................................................. 53Power Sequencing ................................................................................................................. 53

Functional Description: Processor Block ..................................................................... 54Processor Block Overview ................................................................................................... 54Embedded PowerPC 405 RISC Core .................................................................................. 54On-Chip Memory (OCM) Controllers................................................................................ 54Clock/Control Interface Logic ............................................................................................ 55CPU-FPGA Interfaces ........................................................................................................... 55CoreConnect™ Bus Architecture ....................................................................................... 56

Table of Contents


4 www.xilinx.com March 2002 Release1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation

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Functional Description: PowerPC 405 Core ................................................................ 57PPC405 Core........................................................................................................................... 57Instruction and Data Cache ................................................................................................. 57Fetch and Decode Logic ....................................................................................................... 58Execution Unit ....................................................................................................................... 58Memory Management Unit (MMU) ................................................................................... 58Timers...................................................................................................................................... 59Interrupts ................................................................................................................................ 59Debug Logic ........................................................................................................................... 59Big Endian and Little Endian Support ............................................................................... 60

Functional Description: FPGA .......................................................................................... 60Input/Output Blocks (IOBs) ................................................................................................ 60Digitally Controlled Impedance (DCI)............................................................................... 65Configurable Logic Blocks (CLBs) ...................................................................................... 683-State Buffers ........................................................................................................................ 76CLB/Slice Configurations.................................................................................................... 7618 Kb Block SelectRAM Resources ..................................................................................... 7718-Bit x 18-Bit Multipliers..................................................................................................... 80Global Clock Multiplexer Buffers ....................................................................................... 81Digital Clock Manager (DCM) ............................................................................................ 83Routing.................................................................................................................................... 86Configuration......................................................................................................................... 87

Revision History ...................................................................................................................... 90Virtex-II Pro Data Sheet Modules ................................................................................... 90

Data Sheet Module 3:Virtex-II Pro™ Platform FPGAs: DC and Switching Characteristics

Virtex-II Pro Electrical Characteristics........................................................................... 91Virtex-II Pro DC Characteristics.......................................................................................... 91Power-On Power Supply Requirements............................................................................ 93SelectI/O DC Input and Output Levels............................................................................. 94LDT DC Specifications (LDT_25) ........................................................................................ 95LVDS DC Specifications (LVDS_25)................................................................................... 95Extended LVDS DC Specifications (LVDSEXT_25) ......................................................... 95Rocket I/O DC Input and Output Levels .......................................................................... 96

Virtex-II Pro Performance Characteristics ................................................................... 97Virtex-II Pro Switching Characteristics......................................................................... 99

Testing of Switching Characteristics .................................................................................. 99PowerPC Switching Characteristics ................................................................................. 100Rocket I/O Switching Characteristics .............................................................................. 103IOB Input Switching Characteristics ................................................................................ 108IOB Input Switching Characteristics Standard Adjustments ....................................... 109IOB Output Switching Characteristics ............................................................................. 110IOB Output Switching Characteristics Standard Adjustments .................................... 111Clock Distribution Switching Characteristics ................................................................ 117CLB Switching Characteristics .......................................................................................... 117CLB Distributed RAM Switching Characteristics .......................................................... 118CLB Shift Register Switching Characteristics.................................................................. 118Multiplier Switching Characteristics ................................................................................ 119Block SelectRAM Switching Characteristics ................................................................... 120TBUF Switching Characteristics........................................................................................ 120JTAG Test Access Port Switching Characteristics .......................................................... 120

Virtex-II Pro Pin-to-Pin Output Parameter Guidelines ....................................... 121



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Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, With DCM........................................................................................................................ 121

Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, Without DCM ................................................................................................................. 122

Virtex-II Pro Pin-to-Pin Input Parameter Guidelines........................................... 123Global Clock Set-Up and Hold for LVCMOS25 Standard, With DCM....................... 123Global Clock Set-Up and Hold for LVCMOS25 Standard, Without DCM................. 124

DCM Timing Parameters ................................................................................................... 124Operating Frequency Ranges ............................................................................................ 124Input Clock Tolerances....................................................................................................... 126Output Clock Jitter .............................................................................................................. 127Output Clock Phase Alignment ........................................................................................ 127Miscellaneous Timing Parameters.................................................................................... 128Frequency Synthesis ........................................................................................................... 128Parameter Cross-Reference ................................................................................................ 129

Revision History .................................................................................................................... 129Virtex-II Pro Data Sheet Modules ................................................................................. 129

Data Sheet Module 4:Virtex-II Pro™ Platform FPGAs: Pinout Information

Virtex-II Pro Device/Package Combinations and Maximum I/Os .................. 131Virtex-II Pro Pin Definitions............................................................................................ 132

Pin Definitions ..................................................................................................................... 133FG256 Fine-Pitch BGA Package ...................................................................................... 135

FG256 Fine-Pitch BGA Package Specifications (1.00mm pitch) ................................... 143FG456 Fine-Pitch BGA Package ...................................................................................... 144

FG456 Fine-Pitch BGA Package Specifications (1.00mm pitch) ................................... 158FF672 Flip-Chip Fine-Pitch BGA Package.................................................................. 159

FF672 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) .................. 179FF896 Flip-Chip Fine-Pitch BGA Package.................................................................. 180

FF896 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) .................. 205FF1152 Flip-Chip Fine-Pitch BGA Package ............................................................... 206

FF1152 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) ................ 239FF1517 Flip-Chip Fine-Pitch BGA Package ............................................................... 240

FF1517 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) ................ 278BF957 Flip-Chip BGA Package........................................................................................ 279

BF957 Flip-Chip BGA Package Specifications (1.27mm pitch) ..................................... 305Revision History .................................................................................................................... 306Virtex-II Pro Data Sheet Modules ................................................................................. 306



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Volume 2:Virtex-II Pro™ Processor

Volume 2(a): PPC405 User Manual

About This BookDocument Organization..................................................................................................... 311Document Conventions...................................................................................................... 312

General Conventions .......................................................................................................... 312Instruction Fields................................................................................................................. 313Pseudocode Conventions ................................................................................................... 315Operator Precedence........................................................................................................... 317

Registers .................................................................................................................................... 317Terms .......................................................................................................................................... 318Additional Reading .............................................................................................................. 321

Chapter 1: Introduction to the PPC405PowerPC Architecture Overview ................................................................................... 323

PowerPC Architecture Levels............................................................................................ 324PowerPC Embedded-Environment Architecture ........................................................... 326PowerPC Book-E Architecture .......................................................................................... 329

PPC405 Features ..................................................................................................................... 329Privilege Modes ................................................................................................................... 330Address Translation Modes............................................................................................... 331Addressing Modes .............................................................................................................. 331Data Types............................................................................................................................ 331Register Set Summary......................................................................................................... 332PPC405 Organization.......................................................................................................... 334

Chapter 2: Operational ConceptsExecution Model .................................................................................................................... 341Synchronization Operations ............................................................................................ 342

Context Synchronization .................................................................................................... 342Execution Synchronization ................................................................................................ 342Storage Synchronization..................................................................................................... 343

Processor Operating Modes.............................................................................................. 343Privileged Mode .................................................................................................................. 343User Mode ............................................................................................................................ 344

Memory Organization......................................................................................................... 344Effective-Address Calculation........................................................................................... 344Physical Memory................................................................................................................. 345Virtual Memory ................................................................................................................... 345

Memory Management ......................................................................................................... 345Addressing Modes .............................................................................................................. 346

Operand Conventions ......................................................................................................... 347Byte Ordering....................................................................................................................... 349Operand Alignment ............................................................................................................ 353

Instruction Conventions .................................................................................................... 354



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Instruction Forms ................................................................................................................ 354Instruction Classes .............................................................................................................. 355PowerPC Book-E Instruction Classes ............................................................................... 357

Chapter 3: User Programming ModelUser Registers ......................................................................................................................... 359

Special-Purpose Registers (SPRs)...................................................................................... 360General-Purpose Registers (GPRs) ................................................................................... 360Condition Register (CR) ..................................................................................................... 361Fixed-Point Exception Register (XER).............................................................................. 363Link Register (LR) ............................................................................................................... 363Count Register (CTR).......................................................................................................... 364User-SPR General-Purpose Register................................................................................. 364SPR General-Purpose Registers......................................................................................... 365Time-Base Registers ............................................................................................................ 365

Exception Summary ............................................................................................................. 366Branch and Flow-Control Instructions ........................................................................ 367

Conditional Branch Control............................................................................................... 367Branch Instructions ............................................................................................................. 368Branch Prediction ................................................................................................................ 370Branch-Target Address Calculation ................................................................................. 372Condition-Register Logical Instructions .......................................................................... 376System Call ........................................................................................................................... 376System Trap.......................................................................................................................... 377

Integer Load and Store Instructions ............................................................................. 378Operand-Address Calculation........................................................................................... 378Load Instructions................................................................................................................. 381Store Instructions................................................................................................................. 384Load and Store with Byte-Reverse Instructions.............................................................. 385Load and Store Multiple Instructions............................................................................... 386Load and Store String Instructions ................................................................................... 387

Integer Instructions .............................................................................................................. 389Arithmetic Instructions....................................................................................................... 390Logical Instructions............................................................................................................. 395Compare Instructions ......................................................................................................... 398Rotate Instructions .............................................................................................................. 399Shift Instructions.................................................................................................................. 403

Multiply-Accumulate Instruction-Set Extensions.................................................. 405Modulo and Saturating Arithmetic .................................................................................. 405Multiply-Accumulate Instructions ................................................................................... 406Negative Multiply-Accumulate Instructions .................................................................. 413Multiply Halfword to Word Instructions ........................................................................ 419

Floating-Point Emulation .................................................................................................. 422Processor-Control Instructions........................................................................................ 422

Condition-Register Move Instructions............................................................................. 423Special-Purpose Register Instructions.............................................................................. 424

Synchronizing Instructions .............................................................................................. 424Implementation of eieio and sync Instructions.............................................................. 425Synchronization Effects of PowerPC Instructions.......................................................... 425Semaphore Synchronization .............................................................................................. 426

Memory-Control Instructions.......................................................................................... 427



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Chapter 4: PPC405 Privileged-Mode Programming ModelPrivileged Registers ............................................................................................................. 429

Special-Purpose Registers .................................................................................................. 431Machine-State Register ....................................................................................................... 431SPR General-Purpose Registers......................................................................................... 432Processor-Version Register ................................................................................................ 433Device Control Registers .................................................................................................... 434

Privileged Instructions........................................................................................................ 434System Linkage.................................................................................................................... 434Processor-Control Instructions.......................................................................................... 435

Processor Wait State ............................................................................................................. 436

Chapter 5: Memory-System ManagementMemory-System Organization ........................................................................................ 437

Memory-System Features .................................................................................................. 438Cache Organization............................................................................................................. 438Instruction-Cache Operation ............................................................................................. 441Data-Cache Operation ........................................................................................................ 443Data-Cache Performance.................................................................................................... 445

Accessing Memory................................................................................................................ 447Memory Coherency............................................................................................................. 448Atomic Memory Access...................................................................................................... 448Ordering Memory Accesses............................................................................................... 448Preventing Inappropriate Speculative Accesses............................................................. 449

Memory-System Control.................................................................................................... 451Storage Attributes................................................................................................................ 451Storage-Attribute Control Registers ................................................................................. 452

Cache Control.......................................................................................................................... 456Cache Instructions............................................................................................................... 456Core-Configuration Register.............................................................................................. 459

Software Management of Cache Coherency ............................................................. 463How Coherency is Lost ...................................................................................................... 463Enforcing Coherency With Software................................................................................ 465Self-Modifying Code........................................................................................................... 467

Cache Debugging .................................................................................................................. 468icread Instruction ................................................................................................................ 468dcread Instruction ............................................................................................................... 469

Chapter 6: Virtual-Memory ManagementReal Mode ................................................................................................................................. 471Virtual Mode ........................................................................................................................... 472

Process-ID Register ............................................................................................................. 474Page-Translation Table ....................................................................................................... 474

Translation Look-Aside Buffer ....................................................................................... 475TLB Entries ........................................................................................................................... 476TLB Access............................................................................................................................ 479TLB-Access Failures ............................................................................................................ 480

Virtual-Mode Access Protection ..................................................................................... 482TLB Access-Protection Controls........................................................................................ 482Zone Protection.................................................................................................................... 482Effect of Access Protection on Cache-Control Instructions........................................... 483



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UTLB Management .............................................................................................................. 485Recording Page Access and Page Modification....................................................... 486Maintaining Shadow-TLB Consistency ...................................................................... 487

Chapter 7: Exceptions and InterruptsOverview ................................................................................................................................... 489

Synchronous and Asynchronous Exceptions.................................................................. 490Precise and Imprecise Interrupts ...................................................................................... 490Partially-Executed Instructions ......................................................................................... 490

PPC405D5 Exceptions and Interrupts .......................................................................... 491Critical and Noncritical Exceptions .................................................................................. 492Transferring Control to Interrupt Handlers .................................................................... 492Returning from Interrupt Handlers.................................................................................. 494Simultaneous Exceptions and Interrupt Priority............................................................ 495Persistent Exceptions and Interrupt Masking................................................................. 496

Interrupt-Handling Registers .......................................................................................... 497Machine-State Register Following an Interrupt.............................................................. 497Save/Restore Registers 0 and 1 ......................................................................................... 498Save/Restore Registers 2 and 3 ......................................................................................... 499Exception-Vector Prefix Register ...................................................................................... 500Exception-Syndrome Register ........................................................................................... 500Data Exception-Address Register ..................................................................................... 502

Interrupt Reference .............................................................................................................. 502Critical-Input Interrupt (0x0100) ....................................................................................... 503Machine-Check Interrupt (0x0200) ................................................................................... 504Data-Storage Interrupt (0x0300) ........................................................................................ 506Instruction-Storage Interrupt (0x0400) ............................................................................. 508External Interrupt (0x0500) ................................................................................................ 509Alignment Interrupt (0x0600) ............................................................................................ 510Program Interrupt (0x0700) ............................................................................................... 511FPU-Unavailable Interrupt (0x0800)................................................................................. 513System-Call Interrupt (0x0C00)......................................................................................... 514APU-Unavailable Interrupt (0x0F20) ............................................................................... 515Programmable-Interval Timer Interrupt (0x1000).......................................................... 516Fixed-Interval Timer Interrupt (0x1010) .......................................................................... 517Watchdog-Timer Interrupt (0x1020)................................................................................. 518Data TLB-Miss Interrupt (0x1100)..................................................................................... 519Instruction TLB-Miss Interrupt (0x1200).......................................................................... 520Debug Interrupt (0x2000) ................................................................................................... 521

Chapter 8: Timer ResourcesTime Base .................................................................................................................................. 524

Reading and Writing the Time Base................................................................................. 525Computing Time of Day..................................................................................................... 526

Timer-Event Registers......................................................................................................... 527Programmable-Interval Timer Register ........................................................................... 527Timer-Control Register....................................................................................................... 528Timer-Status Register.......................................................................................................... 529

Timer-Event Interrupts ....................................................................................................... 529Watchdog-Timer Events..................................................................................................... 530Programmable-Interval Timer Events.............................................................................. 532Fixed-Interval Timer Events .............................................................................................. 533



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Chapter 9: DebuggingDebug Modes .......................................................................................................................... 536

Internal-Debug Mode ......................................................................................................... 536External-Debug Mode......................................................................................................... 536Debug-Wait Mode............................................................................................................... 537Real-Time Trace-Debug Mode .......................................................................................... 537

Debug Registers..................................................................................................................... 537Debug-Control Registers .................................................................................................... 538Debug-Status Register ........................................................................................................ 541Instruction Address-Compare Registers.......................................................................... 542Data Address-Compare Registers..................................................................................... 543Data Value-Compare Registers ......................................................................................... 543

Debug Events .......................................................................................................................... 543Instruction-Complete Debug Event.................................................................................. 545Branch-Taken Debug Event ............................................................................................... 546Exception-Taken Debug Event .......................................................................................... 546Trap-Instruction Debug Event........................................................................................... 546Unconditional Debug Event .............................................................................................. 547Instruction Address-Compare Debug Event................................................................... 547Data Address-Compare Debug Event.............................................................................. 549Data Value-Compare Debug Event .................................................................................. 553Imprecise Debug Event ...................................................................................................... 556Freezing the Timers............................................................................................................. 556

Debug Interface...................................................................................................................... 557JTAG Debug Port................................................................................................................. 557JTAG Connector .................................................................................................................. 557BSDL...................................................................................................................................... 559

Chapter 10: Reset and InitializationReset ............................................................................................................................................ 561

Processor State After Reset ................................................................................................ 561First Instruction...................................................................................................................... 563Initialization ............................................................................................................................ 563

Sample Initialization Code................................................................................................. 565

Chapter 11: Instruction SetInstruction Encoding ........................................................................................................... 570

Split-Field Notation............................................................................................................. 571Alphabetical Instruction Listing .................................................................................... 571

Appendix A: Register SummaryRegister Cross-Reference ................................................................................................... 767General-Purpose Registers................................................................................................ 768Machine-State Register and Condition Register..................................................... 770Special-Purpose Registers ................................................................................................. 770Time-Base Registers ............................................................................................................. 775Device Control Registers ................................................................................................... 775

Appendix B: Instruction SummaryInstructions Sorted by Mnemonic ................................................................................. 777



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Instructions Sorted by Opcode ....................................................................................... 781Instructions Grouped by Function ................................................................................ 786Instructions Grouped by Form........................................................................................ 792Instruction Set Information .............................................................................................. 797List of Mnemonics and Simplified Mnemonics ..................................................... 802

Appendix C: Simplified MnemonicsBranch Instructions .............................................................................................................. 821

True/False Conditional Branches..................................................................................... 821Comparison Conditional Branches................................................................................... 824Branch Prediction ................................................................................................................ 827

Compare Instructions .......................................................................................................... 828CR-Logical Instructions...................................................................................................... 828Rotate and Shift Instructions ........................................................................................... 829Special-Purpose Registers ................................................................................................. 830Subtract Instructions............................................................................................................ 831TLB-Management Instructions ....................................................................................... 832Trap Instructions ................................................................................................................... 832Other Simplified Mnemonics.......................................................................................... 834

No Operation ....................................................................................................................... 834Load Immediate................................................................................................................... 834Load Address ....................................................................................................................... 834Move Register ...................................................................................................................... 834Complement Register ......................................................................................................... 834Move to Condition Register............................................................................................... 835

Appendix D: Programming ConsiderationsSynchronization Examples................................................................................................ 837

Fetch and No-Op ................................................................................................................. 838Fetch and Store .................................................................................................................... 838Fetch and Add...................................................................................................................... 838Fetch and AND .................................................................................................................... 838Test and Set .......................................................................................................................... 838Compare and Swap............................................................................................................. 839Lock Acquisition and Release............................................................................................ 839List Insertion ........................................................................................................................ 840

Multiple-Precision Shifts .................................................................................................. 840Code Optimization Guidelines....................................................................................... 842

Conditional Branches.......................................................................................................... 842Floating-Point Emulation ................................................................................................... 843Cache Usage ......................................................................................................................... 843Alignment............................................................................................................................. 844

Instruction Performance..................................................................................................... 844General Rules ....................................................................................................................... 844Branches................................................................................................................................ 844Multiplies.............................................................................................................................. 845Scalar Load Instructions ..................................................................................................... 846Scalar Store Instructions ..................................................................................................... 847String and Multiple Instructions ....................................................................................... 847Instruction Cache Misses.................................................................................................... 848



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Appendix E: PowerPC® 6xx/7xx CompatibilityRegisters .................................................................................................................................... 849

Machine-State Register ....................................................................................................... 851Processor-Version Register ................................................................................................ 852

Memory Management ......................................................................................................... 852Memory Translation ........................................................................................................... 852Memory Protection ............................................................................................................. 853Memory Attributes.............................................................................................................. 853

Cache Management .............................................................................................................. 854Exceptions ................................................................................................................................. 854Timer Resources..................................................................................................................... 855Other Differences.................................................................................................................. 856

Instructions........................................................................................................................... 856Endian Support.................................................................................................................... 856Debug Resources ................................................................................................................. 856Power Management ............................................................................................................ 856

Appendix F: PowerPC® Book-E CompatibilityRegisters .................................................................................................................................... 857

Machine-State Register ....................................................................................................... 859Processor-Version Register ................................................................................................ 860

Memory Management ......................................................................................................... 860Memory Translation ........................................................................................................... 860Memory Protection ............................................................................................................. 861Memory Attributes.............................................................................................................. 861

Caches ......................................................................................................................................... 862Memory Synchronization .................................................................................................. 862Exceptions ................................................................................................................................. 862Timer Resources..................................................................................................................... 864Other Differences.................................................................................................................. 864

Instructions........................................................................................................................... 864Debug Resources ................................................................................................................. 864

Index ...................................................................................................................................................... 865

Volume 2(b): PPC405 Processor Block Manual

About This BookDocument Organization..................................................................................................... 873Document Conventions...................................................................................................... 873

General Conventions .......................................................................................................... 873Registers .................................................................................................................................... 874Terms .......................................................................................................................................... 874Additional Reading .............................................................................................................. 877

Chapter 1: Introduction to the PowerPC® 405 ProcessorPowerPC Architecture ......................................................................................................... 879



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PowerPC Embedded-Environment Architecture ........................................................... 880PPC405 Software Features ................................................................................................. 882

Privilege Modes ................................................................................................................... 884Address Translation Modes............................................................................................... 884Addressing Modes .............................................................................................................. 884Data Types............................................................................................................................ 884Register Set Summary......................................................................................................... 885

PPC405 Hardware Organization..................................................................................... 887Central-Processing Unit...................................................................................................... 888Exception Handling Logic.................................................................................................. 889Memory Management Unit ............................................................................................... 889Instruction and Data Caches.............................................................................................. 890Timer Resources .................................................................................................................. 890Debug .................................................................................................................................... 891PPC405 Interfaces ................................................................................................................ 891

PPC405 Performance ............................................................................................................ 892

Chapter 2: Input/Output InterfacesSignal Naming Conventions ............................................................................................ 896Clock and Power Management Interface ................................................................... 897

CPM Interface I/O Signal Summary ................................................................................ 897CPM Interface I/O Signal Descriptions ........................................................................... 898

CPU Control Interface ......................................................................................................... 901CPU Control Interface I/O Signal Summary .................................................................. 901CPU Control Interface I/O Signal Descriptions ............................................................. 901

Reset Interface ........................................................................................................................ 903Reset Requirements............................................................................................................. 903Reset Interface I/O Signal Summary................................................................................ 904Reset Interface I/O Signal Descriptions........................................................................... 904

Instruction-Side Processor Local Bus Interface ....................................................... 907Instruction-Side PLB Operation ........................................................................................ 907Instruction-Side PLB I/O Signal Table............................................................................. 909Instruction-Side PLB Interface I/O Signal Descriptions ............................................... 910Instruction-Side PLB Interface Timing Diagrams........................................................... 918

Data-Side Processor Local Bus Interface .................................................................... 929Data-Side PLB Operation ................................................................................................... 929Data-Side PLB Interface I/O Signal Table ....................................................................... 931Data-Side PLB Interface I/O Signal Descriptions........................................................... 933Data-Side PLB Interface Timing Diagrams...................................................................... 944

Device-Control Register Interface ................................................................................. 958DCR Interface I/O Signal Summary ................................................................................ 960DCR Interface I/O Signal Descriptions............................................................................ 961DCR Interface Timing Diagrams....................................................................................... 963

External Interrupt Controller Interface ....................................................................... 968EIC Interface I/O Signal Summary .................................................................................. 968EIC Interface I/O Signal Descriptions.............................................................................. 968

JTAG Interface........................................................................................................................ 970JTAG Interface I/O Signal Table....................................................................................... 971JTAG Interface I/O Signal Descriptions .......................................................................... 972

Debug Interface...................................................................................................................... 975Debug Interface I/O Signal Summary ............................................................................. 975Debug Interface I/O Signal Descriptions ........................................................................ 975

Trace Interface ........................................................................................................................ 978



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Trace Interface Signal Summary ....................................................................................... 978Trace Interface I/O Signal Descriptions .......................................................................... 979

Additional FPGA Specific Signals ................................................................................ 981Additional FPGA I/O Signal Descriptions...................................................................... 981

Chapter 3: PowerPC® 405 OCM ControllerIntroduction ............................................................................................................................. 983Functional Features .............................................................................................................. 983

Common Features ............................................................................................................... 983Data-Side OCM (DSOCM) ................................................................................................. 984Instruction-Side OCM (ISOCM)........................................................................................ 984

OCM Controller Operation .............................................................................................. 984Operational Summary ........................................................................................................ 984DSOCM Ports....................................................................................................................... 985DSOCM Attributes .............................................................................................................. 986ISOCM Ports ........................................................................................................................ 987ISOCM Attributes................................................................................................................ 989

Timing Specification ........................................................................................................... 990Single-Cycle Mode .............................................................................................................. 990Multi-Cycle Mode ............................................................................................................... 991

Programmer’s Model ........................................................................................................... 992DCR Registers ...................................................................................................................... 992

References................................................................................................................................. 994Application Notes ................................................................................................................. 994

Interfacing to Block RAM................................................................................................... 994Size vs. Performance ........................................................................................................... 994Application Example .......................................................................................................... 995

Appendix A: RISCWatch and RISCTrace InterfacesRISCWatch Interface ......................................................................................................... 1003RISCTrace Interface ........................................................................................................... 1005

Signal Summary....................................................................................................................... 1007

Index .................................................................................................................................................... 1013

Volume 3: Rocket I/O™ Transceiver User Guide

Chapter 1: IntroductionRocket I/O Features ............................................................................................................ 1019In This User Guide ............................................................................................................. 1019Naming Conventions......................................................................................................... 1020For More Information........................................................................................................ 1020Further Reading ................................................................................................................... 1020

Documentation Provided by Xilinx ................................................................................ 1020IBM® CoreConnect™ Documentation ........................................................................... 1021Software Development Documentation......................................................................... 1021



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Chapter 2: Rocket I/O™ Transceiver OverviewBasic Architecture and Capabilities............................................................................ 1023Clock Synthesizer ............................................................................................................... 1025Clock and Data Recovery................................................................................................. 1026Transmitter ............................................................................................................................. 1026

FPGA Transmit Interface.................................................................................................. 10268B/10B Encoder................................................................................................................. 1026Disparity Control............................................................................................................... 1026Transmit FIFO.................................................................................................................... 1027Serializer ............................................................................................................................. 1027

Receiver.................................................................................................................................... 1027Deserializer......................................................................................................................... 1027Receiver Termination........................................................................................................ 10288B/10B Decoder................................................................................................................. 1028

Loopback ................................................................................................................................. 1028Elastic and Transmitter Buffers .................................................................................... 1029

Receiver Buffer................................................................................................................... 1029Clock Correction................................................................................................................ 1029Channel Bonding............................................................................................................... 1030Transmitter Buffer ............................................................................................................. 1031

CRC............................................................................................................................................ 1031Reset/Power Down ............................................................................................................. 1031

Chapter 3: Digital Design ConsiderationsList of Available Ports....................................................................................................... 1033Primitive Attributes ........................................................................................................... 1037Modifiable Primitives ....................................................................................................... 1042Byte Mapping........................................................................................................................ 1046Clocking................................................................................................................................... 1046

Clock Signals ...................................................................................................................... 1046Clock Ratio ......................................................................................................................... 1047Digital Clock Manager (DCM) Examples ...................................................................... 1047Multiplexed Clocking Scheme......................................................................................... 1057Clock Dependency ............................................................................................................ 1058

Resets ........................................................................................................................................ 1061Rocket I/O Transceiver Instantiations ....................................................................... 1062PLL Operation and Clock Recovery............................................................................ 1062

Clock Correction Count.................................................................................................... 1063RX_LOSS_OF_SYNC_FSM .............................................................................................. 10638B/10B Operation.............................................................................................................. 1064Vitesse Disparity Example ............................................................................................... 1066

Status Signals ........................................................................................................................ 10678B/10B Encoding .................................................................................................................. 1067

8B/10B Serial Output Format.......................................................................................... 1076CRC Operation ..................................................................................................................... 1077

CRC Generation................................................................................................................. 1077CRC Latency....................................................................................................................... 1078CRC Limitations ................................................................................................................ 1078CRC Modes......................................................................................................................... 1078

Channel Bonding (Channel-to-Channel Alignment) ......................................... 1080



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Chapter 4: Analog Design ConsiderationsSerial I/O Description ....................................................................................................... 1083Pre-emphasis Techniques................................................................................................ 1084Differential Receiver ......................................................................................................... 1087Jitter ........................................................................................................................................... 1087

Total Jitter (DJ + RJ)........................................................................................................... 1087Clock and Data Recovery................................................................................................. 1087PCB Design Requirements ............................................................................................. 1089

Power Filtering .................................................................................................................. 1089High-Speed Serial Trace Design...................................................................................... 1091

Power Consumption .......................................................................................................... 1094Reference Clock ................................................................................................................... 1094

Chapter 5: Simulation and ImplementationSimulation Models ............................................................................................................. 1095

Smart Model....................................................................................................................... 1095HSPICE ............................................................................................................................... 1095Behavioral........................................................................................................................... 1095

Implementation Tools....................................................................................................... 1095Synthesis ............................................................................................................................. 1095Par........................................................................................................................................ 1095UCF Example ..................................................................................................................... 1096Implementing Clock Schemes ......................................................................................... 1096

Diagnostic Signals .............................................................................................................. 1097LOOPBACK ....................................................................................................................... 1097

Appendix A: Rocket I/O™ Cell ModelsSummary ................................................................................................................................. 1099Verilog Module Declarations ........................................................................................ 1099

GT_AURORA_1................................................................................................................. 1099GT_AURORA_2................................................................................................................. 1100GT_AURORA_4................................................................................................................. 1101GT_CUSTOM..................................................................................................................... 1102GT_ETHERNET_1............................................................................................................. 1103GT_ETHERNET_2............................................................................................................. 1103GT_ETHERNET_4............................................................................................................. 1104GT_FIBRE_CHAN_1......................................................................................................... 1105GT_FIBRE_CHAN_2......................................................................................................... 1106GT_FIBRE_CHAN_4......................................................................................................... 1107GT_INFINIBAND_1 ......................................................................................................... 1108GT_INFINIBAND_2 ......................................................................................................... 1108GT_INFINIBAND_4 ......................................................................................................... 1109GT_XAUI_1 ........................................................................................................................ 1110GT_XAUI_2 ........................................................................................................................ 1111GT_XAUI_4 ........................................................................................................................ 1112



Volume 1: Virtex-II Pro™ Platform FPGA Advance Product Specification

Data Sheet Module 1:Virtex-II Pro™ Platform FPGAs: Introduction and Overview

Figure 1: Virtex-II Pro Ordering Information ......................................................................... 45

Data Sheet Module 2:Virtex-II Pro™ Platform FPGAs: Functional Description

Figure 1: Virtex-II Pro Generic Architecture Overview ........................................................ 47Figure 2: Rocket I/O Block Diagram ......................................................................................... 49Figure 3: Clock Correction in Receiver .................................................................................... 52Figure 4: Channel Bonding (Alignment) ................................................................................. 52Figure 5: Processor Block Architecture..................................................................................... 54Figure 6: CoreConnect Block Diagram..................................................................................... 56Figure 7: PPC405 Core Block Diagram ..................................................................................... 57Figure 8: Relationship of Timer Facilities to Base Clock ..................................................... 59Figure 9: Virtex-II Pro Input/Output Tile ................................................................................ 60Figure 10: Virtex-II Pro IOB Block ............................................................................................ 61Figure 11: Double Data Rate Registers .................................................................................... 62Figure 12: Register / Latch Configuration in an IOB Block ................................................. 63Figure 13: LVCMOS SelectI/O Standard ................................................................................. 63Figure 14: SSTL or HSTL SelectI/O Standards ....................................................................... 64Figure 15: Virtex-II Pro I/O Banks: Top View for Wire-Bond Packages

(CS, FG, and BG) ...................................................................................................................... 65Figure 16: Virtex-II Pro I/O Banks: Top View for Flip-Chip Packages (FF and BF)........ 65Figure 17: DCI in a Virtex-II Pro Bank ..................................................................................... 66Figure 18: Internal Series Termination .................................................................................... 66Figure 19: DCI Usage Examples................................................................................................. 67Figure 20: Virtex-II Pro CLB Element ....................................................................................... 68Figure 21: Virtex-II Pro Slice Configuration ........................................................................... 68Figure 22: Virtex-II Pro Slice (Top Half) .................................................................................. 69Figure 23: Register / Latch Configuration in a Slice .............................................................. 70Figure 24: Distributed SelectRAM (RAM16x1S).................................................................... 71Figure 25: Single-Port Distributed SelectRAM (RAM32x1S) .............................................. 71Figure 26: Dual-Port Distributed SelectRAM (RAM16x1D) ................................................ 71Figure 27: Shift Register Configurations ................................................................................. 72Figure 28: Cascadable Shift Register ........................................................................................ 72

Schedule of Figures



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Figure 29: MUXF5 and MUXFX multiplexers ......................................................................... 73Figure 30: Fast Carry Logic Path ................................................................................................ 74Figure 31: Horizontal Cascade Chain ....................................................................................... 75Figure 32: Wide-Input AND Gate (16 Inputs)......................................................................... 75Figure 33: Virtex-II Pro 3-State Buffers .................................................................................... 76Figure 34: 3-State Buffer Connection to Horizontal Lines ................................................... 76Figure 35: 18 Kb Block SelectRAM Memory in Single-Port Mode .................................... 77Figure 36: 18 Kb Block SelectRAM in Dual-Port Mode........................................................ 78Figure 37: WRITE_FIRST Mode ................................................................................................ 79Figure 38: READ_FIRST Mode.................................................................................................. 79Figure 39: NO_CHANGE Mode ............................................................................................... 79Figure 40: XC2VP4 Block RAM Column Layout .................................................................... 80Figure 41: SelectRAM and Multiplier Blocks ......................................................

Documents

Virtex-II Pro Platform FPGA Documentationebook.pldworld.com/_Semiconductors/XILINX/DataSource CD... · 2002-02-26 · R Virtex-II Pro™ Platform FPGA Documentation • Advance Product