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COA Question Bank Ms. Vincy Joseph

Class: SE CMPNA&B

Subject: Computer Architecture and Organization

Module V

1. What are the major requirements for an I/O module? (06 Marks)

The major requirements for an I/O module fall into following categories:

1. Control and Timing2. Processor Communication3. Device Communication4. Data Buffering5. Error detection

Control and Timing

It is used to co-ordinate the flow of traffic between internal resources (processor/memory) and external devicesExample:The control of transfer of data from an external device to processor involves the following steps:

1. Processor checks the status of the device 2. I/O Module returns the device status 3. If the device is ready to transmit, the processor requests the data4. I/O module obtains data from external device5. Data is transferred from I/O module to processor

Processor Communication

It involves

(a) Command Decoding : I/O modules accepts command from processor (send as signals on control bus).E.g. for a disk drive : read sector, write sector


(b) Data : data is exchanged between processor and I/O module over data bus

(c) Status Reporting : The device reports its status (READY/BUSY) to the processor

(d) Address Recognition : Each I/O device has a unique address and I/O module must recognize the address

Device Communication

The I/O module must be able to perform device communication which involves commands, status and data

Data Buffering

It is needed as there is a speed mismatch in data transfer for memory, processor and external devices. Thus data is buffered in I/O module for the slower devices

Error Detection

I/O module reports error to processor. The error can be:

Mechanical errors (e.g. paper jam in printer) Changes in bit pattern of transmitted data (can be detected by

parity bits)2. Explain in brief Programmed I/O (04 Marks)3. Write short note on programmed I/O (06 Marks)

If an I/O operation is completely controlled by the processor, then the system is programmed I/O

The processor initiates, direct and terminates I/O operations It is the responsibility of the processor to periodically check the

status of I/O until the operation is complete. The overall operation of programmed I/O is


When the processor encounters an instruction related to I/O operation, it issues a command to appropriate I/O module. The I/O module will perform the requested action (READ/WRITE) and set appropriate bits in I/O status register. The processor periodically checks the status of I/O module to find that the operation is incomplete.

Advantage

Simple to implement Requires less hardware or software

Disadvantage

CPU is slowed to the speed of the peripheral (Busy Waiting) Inefficient : As CPU must periodically poll the module to check its

status (ties up CPU for long period with no useful work)4. Write short note on Interrupt Driven I/O (06 Marks)

Interrupt I/O is a way of controlling input/output activity whereby a peripheral or terminal that needs to make or receive a data transfer sends a signal. This will cause a program interrupt to be set. At a time appropriate to the priority level of the I/O interrupt, the processor enters an interrupt service routine.

For input, the device interrupts the CPU when new data has arrived and is ready to be retrieved by the system processor.For output, the device delivers an interrupt either when it is ready to accept new data or to acknowledge a successful data transfer.

The CPU can work continuously on a task without checking the input devices, allowing the devices themselves to interrupt it as necessary.

The action for the input is as follows:


1. The processor issues a READ command. It then goes off and then do something else

2. At the end of each instruction cycle, the processor checks for interrupts.

3. When the interrupt from the I/O module occurs, the processor saves the context of current program and reads the word of data from I/O module and stores it in memory.

4. It then restores the context of the program it was working on and resumes execution


Advantages

1. fast2. efficient

Disadvantages

1. can be tricky to write if using a low level language2. can be tough to get various pieces to work well together3. usually done by the hardware manufacturer / OS maker, e.g.

Microsoft5. Write short note on DMA (05 Marks)6. What is the need of DMA? Explain its various techniques of data

transfer. (10 Marks)7. Explain DMA based data transfer technique for I/O devices (10

Marks)

The software controlled data transfer (Programmed I/O and Interrupt Driven I/O) requires processor to execute a series of instructions to carry out data transfer. This consumes more processing time which can be better utilized for other processing tasks. The major drawbacks of software controlled data transfer are

1. I/O Transfer Rate is limited by CPU speed to test and service a device

2. More time is spend on data transferTo overcome these drawbacks, DMA is used

In this technique, an external device is used to control data transfer. This device termed DMA controller generates address and control signals required to control data transfer and allows peripheral device to directly access memory.


When a processor wishes to read or write a block of data, it issues a command to DMA module with the following information:

1. Whether a read or write is requested 2. Address of the I/O device involved3. The starting location in memory to read from or write to4. The number of words to be read or written

The processor then continues with other work. The DMA module transfers the data between I/O and memory. When the transfer is complete, DMA module sends an interrupt signal to the processor. Thus the processor is involved only at the beginning and end of the transfer.

DMA Channel

For performing the above functions, the basic blocks required in a DMA channel are Data Counter, Data Register, Address Register and Control Logic.

Data Counter: It stores the number of data transfers to be done in one DMA cycle. It automatically decrements after each word transfer.

Data Register: It acts as a buffer

Address Register: It initially holds the starting address of the device. It stores the address of the next word to be transferred. It is automatically decremented and incremented after each word transfer.

After each transfer the data counter is tested for zero. When the data count reaches zero, the DMA transfer halts

Data Transfer Modes

DMA Controller transfers the data in one of the following three modes:

1. Single Transfer Mode (Cycle Stealing Mode)2. Block Transfer Mode


3. Demand or Burst Transfer ModeSingle Transfer Mode

In this mode device can make only one transfer in one cycle. The DMA must release and re-acquire the bus for each word transfer. This is commonly-used by devices that cannot transfer the entire block of data immediately. The peripheral will request the DMA each time it is ready for another transfer. The floppy disk controller only has a one-byte buffer, so it uses this mode.


Block Transfer Mode

In this mode, once the DMA acquires the system bus, an entire block of data is transferred. Once a Block transfer is started, it runs until the transfer count reaches zero.


Demand Transfer Mode

In this mode, data words are transferred as long as the device is ready for transfer (DREQ signal remains active) and Terminal Count is not reached.


8. Compare Interrupt Driven I/O and DMA (10 Marks)

Interrupt I/O is a way of controlling input/output activity whereby a peripheral or terminal that needs to make or receive a data transfer sends a signal. This will cause a program interrupt to be set. At a time appropriate to the priority level of the I/O interrupt, the processor enters an interrupt service routine.

For input, the device interrupts the CPU when new data has arrived and is ready to be retrieved by the system processor.For output, the device delivers an interrupt either when it is ready to accept new data or to acknowledge a successful data transfer.

The CPU can work continuously on a task without checking the input devices, allowing the devices themselves to interrupt it as necessary.

The action for the input is as follows:

1. The processor issues a READ command. It then goes off and then do something else

2. At the end of each instruction cycle, the processor checks for interrupts.

3. When the interrupt from the I/O module occurs, the processor saves the context of current program and reads the word of data from I/O module and stores it in memory.

4. It then restores the context of the program it was working on and resumes execution


Advantages

1. fast2. efficient

Disadvantages

1. can be tricky to write if using a low level language2. can be tough to get various pieces to work well together3. usually done by the hardware manufacturer / OS maker, e.g.

Microsoft


DMA

The software controlled data transfer (Programmed I/O and Interrupt Driven I/O) requires processor to execute a series of instructions to carry out data transfer. This consumes more processing time which can be better utilized for other processing tasks. The major drawbacks of software controlled data transfer are

1. I/O Transfer Rate is limited by CPU speed to test and service a device

2. More time is spend on data transfer

To overcome these drawbacks, DMA is used

In this technique, an external device is used to control data transfer. This device termed DMA controller generates address and control signals required to control data transfer and allows peripheral device to directly access memory.

When a processor wishes to read or write a block of data, it issues a command to DMA module with the following information:

1. Whether a read or write is requested 2. Address of the I/O device involved3. The starting location in memory to read from or write to4. The number of words to be read or written

The processor then continues with other work. The DMA module transfers the data between I/O and memory. When the transfer is complete, DMA module sends an interrupt signal to the processor. Thus the processor is involved only at the beginning and end of the transfer.

DMA Channel


For performing the above functions, the basic blocks required in a DMA channel are Data Counter, Data Register, Address Register and Control Logic.

Data Counter: It stores the number of data transfers to be done in one DMA cycle. It automatically decrements after each word transfer.

Data Register: It acts as a buffer

Address Register: It initially holds the starting address of the device. It stores the address of the next word to be transferred. It is automatically decremented and incremented after each word transfer.

After each transfer the data counter is tested for zero. When the data count reaches zero, the DMA transfer halts

9. What is bus arbitration? Explain its techniques. (10 Marks)10. What is bus arbitration? Explain any two techniques. (10 Marks)

The device that is allowed to initiate data transfers on the bus at any given time is called the bus master. In a computer system there may be more than one bus master such as processor, DMA controller etc.They share the system bus. When current master relinquishes control of the bus, another bus master can acquire the control of the bus.

Bus arbitration is the process by which the next device to become the bus master is selected and bus mastership is transferred to it. The selection of bus master is usually done on the priority basis.

There are two approaches to bus arbitration: Centralized and distributed.

Centralized Arbitration

In centralized bus arbitration, a single bus arbiter performs the required arbitration. The bus arbiter may be a processor or a separate controller


connected to the bus. There are three different arbitration schemes that use the centralized bus arbitration approach. These schemes are:a. Daisy chainingb. Polling methodc. Independent requestDaisy chaining

The system connections for Daisy chaining method are as follows.

It is a simple method. All masters make use of the same line for bus request. In response to the bus request the controller sends a bus grant if the bus is free. The bus grant signal serially propagates through each master until it encounters the first one that is requesting access to the bus. This master blocks the propagation of the bus grant signal, activates the busy line and gains control of the bus. Therefore any other requesting module will not receive the grant signal and hence cannot get the bus access.

Advantages

It is simple and cheaper method It requires least number of lines and this number is independent of

the number of masters in the system

Disadvantages


Propagation delay of the bus grant signal is proportional to the number of bus masters. This makes arbitration slow.

The priority of the master is fixed by its physical location Failure of one master causes the whole system to fail.

Polling method

In this method, the controller generates the addresses for the masters. Number of address line required depends on the number of master connected in the system. For example, if there are 8 masters connected in the system, at least three address lines are required. In response to the bus request, the controller generates a sequence of master addresses. When the requesting master recognizes its address, it activates the busy line and begins to use the bus.

Advantages

The priority can be changed by altering the polling sequence stored in the controller

If one module fails, the entire system does not fail.

Independent Request


In this scheme each master has a separate pair of bus request and bus grant lines and each pair has a priority assigned to it. The built in priority decoder within the controller selects the highest priority request and asserts the corresponding bus grant signal.

Advantage:

Separate pairs of bus request and grant signals makes arbitration fast

Disadvantage:

It requires more bus request and grant lines.

Distributed Arbitration

In distributed arbitration, all devices participate in the selection of the next bus master. In this scheme each device on the bus is assigned a 4-bit identification number.


The number of devices connected on the bus when one or more devices request for the control of bus, they assert the start-arbitration signal and place their 4-bit ID numbers on arbitration lines, ARB0 through ARB3.

These four arbitration lines are all open-collector. Therefore, more than one device can place their 4-bit ID number to indicate that they need the control of bus. If one device puts 1 on the bus line and another device puts 0 on the same bus line, the bus line status will be 0. Device reads the status of all lines through inverter buffers so device reads bus status 0 as logic 1. Scheme the device having highest ID number has highest priority.

When two or more devices place their ID number on bus lines then it is necessary to identify the highest ID number from the status of bus line. Consider that two devices A and B, having ID number 1 and 6, respectively are requesting the use of the bus.

Device A puts the bit pattern 0001, and device B puts the bit pattern 0110. With this combination the status of bus-line will be 1000; however because of inverter buffers code seen by both devices is 0111.


Each device compares the code formed on the arbitration line to its own ID, starting from the most significant bit. If it finds the difference at any bit position, it disables its drives at that bit position and for all lower-order bits.

It does so by placing a 0 at the input of their drive. In our example, device A detects a difference on line ARB2 and hence it disables its drives on line ARB2, ARB1 and ARB0. This causes the code on the arbitration lines to change to 0110. This means that device B has won the race.

The decentralized arbitration offers high reliability because operation of the bus is not dependent on any single device.

11. Write short note on Scanner (07 Marks)

Scanners transform printed material and photographs into digital representations. Most scanners use a flat-bed arrangement, in which the page being scanned is placed over a flat glass surface. A source of light scans the page, and the reflected light is focused on a linear array of charge coupled devices (CCDs). When a CCD device is exposed to light, an electrical charge is stored in a tiny capacitor associated with it such that the amount of charge is proportional to the intensity of light. This charge is collected by appropriate circuitry and converted to a digital representation using an analog to digital converter. For color scanners, red green and blue filters are used to separate the primary colors and process them separately. As the light source moves across the page, the sensor array is read repeatedly, thus sampling the successive lines of pixels of image. After scanning the image is represented in memory as an array of pixels.

12. Write short note on Joysticks (06 Marks)


Joystick is a short pivoted stick that can be moved by hand to point in any direction in the X-Y plane. When this information is sent to the computer, the software moves the cursor on the screen in the same direction.

The position of the stick can be sensed by a suitable linear or angular position transducer, such as the potentiometer arrangement. The voltage outputs of the X and Y potentiometers are fed to two analog-to-digital convertors , whose outputs determine the position of the joystick and thus the desired direction of motion

Joysticks are widely used in video games. For use in video games, the joystick is shaped into a handle that suits the nature of the game. It is usually equipped with push buttons to be used for shooting a ball or firing a gun.

13. Write short note on Plotter (05 Marks)

A plotter is a printer that interprets commands from a computer to make line drawings on paper with one or more automated pens. Unlike a regular printer, the plotter can draw continuous point-to-point lines directly from vector graphics files or commands. There are different


types of plotters: a drum plotter draws on paper wrapped around a drum which turns to produce one direction of the plot, while the pens move to provide the other direction; a flatbed plotter draws on paper placed on a flat surface; and an electrostatic plotter draws on negatively charged paper with positively charged toner.

Plotters were the first type of printer that could print with color and render graphics and full-size engineering drawings. Plotters are much more expensive than printers. They are most frequently used for CAE (computer-aided engineering) applications, such as CAD (computer-aided design) and CAM (computer-aided manufacturing). Hewlett-Packard is the leading vendor of plotters worldwide.

14. Write short note on Touchpad (07 Marks)

The touchpad is a small pad made of pressure sensitive material. When the user’s finger touches some point on the pad, the pressure causes the electrical characteristics of the material at that spot. The location of the spot is detected and communicated to the computer. By moving a finger across the pad, the user can instruct the software to move the cursor on the screen in the same direction. This makes touchpad a low cost replacement for the mouse, with high degree of robustness and reliability because it contains no moving parts.

The most innovative material for implementing touchpad is the one that has a large number of optical fibers embedded in it. The material can identify the location of an object touching it as well as the amount of pressure being applied. This material was developed for robotic applications in space.

A touchpad can be combined with a liquid crystal display to produce a touch sensitive screen that can be used for both input and output operations.


15. Explain in brief memory mapped I/O (05Marks)Memory mapped I/O is an interfacing technique in which memory related instructions are used for data transfer and the device is identified by a 16-bit address. In this type, the I/O devices are treated as memory locations. The control signals used are MEMR and MEMW. The interfacing between I/O and microprocessor will be same as single memory location. For data transfer between I/O device and microprocessor, microprocessor will send address, generate control signals MEMR and MEMW.In MEMR, it accepts data from I/O device while in MEMW it transfers data to I/O device. With memory-mapped I/O, there is a single address space for memory locations and I/O devices. The processor treats the status and data registers of I/O modules as memory locations and uses the same machine instructions to access both memory and I/O devices.Advantage large stock of instructions can be used, allowing more efficient

programming. Memory related instructions are available such as LDA, STA.

Disadvantage

Valuable memory address space is used up.

Decoding 16-bits requires more hardware.16. Explain in brief function of 8089 I/O processor (04 Marks)

1. I/O operations which previously required large amounts of CPU supervision and therefore limited its data processing time can now be independently managed and maintained by an I/O processor like 8089.

2. The 8089 and its host processor communicate through messages placed in blocks of shared memory.


3. The 8089 has two independent I/O channels that operate concurrently. Each channel has a separate set of registers and individual external interrupt, DMA request and external terminate pins.

4. If any I/O operation does not complete successfully, the channel takes corrective action, signaling the host processor when the I/O operation is completed or error correction routines have finished executing.

5. A task block program, written in 8089 Assembly Language, is executed for each channel. Task block programs manage and control the I/O operations performed by an I/O channel.

Documents

Web viewThe DMA must release and re-acquire the bus for each word ... Bus arbitration is the process by which the next device to become the bus master is selected and