Victor P. Nelson Computer-Aided Design of ASICs Concept to
Silicon
Slide 2
ASIC Design Flow Behavioral Model VHDL/Verilog Gate-Level
Netlist Transistor-Level Netlist Physical Layout Map/Place/Route
DFT/BIST & ATPG Verify Function Verify Function Verify Function
& Timing Verify Timing DRC & LVS Verification IC Mask
Data/FPGA Configuration File Standard Cell IC & FPGA/CPLD
Synthesis Test vectors Full-custom IC Front-End Design Back-End
Design
Slide 3
ASIC CAD tools available in ECE Modeling and Simulation
Modelsim, ADVance MS/Questa, Eldo, Mach TA/ADiT (Mentor Graphics)
Verilog-XL, NC_Verilog, Spectre (Cadence) Design Synthesis
(digital) Leonardo Spectrum, Precision RTL (Mentor Graphics) Design
Compiler (Synopsys), RTL Compiler (Cadence) Design for Test and
Automatic Test Pattern Generation DFT Advisor, Fastscan, Flextest
(Mentor Graphics) Schematic Capture & Design Integration Design
Architect-IC (Mentor Graphics) Design Framework II (DFII) -
Composer (Cadence) Physical Layout IC Station (Mentor Graphics) SOC
Encounter, Virtuoso (Cadence) Design Verification Calibre (Mentor
Graphics) Diva, Assura (Cadence)
Slide 4
Mentor Graphics Analog/Mixed-Signal IC Design Flow
Slide 5
Mentor Graphics CAD Tools (select from eda list in user-setup
on the Sun network) ICFlow** For custom & standard cell IC
designs IC flow tools (Design Architect-IC, IC Station, Calibre)
Digital/analog/mixed simulation (Modelsim,ADVance MS,Eldo,MachTA)
HDL Synthesis (Leonardo) ASIC Design Kit (ADK)** Support files for
various technologies DFT ATPG/DFT/BIST tools (DFT Advisor,
Flextest, Fastscan) Modelsim ** (HDL Simulation) FPGA (FPGA
Advantage, Modelsim, Leonardo) *Xilinx/ISE (Xilinx FPGA/CPLD - back
end design) *QuartusII (Altera FPGA/CPLD - back end design)
*Ims/6.2 (IMS chip tester) ** Installed on both Solaris and Linux
servers * Vendor-Provided (Not Mentor Graphics) Tools
Slide 6
Mentor Graphics ASIC Design Kit (ADK) Technology files &
standard cell libraries AMI: ami12, ami05 (1.2, 0.5 m) TSMC:
tsmc035, tsmc025, tsmc018 (0.35, 0.25, 0.18 m) IC flow & DFT
tool support files: Simulation VHDL/Verilog/Mixed-Signal models
(Modelsim SE/ADVance MS) Analog (SPICE) models (Eldo/Accusim)
Post-layout timing (Mach TA) Digital schematic (Quicksim II,
Quicksim Pro) (except tsmc025,tsmc018) Synthesis to standard cells
(LeonardoSpectrum) Design for test & ATPG (DFT Advisor,
Flextest/Fastscan) Schematic capture (Design Architect-IC) IC
physical design (standard cell & custom) Floorplan, place &
route (IC Station) Design rule check, layout vs schematic,
parameter extraction (Calibre) We also have ADKs for Cadence tools
for several technologies
Slide 7
Xilinx/Altera FPGA/CPLD Design Tools Simulate designs in
Modelsim Behavioral models (VHDL,Verilog) Synthesized netlists
(VHDL, Verilog) Requires primitives library for the target
technology Synthesize netlist from behavioral model Leonardo
(Levels 1,2,3) has libraries for most FPGAs (ASIC-only version
currently installed) Xilinx ISE has its own synthesis tool Vendor
tools for back-end design Map, place, route, configure device,
timing analysis, generate timing models Xilinx Integrated Software
Environment (ISE) Altera Quartus II & Max+Plus2 Higher level
tools for system design & management Mentor Graphics FPGA
Advantage Xilinx Platform Studio : SoC design, IP management, HW/SW
codesign
Slide 8
Behavioral Design & Verification Create Behavioral/RTL HDL
Model(s) Simulate to Verify Functionality Synthesize Circuit
Synopsys - Design Compiler Leonardo Spectrum, Xilinx ISE (digital)
Modelsim (digital) VHDL-AMS Verilog-A ADVance MS (analog/mixed
signal) VHDL Verilog SystemC Technology Libraries
Technology-Specific Netlist to Back-End Tools Simulate to Verify
Function/Timing VITAL Library Design Constraints
Slide 9
ADVance MS Digital, Analog, Mixed-Signal Simulation ADVance MS
Working Library Design_1 Design_2 VITAL IEEE 1164 Resource
Libraries Simulation Setup EZwave or Xelga Input Stimuli
VHDL,Verilog, VHDL-AMS, Verilog-A, SPICE Netlists Eldo, Eldo RF
Modelsim View Results Mach TA Mach PA Analog (SPICE) Digital
(VHDL,Verilog) Mixed Signal (VHDL-AMS, Verilog-A) SPICE models
Xilinx SIMPRIMS
Slide 10
ADVance MS : mixed-signal simulation A/D converter digital
analog VHDL-AMS
Slide 11
ADVance MS: mixed Verilog-SPICE SPICE subcircuit Verilog top
(test bench)
Slide 12
Questa ADMS (replaces ADVance MS) Four simulation engines
integrated for SoC designs Questa VHDL/Verilog/SystemC digital
simulation Eldo analog (SPICE) simulation ADiT accelerated
transistor-level (Fast-SPICE) simulation (replaces Mach TA) Eldo RF
Engines and languages can be mixed in a simulation IEEE 1497
Standard Delay File Format (SDF) IEEE 1076.1 VHDL-AMS IEEE 1076
VHDL IEEE 1364 Verilog IEEE 1800 SystemVerilog IEEE 1666 SystemC
Accellera standard Verilog-AMS Language SPICE Eldo, HSPICE, and
Spectre dialects.
Slide 13
Questa ADMS
Slide 14
Example: 4-bit binary counter VHDL model (count4.vhd) VHDL
model Create working library: vlib work vmap work work Compile:
vcom count4.vhd Simulate: vsim count4(rtl) ModelSim
simulation-control inputs ModelSim Macro (count4_rtl.do) ModelSim
Macro OR, VHDL testbench ModelSim results listing or waveform
listingwaveform
Slide 15
-- count4.vhd 4-bit parallel-load synchronous counter LIBRARY
ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all;
--synthesis libraries ENTITY count4 IS PORT
(clock,clear,enable,load_count : IN STD_LOGIC; D: IN unsigned(3
downto 0); Q: OUT unsigned(3 downto 0)); END count4; ARCHITECTURE
rtl OF count4 IS SIGNAL int : unsigned(3 downto 0); BEGIN
PROCESS(clear, clock, enable) BEGIN IF (clear = '1') THEN int
tpd_A0_Y, PathCondition => TRUE ), 1 => ( InputChangeTime
=> A1_ipd'LAST_EVENT, PathDelay => tpd_A1_Y, PathCondition
=> TRUE ) ), GlitchData => GlitchData_Y, Mode => OnDetect,
MsgOn => TRUE, Xon => TRUE, MsgSeverity => WARNING
Determine delay along each input-output path"> INT_RES_0, Paths
=> ( 0 => ( InputChange" title="VITAL Model (3) -- PATH DELAY
SECTION -- VitalPathDelay01Z ( OutSignal => Y, OutSignalName
=> "Y", OutTemp => INT_RES_0, Paths => ( 0 => (
InputChange">
Design for test & test generation Consider test during the
design phase Test design more difficult after design frozen Basic
steps: Design for test (DFT) insert test points, scan chains, etc.
to improve testability Insert built-in self-test (BIST) circuits
Generate test patterns (ATPG) Determine fault coverage (Fault
Simulation)
ASIC DFT Flow Insert Internal Scan Circuitry Generate/Verify
Test Vectors Synthesized VHDL/Verilog Netlist adk.atpg ATPG Library
DFT Advisor Fastscan/ Flextest VHDL/Verilog Netlist With Scan
Elements Test Pattern File
Slide 34
Example DFTadvisor session Invoke: dftadvisor verilog count4.v
lib $ADK/technology/adk.atpg Implement scan with defaults: (full
scan, mux-DFF scan elements) set system mode setup analyze control
signals auto set system mode dft run insert test logic write
netlist count4_scan.v verilog write atpg setup count4_scan (creates
count4_scan.dofile for ATPG in Fastscan)
Slide 35
count4 without scan design
Slide 36
count4 scan inserted by DFTadvisor
Slide 37
ATPG with FastScan (full-scan circuit) Invoke: fastscan verilog
count4.v lib $ADK/technology/adk.atpg Generate test pattern file in
FastScan: dofile count4_scan.dofile (defines scan path &
procedure) ** set system mode atpg create patterns auto (generate
test patterns) save patterns ** count4_scan.dofile was created by
DFTadvisor
Slide 38
Test file: scan chain definition and load/unload procedures
scan_group "grp1" = scan_chain "chain1" = scan_in = "/scan_in1";
scan_out = "/output[3]"; length = 4; end; procedure shift
"grp1_load_shift" = force_sci "chain1" 0; force "/clock" 1 20;
force "/clock" 0 30; period 40; end; procedure shift
"grp1_unload_shift" = measure_sco "chain1" 10; force "/clock" 1 20;
force "/clock" 0 30; period 40; end; procedure load "grp1_load" =
force "/clear" 0 0; force "/clock" 0 0; force "/scan_en" 1 0; apply
"grp1_load_shift" 4 40; end; procedure unload "grp1_unload" = force
"/clear" 0 0; force "/clock" 0 0; force "/scan_en" 1 0; apply
"grp1_unload_shift" 4 40; end;
ASIC Physical Design (Standard Cell) (can also do full custom
layout) Floorplan Chip/Block Place & Route Std. Cells
Component-Level Netlist (EDDM format) IC Mask Data Design Rule
Check Std. Cell Layouts Mentor Graphics IC Station (adk_ic) Mach
TA/Eldo Simulation Model Backannotate Schematic Generate Mask Data
Layout vs. Schematic Check Design Rules Process Data Libraries
Calibre ICblocks
Slide 41
Cell-Based IC I/O pads
Slide 42
Cell-Based Block
Slide 43
Source: Weste CMOS VLSI Design Basic standard Cell layout
Slide 44
Preparation for Layout 1. Use Design Architect-IC to convert
Verilog netlist to Mentor Graphics EDDM netlist format Invoke
Design Architect-IC (adk_daic) On menu bar, select File > Import
Verilog Netlist file: count4.v (the Verilog netlist) Output
directory: count4 (for the EDDM netlist) Mapping file
$ADK/technology/adk_map.vmp 2. Open the generated schematic for
viewing Click Schematic in DA-IC palette Select schematic in
directory named above (see next slide) Click Update LVS in the
schematic palette to create a netlist to be used later by Calibre
3. Create design viewpoints for ICstation tools adk_dve count4 t
tsmc035 (V.Ps: layout, lvs, sdl, tsmc035) Can also create
gate/transistor schematics directly in DA-IC using components from
the ADK library
Slide 45
DA-IC generated schematic
Slide 46
Eldo simulation from DA-IC Run simulations from within DA-IC
Eldo, ADVance MS, Mach TA DA-IC invokes a netlister to create a
circuit model from the schematic SPICE model for Eldo & Mach TA
Eldo analyses, forces, probes, etc. same as SPICE View results in
EZwave
Slide 47
Eldo input and output files -Netlist -Simulation cmds
-Stimulus
Slide 48
SPICE netlist for modulo7 counterSPICE circuit file generated
by DA-IC Force values (created interactively) From ADK library
Slide 49
Force functions (1) DC value Vsigname A 0 DC 5 Value (volts)
Between circuit nodes A and GND (node 0) V indicates voltage Force
name
Slide 50
Force functions (2) Pulse/square wave Vsigname B 0 pulse 0 5 0
0.1N 0.1N 20N 40N Initial Voltage v1 Pulsed Voltage v2 Delay from
start of period for waveform to begin - td Rise Fall time tr tf
Pulse Period width tp tw v1 v2 td tr tw tf Nodes tp
Slide 51
Force functions (3) Pattern wave (for logic 0 & 1 values)
Vname B 0 pattern 5 0 5n 0.1n 0.1n 10n 011010 R Logic 1 & 0
voltages Between circuit Nodes B & GND (node 0) Bit pattern
Repeat the pattern (optional) Delay to waveform begin Rise &
Fall Time between changes Duration of bit value 0 11 0 1 0 delay
pattern
Slide 52
Eldo simulation of modulo7 counter (transient analysis)
Slide 53
Create a std-cell based logic block in IC Station Invoke:
adk_ic In IC Station palette, select: Create Cell Cell name: count4
Attach cell library: $ADK/technology/ic/process/tsmc035 Process
data: $ADK/technology/ic/process/tsmc035 Design rules:
$ADK/technology/ic/process/tsmc035.rules Angle mode: 45 Cell type:
block Select With connectivity (use imported schematic) EDDM
schematic viewpoint: count4/layout Logic loading options: flat
Slide 54
Create Cell dialog box
Slide 55
Auto-floorplan the block place & route > autofp
Slide 56
Auto-place the std cells Autoplc > StdCel
Slide 57
Auto-place ports ( signal connections on cell boundaries)
Autoplc > Ports
Slide 58
AutoRoute all nets (hand-route any unrouted overflows) Then:
Add > Port Text to copy port names from schematic for
Calibre
Slide 59
Layout design rule check (DRC) Technology-specific design rules
specify minimum sizes, spacing, etc. of features to ensure reliable
fabrication Design rules file specified at startup Ex.
tsmc035.rules From main palette, select ICrules Click Check and
then OK in prompt box (can optionally select a specific area to
check) Rules checked in numeric order
Slide 60
Common errors detected by DRC To fix, click on First in palette
to highlight first error Error is highlighted in the layout Click
View to zoom in to the error (see next) Example: DRC9_2: Metal2
spacing = 3L Fix by drawing a rectangle of metal2 to fill in the
gap between contacts that should be connected Click Next to go to
next error, until all are fixed NOTE: There can be no DRC errors if
MOSIS is to fabricate the chip they will run their own DRC.
Slide 61
Sample error: DRC9_2 metal2 spacing = 3L Draw rectangle of
metal2 to fill gap It also called contact-to-contact metal 2
spacing DRC9_2 error
Slide 62
Layout vs schematic check using Calibre Interactive LVS Compare
extracted transistor-level netlist against netlist saved in DA-IC
From ICstation menu: Calibre > Run LVS In popup, Calibre
location: $MGC_HOME/../Calibre Rules:
$ADK/technology/ic/process/tsmc035.calibre.rules Input:
count4.src.net (previously created in DA-IC) H-cells:
$ADK/technology/adk.hcell (hierarchical cells) Extracted file:
count4.lay.net
Slide 63
Post-layout parameter extraction via Calibre Interactive PEX
Extract Spice netlist, including parasitic RC Simulate in Eldo or
MachTA ICstation menu: Calibre>Run PEX Options similar to
Calibre LVS Extraction options: lumped C + coupling caps
distributed RC distributed RC + coupling caps Output file:
count4.pex.netlist
Slide 64
Post-layout simulation with MachTA MachTA is an accelerated
Spice simulator Digital & mixed-signal circuits Analyze timing
effects pre- and post-layout SPICE netlists with parasitic R/C
Execute test vector file to verify functionality Algorithms support
large designs Partition design, simulate only partitions with
changes Combine time-driven & event-driven operation Solves
linearized models using a proprietary high-performance,
graph-theory based, matrix solution algorithm
Slide 65
Mach TA flow diagram SPICE netlist
$ADK/technology/mta/tsmc035
Slide 66
Prepare Calibre-extracted netlist for Mach TA
(file.pex.netlist) In file.pex.netlist, insert model definitions
and VDD/GND voltage source functions after comment header: * File:
m7.pex.netlist * Created: Thu Nov 15 15:25:56 2007 * Program
"Calibre xRC" * Version "v2005.2_9.14".model n nmos.model p pmos
Vvdd VDD 0 5 Vgnd GND 0 0 Delete (or comment out with * in 1 st
column).subcircuit statement and any continuation lines (for long
statement): *.subckt modulo7 CLK Q[1] CLEARBAR I[1] Q[0] I[0] Q[2]
*+ L_CBAR I[2] GND VDD Change.ends to.END near end of file
Slide 67
Post-layout simulation with Mach TA Invoke Mach TA: ana -
command file to initialize Anacad SW mta ezw t
$ADK/technology/mta/tsmc035 count4.sp Other options: -do file
(execute commands from file.do instead of design.spdo -donot (run
without simulating compile only) -b (run in batch mode no GUI
output to console) Transistor calibration files for this technology
Generate waveform database & display in EZwave Netlist,
modified as on previous slide
Slide 68
Sample Mach TA dofile (transient analysis) plot v(clk) v(q[2])
v(q[1]) v(q[0]) measure rising TRIG v(clk) VAL=2.5v RISE=1 TARG
v(q[0]) VAL=2.5v l load l reset h count l clk run 5 ns h reset h
clk run 5 ns l clk run 5 ns h clk run 5 ns Signals to observe in
EZwave Measure time from rising edge of clk (TRIGger) to 1st rising
edge of q[0] (TARGet) - voltages Drive signals low/high (Lsim
format) Simulate for 5 ns Command to execute: dofile file.do
Slide 69
EZwave waveform viewer (results for previous dofile)
Double-click signal name to display.
Slide 70
Alternative Mach TA dofile (same result as previous example)
plot v(clk) v(q[2]) v(q[1]) v(q[0]) measure rising TRIG v(clk)
VAL=2.5v RISE=1 TARG v(q[0]) VAL=2.5v vpulse Vclk clk 0 pulse(0 3.3
10n.05n.05n 10n 20n) l load l reset h count run 5 ns h reset run
200 ns Voltage source name Nodes to which source connected v-levels
delay rise fall width period Periodic pulses
Slide 71
Mach TA test vector file Verify design functionality/behavior
apply test vectors capture outputs compare outputs to expected
result use vectors/outputs from behavioral simulation Command to
execute a test vector file: run tvend tvfile.tv test vector file
(next slide)
Slide 72
Test vector file format # Test vector file for modulo7 counter
CODEFILE UNITS ps RISE_TIME 50 FALL_TIME 50 INPUTS
clk,reset,load,count,i[2],i[1],i[0]; OUTPUTS q[2] (to=max),q[1]
(to=max),q[0] (to=max); CODING(ROM) RADIX 3; @0 X; @2000 0; @7000
0; @10000 5; @20000 5; @30000 6; @40000 6; @50000 0; @60000 0; ..
END Header Vectors: @time expected_output Sample 5 fs before next
vector signal order within vectors Test vectors derived from
behavioral simulation results Vector format
Slide 73
Behavioral simulation listing Corresponding Mach TA test vector
file
Slide 74
Alternate test vector file (clock generated separately by
voltage source) vpulse vclk clk 0 pulse(0 3.3 10n.5n.5n 10n 20n)
Can mix other simulation commands with test vector
application.
Slide 75
Mach TA has been replaced by ADiT Fast-SPICE simulator Analog
& mixed-signal 10X to 100X faster than other SPICE simulators
Integrated with Questa
Slide 76
Top level layout design flow** Create a symbol for each core
block (adk_daic) Create a chip-level schematic from core blocks and
pads (adk_daic) Generate design viewpoints (adk_dve) Create a
layout cell for the chip(adk_ic) Place core logic blocks from the
schematic Generate a pad frame Move/alter core blocks to simplify
routing Route pads to core blocks Design rule check & fix
problems Generate mask data ** Refer to on-line tutorials by Yan/Xu
and by Dixit/Poladia
Slide 77
Chip-level schematic (1) Generate a symbol for each core logic
block In DA-IC, open the schematic (eg. modulo7) Select:
Miscellaneous > Generate Symbol Add phy_comp property to the
symbol Select the body of the symbol From the popup menu:
Properties > Add Enter property name: phy_comp Enter property
value: mod7b (layout cell name for the block created in IC Station)
Check & save Example on next slide
Slide 78
Symbol with phy_comp property Layout cell is mod7b for logic
schematic modulo7
Slide 79
Chip-level schematic (2) In DA-IC, create a schematic for the
chip Instantiate core blocks Menu pallete: Add > Instance Select
and place generated symbol Add pads from ADK Library>Std.
Cells>Pads >tsmc035 : In, Out, BiDir, VDD, GND Wire pads to
logic blocks and connectors Assign pin numbers, if known Change pad
instance name to PINdd (dd = 2-digit pin #) Check & save Create
design viewpoints with adk_dve Example on next slide
Slide 80
Assigning PAD pin numbers Change instance name property on pads
to PINxx xx = 2-digit pin number (01 40 for Tiny Chip package)
Place pad on chip pin 01 Default instance names
Slide 81
Top-level schematic for modulo7 chip Hierarchical connectors on
Pad pins Wire block I/O pins to pad signal pins VDD/GND Pads Core
block Instance name = PINxx (chip pin #)
Slide 82
Chip layout Start IC Station (adk_ic) & create a new layout
cell enter cell name logic source is layout viewpoint of chip
schematic same library, process file, rules file, and options as
standard cell layout Open the schematic ADK Edit menu: Logic Source
> Open In the schematic, select all core cells (but not pads)
Place the cells: Place > Inst Generate the pad frame Top menu
bar: ADK > Generate Padframe > tsmc035
Slide 83
Chip layout (2) Move, rotate, flip core logic cells as desired
to make routing easier BUT - DO NOT EDIT OR MOVE PAD CELLS
Autoroute all connections Select autoroute all on P&R menu
Click options on prompt bar, and unselect Expand Channels (prevents
pads from being moved) Add missing VDD/GND wires, if necessary
Autorouter might only route 1 VDD/GND wire, even if multiple
VDD/GND pads Manually add others: Objects>Add>Path VDD/GND
net width = 50 VDD/GND net vias = 6x6 (copy an existing via)