Because very-high-speed ICs are in the early stages of development,this discussion focuses on the technological challenges of

scaling to smaller dimensions.

VHSICSystemsandTechnologyD. F. BarbeOffice of theAssistant Secretary of the Navy

The principal objective of the VHSIC thrust-basedon 20 years of industrial, academic, and military ex-perience-is to insert very-high-speed integrated circuitsinto defense systems. To achieve this objective, certaintechnological barriers must be overcome and subsystemsmust be built to demonstrate the improved capability.These subsystems, along with the technological chal-lenges, are discussed in this article.

Tablel.Progress in IC development.

LEVEL OF NUMBER OF LOGICINTEGRATION GATES CHIP

SMALL-SCALE INTEGRATION 3-30MEDIUM-SCALE INTEGRATION 30-300LARGE-SCALE INTEGRATION 300-3000VERY-LARGE-SCALE INTEGRATION > 3000

TIME PERIOD OFDEVELOPMENT

EARLY 1960'sMID-LATE 1960'sEARLY-MID 1970'sBEYOND LATE 1970's

IC Progress. From 1959-when the first integrated cir-cuit contained a few transistors per chip-until the pres-ent time, the density of IC components has increased atthe rate of a factor of two per year (see Table 1). Thehighest density per chip has been achieved in memory be-cause of its very regular structure. Since logic or signalprocessing functions require more random interconnec-tions, the levels of density and rates of increase have beensomewhat less-but, nevertheless, quite remarkable-inlogic chips. This rapid increase in circuit density is due inpart to the rapid decrease in circuit dimensions; im-provements in optical lithography and chip fabricationhave yielded circuits with dimensions in the 2.5- to5.0-micrometer range (Figure 1).

Throughput capacity. A parameter adopted to describethe signal processing capacity of very-high-speed ICs,throughput capacity is the product of the number of gateson an IC chip times the clock frequency in Hertz, so theunits are gate Hertz (the clock period is taken to be fourgate delays).

Figure 2 shows the throughput capacity for several sys-tems. Microprocessors have throughput rates on theorder of 1010, voice processors and the global positioning

Figure 1. Minimum feature size as a function of time from 1960 to 1980and beyond.

0018-9162/81/0200-0013$00.75 1981 IEEEFebruary 1981 13

satellite processor have throughput rates on the order of101 i, the AIM-54 phoenix seeker processor and the UYK20 standard computer have throughput rates on the orderof 1012. JTIDS, the joint tactical information distributionsystem, has a throughput rate between 1012 and 1013, andthe Navy sonar, the BQQ-5, has a throughput rate on.theorder of 10'4. These are throughput rates for systemscomposed, in most cases, of many chips. Cost, weight,and power dissipation are high, and reliability tends to bea problem because of numerous interconnections be-tween chips. As a result, there is great incentive for fab-ricating chips with more and more signal processing capa-bility-that is, chips with higher throughput capacity.

Table 2 lists projected throughput needs for severalsystems. As points of reference for ICs, chip throughputrates on the order of 1010 can be achieved with 5-micro-meter technology, and chip throughput rates between 1012and l0'3 are projected with I-micrometer technology.'The power dissipation and weight of systems having

various throughput rates are a strong function of featuresize (Figure 3). For example, a system requiring 2 x 1013gate Hz and using 5-micrometer IC technology could beexpected to weigh slightly more than 1000 kg and dissipateover 100 watts. The same system capability based on1-micrometer technology could be expected to weighabout 10 kg and dissipate about one watt. Thus, very largereductions in power dissipation and system weight can beachieved by concentrating on the reduction of IC featuresize.

Defense systems. Several observations can be maderegarding defense systems. First, their complexity andhigh life-cycle costs prevent us from fielding the desirednumber of systems. Second, performance require-ments-for example, very-high throughput rates-tend tobe different from those of the commercial sector. Third,the defense environment is different. The environmentexperienced by a signal processor on the deck of aship-where it may be subjected to transmission fromradar, for example-is very different from that of mostcommercial systems. Fourth, defense applications tend torequire custom ICs. This is due to the fact that the budgetfor weight, power dissipation, and size on defense plat-forms tends to be very restricted, and space, power, andweight can be saved by designing custom chips specificallyto do the job that is needed. Fifth, the leverage of defensein the IC market is not nearly as great as it used to be. Theabsolute defense need has remained essentially constantwhile the commercial market has increased greatly,thereby reducing, in relative terms, the military's marketleverage.

Finally, we must improve defense-system logistics. Thisincludes the need for built-in tests and for systems withbetter fault-toleranrce, reliability, and repairability.System complexity, coupled with the decreasein trainedtechnical personnel, clearly indicates that we should vec-tor toward systems which are inherently more reliable.Also, built-in test techniques indicating fault location, sothat technicians without a great deal of training could ef-fect repairs in an efficient manner, would be highlyuseful.

Figure 2. Performance of several systems on a plot of clock frequencyvs. number of gates, with throughput capacity as a parameter.

Table 2.Defense IC throughput needs.

APPLICATION

COMMAND, CONTROL, AND COMMUNICATIONSRADARELECTRONIC WARFAREIMAGE PROCESSORSCOMPUTERSANTISUBMARINE WARFARE

THROUGHPUT RATES(GATE Hz)

10131014

,o14101310131014 Figure 3. Power and weight of IC assemblies vs. IC feature

size, with throughput rate as a parameter.

COMPUTER14

The VHSIC program

Approach. The VHSIC program2 is an IC technologyeffort driven by a systems approach-that is, thetechnology is pushed in the direction dictated by systemsneeds for the mid-1980's and beyond. As shown in Figure4, systems requirements drive the development of systemsbrassboards which then impact design, architecture, soft-ware, and test technology. They, in turn, guide fabrica-tion, lithography, and CAD development, culminating inproduction lines which provide the ICs to meet systemsrequirements.

Planned program outputs include (1) a family of chipsto perform the most commonly occurring signal pro-

cessing functions across systems in the three military ser-

vices; (2) higher-order computer-aided-design techniquesfor efficient design of very complex ICs in terms of time,cost, and manpower; (3) pilot production lines to manu-facture the family of chips as well as custom chips; and (4)systems brassboards to demonstrate VHSIC capabilities.

Thus, the overall objective of the VHSIC program isthe direct development of militarized, advanced ICs forintroduction into future military systems in a timely, af-fordable manner. Expected benefits include advancedmilitary capability, high return on investment includinglife-cycle costs, and increasing the lead in military ICs byseveral years. The program expects not only to advanceIC technology (measured in terms of computationalspeed and size, weight, and power requirements), but alsoto achieve this advance directly in militarized circuits withhigh reliability, ease of testability and diagnosis, and hightolerance to military stress environments. Each phase ofthe VHSIC program is intended to play a specific role inreaching these objectives.

Schedule. The VHSIC program is divided conceptuallyinto four phases: Phases 0, 1, 11, and 111. Phase 0, 1, and 11will be carried out consecutively, but Phase III will be car-

ried out in parallel with the other three. The program

began in March 1980 and is scheduled to continue into1986.Phase 0 is a study phase to define the necessary work,

the detailed approach, and the plans for achieving theultimate objectives of the VHSIC program. This analysisproceeds in a top-down fashion, starting with the selec-tion and analysis of at least three projected militarysystems or subsystems to determine their signal and data-processing requirements and to identify broadly ap-

plicable VHSIC chips.In Phase 0, architectures and design approaches will be

selected and investigated to implement VHSIC chips with1.25-micrometer and submicrometer minimum featuresizes using a minimum clock rate of 25 MHz and pro-

viding a minimum functional throughput of 5 x IO I gateHz per cm2 for the 1.25-micrometer features and ap-

proximately 1013 gate Hz per cm2 for the submicrometerfeatures. In addition, chip technology and processingtechniques, including device technologies, interconnects,and metallizations appropriate for both feature sizes, willbe studied along with chip fabrication and manufacturingtechniques. The studies will also cover packaging trade-offs, CAD techniques, and lithographic requirements

February 1981

and techniques-all necessary to achieve the overallVHSIC program goals. In addition, susceptibility to ther-mal stress over the full military temperature range from- 550C to + 1250C, to radiation doses to 104 rads (Si), toelectromagnetic interference, and to other environmentalfactors met in military applications will be considered.Phase I is subdivided into two parallel efforts. Using

1.25-micrometer IC technology, Phase Ia is directedtoward developing complete electronic brassboard sub-systems within about three years. These brassboards mayconsist of several VHSIC chips operating at a minimumclock rate of 25 MHz. It is anticipated that a pilotproduction-line capability will be established for thistechnology. Minimum requirements of reliability, test-ability, and environmental immunity will be demanded.Phase lb will consist of initial efforts to extend IC tech-

nology to submicrometer feature sizes and correspondingcircuit complexities. This will include high-resolutionlithography and replication techniques, submicrometerdevice design and modeling, substrate and epitaxialgrowth improvements and analysis, metallization reliabil-ity and interconnect analysis, appropriate CAD tech-niques, and architecture and systems considerations. Afeature of both Phases la and lb will be design fortestability and fault location.

Similarly, Phase II is divided into two parallel pro-grams. Phase Ila will provide- subsystem demonstrationsbased on Phase la brassboards, and Phase Ilb will con-tinue the Phase lb submicrometer development effort.Phases lb and llb are directed at developing all aspects ofIC technology necessary to cross the so-called one-micro-meter barrier, considered to be the practical limit of con-ventional optical lithography. The end goal of these ef-forts is the development of production capability for ad-vanced chips. This includes not only lithography andfabrication but also design, architecture, software, andtesting technologies. Subsystem demonstrations of Phasellb technology are expected at the end of the program orshortly thereafter through extensions or other funding.The Phase III VHSIC support program runs parallel

with the main program efforts. Whereas the Phase I andII program contracts are expected to be large, verticallyintegrated efforts with each contractor covering all

Figure 4. The VHSIC program is driven by systems requirements.

15

aspects of VHSIC development, Phase III will consist ofmany smaller, shorter-term efforts in key technologyareas designed to feed into the main program. Part of themotivation for establishing Phase III was to permit andencourage the participation of universities and smallbusinesses in the program. Phase III efforts will focus onhigh-resolution lithographic equipment and processingtechnology; advanced architecture and design conceptsfor reducing custom fabrication; increasing chip utiliza-tion and system reliability through fault-tolerance andimproving system-testability through on-chip testing; ad-vanced CAD techniques; improved silicon materials andfabrication processes; analytical methods for determina-tion of substrate and fabrication-induced defects at thesubmicrometer level; methods for improving radiation,thermal, and mechanical stress tolerance; establishmentof design standards and interface requirements; newdevice, gate, and circuit structures; and techniques fordocumentation and methods for improved and simplifiedutilization and testing.

Candidate systems brassboards

The systems demonstration units-that is, the brass-boards-are the initial mechanism by which VHSIC tech-nology will be transferred into operational equipment.For discussion, the 20 candidate brassboard systems3 in-cluded in the VHSIC program are classified in six categor-ies: (1) command, control, and communications, (2)radar, (3) electronic warfare, (4) image processing, (5)general-purpose computers, and (6) antisubmarine war-fare (see Figure 5).

Command, control, and communications. There arefour candidate brassboard systems in the command, con-trol, and communications category.

JTIDS (Air Force). The joint tactical informationdistribution system is an Air Force/Navy program todevelop a family of terminals and interfaces for inte-

grated communications, navigation, and identification intactical and air defense operations. Initial implementa-tion of JTIDS is planned in 1982 using the Air Force'sE-3A airborne warning and control system and F-15 andF-16 fighters, as well as Navy ships and aircraft. Eventual-ly, it will be linked with the Army's proposed battlefieldinformation distribution system. The JTIDS network isintended to connect many different types of weaponssystems, dispersed over a wide area, with sources ofsurveillance, intelligence, and support information,weapon controllers, and decision-making commanders.The system architecture is based on time division multipleaccess enhanced with an advanced TDMA for time slotaccessing modes and multinet operations. Basiccapabilities are derived through the use of spread-spectrum TDMA technology, and signal transmission isat microwave frequencies using cryptographic encodingfor security. The role of the VHSIC components will be toprovide modules which perform one or more of thevarious processing functions. This will simplify system in-tegration through a standard interface.

BIDS (Army). The battlefield information distribu-tion system is the Army's equivalent of JTIDS. TheArmyis in the process of developing a new generation ofautomated fire control, comand and control, air defense,and intelligence gathering systems that require real-time,jam-resistant information distribution among a largenumber of users. The subsystem modules using VHSICcomponents will employ advanced signal processing andspread-spectrum modulation at rates greater than 100MHz with appropriate error control. The modules in-clude a single chip for speech processing at rates as low asfeasible and, in Army terminology, a universal program-mable frequency synthesizer, in addition to an all-digitalintermediate-frequency signal processor operating atrates of 200-300 MHz.

Anti-jam modem (Navy). A VHSIC chip set is beingsought to replace the specialized modems of the past andeliminate costly redesign. The ideal all-purpose modem

Figure 5. Candidate VHSIC systems brassboards.

COMPUTER16

would stress programmability so that the same circuitrycould serve many different sets of data modulationschemes (AM, FM, SSB, FSK, PN, etc.), frequency-hop-ping rates, and spread-spectrum formats by simplychanging the microprogram in a read-only memory. Theresulting hardware is to be a black box add-on to existingcommunications systems and will be compatible with theNavy's advanced satellite communications equipmentand JTIDS. Production quantities of at least 100,000modems are estimated.

NATO IFF (Navy). Last year, the Navy was desig-nated the lead service to develop a triservice NATO iden-tification system to be used by all military ships and air-craft throughout NATO by the late 1980's. The new sys-tem must be compatible with all existing identificationsystems (Mark V, Mark XII, and DABS-discrete ad-dress beacon system). The market is immense, in the $7billion bracket.

Radar. The second category, radar, includes five brass-board systems.

Surveillance radar (Navy). Functions of this proposedairborne system to detect and help counter enemy missilesinclude adaptive beamforming combined with adaptiveDoppler processing (side lobe cancellation plus moving-target indication). It will have a programmable matchedfilter, signal synthesizer, and detector. Throughput rate isprojected at 4 x 1013 gate Hz. The radar's weight will belimited to approximately 460 kg.

Tactical air radar signal processor (Navy). VHSIC-based subsystems will be needed for signal processors inthe next generation of fleet air defense aircraft. This newprocessor is expected to be installed initially in the F-14and later in the F/A-1 8. Its main functions include timedomain correlation, 100 MHz analog-to-digital conver-sion, and fast Fourier transforms. It uses digital filters, a256 x 16 random-access memory with 4-ns access, a com-plex 16-bit ALU, and a high-speed input/output con-troller.

MRSP (Air Force). The multi-function radar signalprocessor is to be mounted within the nose radar of high-performance tactical aircraft. It will be used for thedelivery of air-to-ground precision weapons with modesrequiring the execution of large, complex fast Fouriertransforms at rates greater than 20 MHz. The same systemwill be used for future air-to-air radar processing require-ments, including threat assessment.

AMRAAM (AirForce). The advanced medium-rangeair-to-air system, a next-generation weapon for tacticalaircraft, uses an I/J-band coherent pulsed-Doppler radarwith a pulse repetition frequency variable from 15 kHz to1 MHz. By increasing throughput rates, VHSIC com-ponents will provide larger numbers of range gates andimproved Kalman filters. AMRAAM also needs a high-frequency, high-stability frequency synthesizer capableof operating over the I/J-band at 100 kHz intervals with± 25 kHz accuracy.

M2F2 (Army). The Army's equivalent ofAMRAAM,the multi-mode fire-and-forget missile, cannot be builtwith conventional component technology. The newmissile will be used for either air defense or land combat.using more than one seeker mode. The Army is consider-ing some combination of passive antiradiation homingwith narrowband or wideband receivers, passive infraredwith one or more colors, and active radar or, for an in-terim system, semiactive radar.

Electronic warfare. Four brassboard systems areplanned for the electronic warfare category.

APMS (Air Force). An advanced power managementsystem is needed to improve airborne elctronic counter-measures. ECM performance can be improved by bettermanagement of jammer resources in spectral, temporal,and spatial domains for any given receiver/transmitterconfiguration. VHSIC components are being considered tobring down weight to 55 kg, size to 0.074 m3 (2.6 ft3), powerto 600 W, and cost to $180,000 in production quantities.

Target acquisition fire control (Army). This is theplanned signal processor for a forward-looking infraredsystem to be installed initially in combat vehicles such asthe XMl tank, later in remotely piloted vehicles such asthe Aquila, and still later in mini-RPVs. The FLIR willpick up targets and then hand them off to precision-guided munitions such as Copperhead or Hellfire fordestruction. This requires continuously available interac-tive imagery at compression ratios of up to 10,000:1 foranti-jam protection with minimal degradation of thesignal. Since weight and power constraints will be severe,high-functional-density VHSIC components will beessential.

ESMsignal sorter (Navy). At present, electronic-sup-port-measures signal sorters use 1500 LSI chips; VHSICtechnology is aimed at reducing that number to 30. Fur-thermore, the electromagnetic threat is expected to in-crease both in density and complexity, with sophisticatedemitters producing waveforms that include both frequen-cy and time agility. Better signal-sorting systems will beneeded on aircraft, surface ships, and submarines, withcontent-addressable memories improved over the current64-bit density with 300-ns delays to 1K-bit densities with30-ns delays.

EW weapon targeting (Army). This is a program toprovide a passive, highly mobile, integrated electronic-warfare system-probably mounted on advanced attackhelicopters-for real-time targeting and guidance infor-mation for firing against highly mobile, high-prioritythreats. This must be an all-weather system with on-boardweapon guidance capable of ensuring an accuracy of10-50 m from ranges of 10-25 km. The antennas andreceivers will have to be modular so that they can coverenemy electromagnetic emissions over a bandwidth of1-95 GHz.

Image processing. Three systems comprise the image-processing brassboards.

February 1981 17

Image processor (Navy). The use of focal-plane arraytechnology for surveillance, weapon control, and signalprocessing is advancing faster than processing tech-nology. Extraction of signal information from theoptical/electro-optical energy presented to the detectorsof a focal-plane array exceeds the ability of conventionalanalog hardware, such as charge-coupled devices, to han-dle the high data rates. The Navy is seeking to applyVHSIC components in a modular approach for process-ing 64-96 multiplexed channels in a single chip from a sen-sor with up to 1000 channels. The processor will performgain and offset correction, two-dimensional adaptivespatial filtering, multispectral ratioing, two-dimensionaladaptive thresholding, and edge detection. The vectorprocessor will sample data at 1 MHz and perform pro-grammable algorithms, using external reference data andthe main data stream, at 50 operations between datasamples. Requirements for bit rates ranging from 10 tolOOM bit/s and processing rates of 1012 to 101' gate Hz areexpected.

AOSP (AirForce). Under a cooperative program withDARPA, the Defense Advanced Research ProjectsAgency, the Air Force is developing new families ofspace-based surveillance sensors and communicationssystems for the late 1980's and early 1990's. The objectiveof the advanced on-board signal processor program is toperform the signal processing functions on board thesatellites within the appropriate power, life, radiation,size, and weight constraints. VHSIC components areplanned to meet the processing requirements of multi-mission radar, electro-optical sensor, and advanced com-munications systems.

Cruise missile (Air Force). Future versions of thecruise missile will require more accurate guidance, and theAir Force is looking at VHSIC components for anautonomous precision navigation and guidance systemthat will reduce weight, increase maneuverability, and im-prove survivability by allowing the missile to fly at loweraltitudes and at greater speed. This effort is being con-ducted in conjunction with DARPA's autonomous ter-minal homing program. The Air Force estimates thathigh-velocity terminal guidance will require patternmatching of up to 256 x 256 pixel images at 5 frames/swith 4 bits/pixel. These may be divided into subarrays forparallel processing.

General-purpose computers. Three general-purposecomputer brassboards are contemplated for the VHSICprogram.

General-purpose computer (Navy). The Navy is con-sidering the use of VHSIC components to producesmaller versions of existing computers. These new modelswill emulate the Navy's AN/AYK-14 airborne computerand AN/UYK-20 shipboard computer (which are alreadysoftware-compatible with each other), and initial applica-tions will be in torpedoes and the F-14 carrier-basedfighters. The goal is to develop a chip set to build a 32-bitmicroprogrammable processor capable of executing 50million instructions per second.

Universalsensorsignalprocessor (A irForce). This is aprogram to use VHSIC technology to create a general-purpose signal processor for demonstration with theE-3A AWACS radar. The E-3A was chosen because itsradar exhibits many of the needs common to existingmilitary systems and because the aircraft is expected tohave a 30-year life, during which time the threat to bedealt with is likely to change considerably. Oncedeveloped, the universal signal processor is expected to beable to support the sensors used in other programs such asPave Paws, advanced tactical radar, space radar,space/airborne electro-optical search systems, and unat-tended radar. Immediate requirements are for an im-proved ECCM capability, but ESM is also included inplans for the future.

AN/A YK-15A (Air Force). This is a program to"shrink" a general-purpose airborne computer onto aVHSIC chip. The Air Force already has two candidateprocessors-a microcomputer with a 300K operations-per-second throughput rate and a larger processor with a400 KOPS rate. Both use core memory. This program isaimed at developing a smaller, more powerful computerfor missile applications where space is severely limited.

Antisubmarine warfare. The Navy is considering aVHSIC chip set for programmable processing of ASWdata. The critical, computationally intensive portion ofthe acoustic signal processing task consists of adaptivefiltering, beamforming, Fourier analysis, and fixed filter-ing. These require a broadly applicable signal processingsubsystem performing the mathematical operations offast Fourier transform, Widrow LMS algorithm, digitalfiltering, and delay-and-sum beamforming. The pro-cessor also has to perform all other acoustic functions, in-cluding integration, autodetection, parameter estima-tion, and analog/digital conversion, but these are notconsidered speed-critical. Applications will be in surfacesonars, advanced sonobuoy array processors, andtorpedoes.

Scaling to smaller dimensions:benefits and barriers

Achieving the throughput rates discussed above re-quires a fundamental change in the IC transistor-that ofscaling down its dimensions. Thus, a number of techno-logical barriers must be overcome before the benefits ofthe VHSIC program can be realized.

Benefits. As an example of the benefits of scaling tosmaller dimensions, consider the MOS transistor-com-posed of a source, a drain, and a gate-as shown in Figure6. The gate is separated from the silicon substrate by theoxide thickness To . The source and drain spacing is L,and the channel width is W. The scale factor, K, is definedas the old dimension divided by the new dimension. L, W,and Tox are all reduced by the factor K. The doping densi-ty of the channel must increase by the factor K as theminimum feature size is decreased, and the gate voltagemust be decreased by the factor K. Thus,

COMPUTER18

* device area scales by the factor K-2,* delay time scales by the factor K- ',* power dissipation scales by the factor K- 2, and* radiation hardness increases by the factor K- 2.

These are the significant benefits of scaling.

Negative effects. Turning now to the barriers that mustbe overcome to achieve these very beneficial effects, firstconsider the negative effects of scaling4:

* the line resistance increases by the square of the scalefactor,

* current density increases linearly with scale factor,and

* contact resistance increases by K2.As a result of higher current density, the median time to

failure of the interconnect decreases. For example, Figure7 shows that the median time to failure in an aluminum in-terconnect line is orders of magnitude larger in a linecarrying 105 A/cm2 than in a line carrying 106 A/cm.2This is primarily due to electro-migration. Interconnectsystems have been devised which improve this situation,but it is mentioned here to indicate one of the problemsthat results, and must be overcome in a practical way, ascircuits are scaled to smaller dimensions.

Noise margins. Another detrimental effect of scalingMOS transistors is reduced noise margins. The root meansquare noise of MOS transistors, primarily 1/f noise, isinversely proportional to the square root of the transistorarea. The signal is proportional to the voltage swing,which scales as K- '. Therefore, the signal-to-noise ratioin the MOS transistor decreases as the square of the scalefactor, and the noise margin is less in small transistors.

Electromagnetic interference. The electromagnetic in-terference is a function of bipolar transistor perimeter, asillustrated in Figure 8. As the perimeter decreases, thesusceptibility to electromagnetic interference increases.5This is especially important to Navy systems, such as ship-board systems, where signal processors may be exposed toradiation due to radar antennas.

Soft errors. Another problem which becomes moreserious with scaling is the soft error problem in dynamic

Tox

random-access memories. Loss of memory bits can resultfrom alpha particle emissions from packages containingminute amounts of radioactive materials. As shown inFigure 9, the error rate of charge-coupled dynamic RAMsincreases as the critical charge, or the size of the storagecell, decreases. This may force VHSIC designs to usestatic memory, which is not as susceptible to soft errorproblems as dynamic memory.

Radiation hardness. Although scaling laws indicate again in radiation hardness with scaling, the trend as

Figure 7. Median time to failure vs. reciprocal temperaturefor aluminum interconnects.

L

K = SCALE FACTOR = OLD DIMENSION/NEW DIMENSION

DEVICE PARAMETER SCALING FACTORDEVICE DIMENSION T0,, L, W 1/KDOPING DENSITY NA KVOLTAGE V 1/KCURRENT/ 1/K

Figure 6. The basic assumptions used in the scalingtheory of MOS transistors.

Figure 8. Radio frequency sensitivity factor vs. bipolar transistor emit-ter perimeter.

February 1981 19

Figure 9. Error rate vs. critical charge for charge-coupledRAM cell.

several technologies have evolved from MSI toward VLSI(for which no effort has been made to radiation harden)shows an alarming tendency for devices having smallerfeature sizes to be more susceptible to ionizing radiation.This situation is illustrated in Figure 10. In many cases thefactors causing the susceptibility to radiation have beenidentified and corrective measures taken, thereby increas-ing radiation hardness to rather high levels. But thegeneral trend is for smaller MOS devices to be moresusceptible to radiation, and care must be taken to iden-tify inherently radiation-soft devices and techniques sothat inherently radiation-hard technologies can beselected.

Economical lithography. With optical lithography-the lithographic technique used during the 20-year historyof ICs-whole wafers are exposed at once. This allows

Figure 10. Radiation hardness vs. device density for sev.eral technologies.

delineation of a larger number of chips at one time andturns out to be a very economical way of definingfeatures. The problem arises as the feature size is reduced;a very fundamental factor-the wavelength of light-limits feature sizes to approximately one micrometer.Steps have been taken to use short-wavelength visiblelight, that is, ultraviolet, in lithography, but this has beentaken to the point of diminishing returns.

It seems clear that achieving feature sizes well belowone micrometer-for example, 0.5 micrometer-will re-

quire a fundamentally different lithographic technique.A leading contender is electron-beam lithography, whichmakes use of a computer-controlled scanning electronmicroscope system as illustrated in Figure 11. Applyingdigital voltages to the system causes the electron beam toscan over the wafer, exposing electron resists in the ap-propriate places and thereby delineating one level of theIC. This can be done in a raster-scan fashion, illustrated inFigure 12, with the electron beam turned on and off at ap-propriate places as it scans the wafer. Alternate schemes,shown in Figure 13, include a vector-scan system wherebythe beam is directed to and moved in only the area whereexposure is desired. A more advanced technique uses anextended-area square aperture to expose-at one time-areas many times the inherent beam diameter. In an evenmore advanced technique, a variable aperture providesrectangles of various dimensions to eliminate scanningthe minimum-size beam over a large area.

The problem with these electron-beam lithographysystems is one of economics. Chips must be exposed oneat a time, that is, in series rather than in parallel as with thewhole-wafer optical lithography techniques. However,considerable progress has been made, and definition offeature sizes necessary for VHSIC has been demon-strated. It is the economics of the situation which must beaddressed by the VHSIC program.

Figure 11. Schematic diagram of an electron-beam li-thography column.

20 COMPUTER

Computer-aided design. Because defense applicationsrequire a good deal of customality and because ofthe highcost of design for large-scale and very-large-scale ICs, thesuccess of the VHSIC program depends heavily on im-proved computer-aided design techniques.

The increasing design problem. Consider the followingpoints. The Intel 8086 microprocessor required 13 man-years for layout, and the Motorola 68000 microcomputerchip required 52 man-years design time. The design costof ICs, as we move into the VLSI era, is becoming verylarge. Large design costs can be accommodated in chipswhich have a very broad application base, such asmemory, but justifying custom chips becomes very dif-ficult for less extensive applications.To illustrate the magnitude of the design problem,

imagine each layer of a chip drawn on quadrille paperwith the minimum IC feature as a l/4-inch division. In thelate 60's, when we were dealing with feature sizes between15 and 20 micrometers, a feature had to be magnified by afactor of 350 for it to equal l/4 inch, and a complete masklevel would have required a 7-foot piece of quadrillepaper. This would be mangeable. But, moving intofeature sizes achievable through the 70's and into the late70's, such chip layouts would require pieces of quadrillepaper the size of a living room floor and two tennis courts,respectively. Continuing through VHSIC I and 11-thatis, 1.25 and 0.5 micrometers, respectively-would require

Table 3.The design problem.

DEVELOPMENTTIMEPERIOD

LATE 60'SEARLY 70'SLATE 70'SVHSICVHSIC II

MINIMUMFEATURESIZE: LINEAND SPACE17.51m821.250.5

SCALEFACTOR TOMAGNIFY

TO 1/4 INCH350800

32005000

12500

PAPER SIZE TOLAY OUT 250MIL CHIP

I 7 FT) WALL HANGING( 17 FT) LARGE LIVING ROOM FLOOR( 67 FT) TWO TENNIS COURTS(100 FT) TWO BASKETBALL COURTS(260 FT) TWO FOOTBALL FIELDS

scale factors on the order of 5000 and 12,500 and papersizes on the order of two basketball courts and two foot-ball fields.

This example, summarized in Table 3, illustrates themagnitude of the design problem as we achieve micro-meter and submicrometer feature sizes. Clearly, comput-er aids on a large scale will be mandatory to design thesechips economically.

The Macrocell approach. One of the methods underconsideration for economical chip design is the macrocellapproach. The design for each macrocell-a functionalblock, such as a multiplier or a memory, which could beequivalent to an LSI chip-would be stored in a macrocelllibrary. Chips would then be designed by arrangingmacrocells into an interconnection grid structure as illus-trated in Figure 14. Once a macrocell was designed, thedesign-that is, the macrocell-could be used over andover again and its cost amortized over many chip designs.

Macrocells can be designed in various ways. For exam-ple, a macrocell for widespread use, such as a memorycell, could be designed very carefully, perhaps in amanpower-intensive manner, to achieve high density. Onthe other hand, a specialized macrocell for a one-of-a-kind application might be designed using an automatedtechnique which would provide a low-cost but low-functional-density macrocell.

In principle, the macrocell approach brings flexibilityto VHSIC chip design. However, as listed in Figure 14,

Figure 12. Schematic diagram of a raster-scan electron-beam pattern.

Figure 13. Diagram showing non-raster-scanned electron.beam patterns. Figure 14. The macrocell VHSIC design approach.

February 1981 21

there are other issues, aside from the design strategy itself,such as testability of the macro, effective interconnectionof macros on a chip, and overall chip testability.

Substrates. Finally, we turn to a somewhat mundanebut nevertheless a barrier problem-that is, the quality ofthe silicon substrate. In a qualitative sense, as minimumfeature sizes are reduced, defects which were previouslynot debilitating become more and more debilitating sincethe size of the defect increases relative to the size ofthe ac-tive device. As a result, more attention must be given todefect density. The quality of the material varies from lotto lot, from time to time, and from manufacturer to man-ufacturer; however, the extremely high-quality silicon

Figure 15. Defect density vs. parts per million oxygen con-lent for several domestic and foreign silicon suppliers.

Figure 16. Scanning electron microscope photographs of(left) normal CZ-grown silicon and (right) Sony magnetic-grown silicon.

substrate material that has been achieved by Shinetsu andSony with defect densities close to I defect per squaremm, as illustrated in Figures 15 and 16, should be em-phasized. Low defect densities have been identified byAracor 8 as being very sensitive to two parameters: the ox-ygen content in the wafer and the carbon to oxygen ratio.This work is continuing under VHSIC III sponsorship inan attempt to identify the growth parameters necessary toachieve very-low defect density in starting materials andto improve our capability for providing high-qualitymaterial to VHSIC contractors.

In summary, successful completion of the VHSIC pro-gram will result in a highly significant and broadly basedpayoff to the military departments, but many difficulttechnological and economic barriers must be overcome toreach these goals. This will require the ingenuity and jointefforts of the IC and defense systems industries, theuniversity community, and the military departments. -

References

1. G. W. Preston, "High-Speed Integration Circuits forMilitary Applications," IDA Paper P-1423, Nov. 1979.

2. L. W. Sumney, "VLSI With a Vengeance," IEEE Spec-trum, Vol. 17, No. 4, Apr. 1980, pp. 24-27.

3. John Rhea, "VHSIC-Advanced Components for a NewGeneration of Weapon Systems," Intel. Def. Rev., Vol. 6,1980, pp. 887-889.

4. J. L. Prince, "VLSI Device Fundamentals," in VLSIFun-damentals and Applications, D. F. Barbe (ed.), Springer-Verlag, 1980.

5. Robert E. Richardson, Jr., "Modeling of Low-Level kec-tification RFI in Bipolar Circuitry," IEEE Trans. Elec-tromagnetic Compatibility, Vol. EMC-21, Nov. 1979, pp.307-311.

6. H. L. Hughes, private communication.7. IEEE Solid State Circuits and Technology Committee

Workshop on Microprocessors and Memories, Feb. 12,1980.

8. T. J. Magee, Interim Report on Contract N00014-80-C-0071: Silicon Quality-A Consideration for VHSI CircuitDevelopment.

David F. Barbe is the assistant for elec-tronics and physical sciences in the Officeof the Assistant Secretary of the Navy forReearch, Engineering, and Systems. Be-

fore that, he was a fellow engineer at theWestinghouse Advanced Technology Lab-oratory in Baltimore, Maryland, and headof the Microelectronics Branch at the Na-val Research Laboratory in Washington,

Barbe is an IEEE fellow, cited for his pioneering work incharge-coupled devices, and has received several citations andawards for outstanding government service. He has publishedand presented over 100 technical papers and edited several booksin the fields of electro-optical imaging, charge-coupled devices,and VLSI.He received the BSEE with high honors in 1962 and the MSEE

in 1964 from West Virginia University. In 1969 he received thePhD degree in electrical engineering from The Johns HopkinsUniversity. He is a member of Eta Kappa Nu, Tau Beta Pi,Sigma Xi, the American Physical Society, and the IEEE.

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