VHDLSolutionsss

Digital Design & Embedded SystemsDigital Design & Embedded Systems

VHDL: The very basicsVHDL: The very basics

Learning outcomes

VHDL design units

VHDL data types

VHDL operators

VHDL operators

VHDL conventions

Concurrent signal assignments

HDL: Hardware Description Language Most used: VHDL, Verilog

VHDL : Very high speed integrated circuit

Overview

Originally developed for US Department of Defense, firstreleased in 1987 as an IEEE standard (VHDL-87), lastmajor revision VHDL 2000

A technology independent, standard language fordescribing digital electronic systems

VHDL Primary Constructs

VHDL primary constructso Design Units, used to describe logic

Contains the implementation of the functionality exposed by package declaration

Defines the names, input/output signals of a hardware module

Describes a particular implementation of an entity

Allows a convenient way to define and group functions, procedures, types, components, etc.

exposed by package declaration

The Entity

A black box, this defines theinterface to the outside world

One entity can have manydifferent architectures

Entity Declaration

Simplified syntax:

The Architecture

Describes what the circuit actually doeso Internal implementation

AND Gate

Simplified syntax:

AND Gate

Entity Declaration & Architecture -Example

Libraries, Packages & Package Bodies

VHDL library files allow the storage of commonly usedpackages and entities that can be used in VHDL programs.There are two types:

o Standard library: used to store predefined packageso User-defined library: holds user-defined packages

The keyword LIBARARY makes the packages contained inthe library_name libarary available or visible to the VHDLprogram

The keyword USE identifies what is to be used from thelibrary

Libraries, Packages & Package Bodies

Packages hold reusable code such ascomponents, functions and proceduresand to make them available to VHDLprogram

o Can be defined by the user or suppliedby an outside source in the form ofstandard packages

standard packages

The package body is where the items listed in the packagedeclaration are defined

Library Declarations - Example

AND Gate

Data Objects & Identifiers

Four Classes of Data objects:

Constant: Holds a single value of a given type

Variable: Holds a value of a given type where a value of same type can be assigned

Signal: Used to define a data pathway between two

Signal: Used to define a data pathway between two functional units

File: Contains a sequence of value of one or more types

o Used for simulation only

Identifiers are used as variable, signal or constantnames , as well as names of design units (entities,architectures, etc.)

Data Types

The type of a signal, variable, or constantobject specifies the range of values it maytake and the set of operations that can beperformed on it

Data Types: Enumerated types

CHARACTER - one of the ASCII set BOOLEAN - can be FALSE or TRUE BIT can be 0 or 1 STD_LOGIC - signal or variable of this type can take on thefollowing values:

U: uninitialized. This signal hasnt been set yet.

U: uninitialized. This signal hasnt been set yet. X: unknown. Impossible to determine this value/result. 0: logic 0 1: logic 1 Z: High Impedance W: Weak signal, cant tell if it should be 0 or 1. L: Weak signal that should probably go to 0 H: Weak signal that should probably go to 1 -: Dont care.

Data Types: Arrays

An array of type BIT is called a BIT_VECTOR

i.e. signal MYSIG : BIT_VECTOR(0 to 3); -- in architecture

An array of type STD_LOGIC is called aSTD_LOGIC_VECTOR

i.e. yourSIG: OUT STD_LOGIC_Vector(31 downto 0); -- in entity

i.e. yourSIG: OUT STD_LOGIC_Vector(31 downto 0); -- in entity

A STRING is a character array

i.e. Constant GREETING:STRING:=Hello!;

Port Modes

IN means input-ONLYo you cannot use a mode IN signal on the LEFT of an equation (you cannot assign a new value to INPUTS)

OUT means output-ONLYo You cannot use a mode out signal on the RIGHT side

o You cannot use a mode out signal on the RIGHT side of an equation (you cannot use the OUTPUTS)

INOUT means bi-directionalo Like a three-state bus, for example. This type of signal may appear on the left OR right side of equations

Port Modes - Example

Exercise 1

Write the VHDL code (Entity part) to implement the following 4:1 multiplexer:

Entity??

Port Modes - Solution

Conventions Naming and Labelling

VHDL is not case sensitive

Example

george

georgeGeorgeGEORGE

are all equivalent

Conventions Naming and Labelling

General rules:

1. All names should start with an alphabet character (a-z or A-Z)

2. Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_)

and underscore (_)

3. Do not use any punctuation or reserved characters within a name (!, ?, ., &, +, %, etc.)

4. Do not use two or more consecutive underscore characters (__) within a name

5. All names and labels in a given entity and architecture must be unique

Conventions Comments

Comments in VHDL are indicated with a double dash --

o Comment indicator can be placed anywhere in the line

o Any text that follows in the SAME line is treated as a comment

o Carriage return terminates a comment

o Carriage return terminates a comment

Example

-- this is an exampleData_in

Conventions Reserved Words

You cannot use these as identifiers

Conventions Free Format

VHDL is a free format language

o Space and carriage return are treated the same way

Example

are all equivalent

Exercise 2

Find the errors in the following VHDL code and correct them.

Conventions

Operators

Operators are used in expressions involving signal, variable, or constant object types

Operators -Examples

Let A=1100, B=1110

Concurrent Signal Assignment Statements

Many components of a circuit can be operatingsimultaneously and concurrently driving distinct signals tonew values

How can we describe the assignment of values to signals?o Signal is assigned a value at a specific point in time

Within VHDL, signals are assigned values using Signal

Within VHDL, signals are assigned values using Signal Assignment Statements

Multiple signal assignment statements are executed concurrently and referred to us as Concurrent Signal Assignment Statements:

o Simple Signal Assignments o Conditional Signal Assignments o Selected Signal Assignments

Simple Signal Assignments

These have the formtarget


Exercise 4 (Homework)

Write the VHDL code toimplement the functionexpressed in the followingtruth table using simple

signal assignments

Entity??Architecture??Signal Assignment ??

F = ??


LMNMLF ++++====

Alternative architecture:

Solution ?

Conditional Signal Assignments

These have the form

target


LMNMLF ++++====


Exercise 6

Write the VHDL code to implement a 4:1 multiplexer using conditional signal assignments.

Entity??Architecture??Conditional Signal Assignment ??

Selected Signal Assignments

These are of the formwith choose_expression select

target

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