VHDL sinteza

8/7/2019 VHDL sinteza

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VHDL RTL


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.

.

(RTL)

- . IEEE 1076.6, VHDLRegister Transfer Level .


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IEEE 1076.6

VHDL

.

1999. => VHDL-87.

2004. => VHDL-2002.


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:

, boolean, bit character.

, integer, natural i positive.

bit_vector string

std_ulogic, std_ulogic_vector, std_logic std_logic_vector, std_logic_1164

unsigned signed, numeric_bit unsigned signed, numeric_std


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boolean bit,

std_logic std_ulogic .


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.

enum_encoding:

attribute enum_encoding : string;

:type state is (idle, preamble, data, crc, ok, error);a ttr ibu te enum_encoding of state : type is "000 001 010 011 100 111";


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.

,

:type sample is r ang e 64 to 63 ; 7-

sub type table_index is natural r ang e 0 to 1023 ; 10-

231

+2 31 1


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.

.

.=> .


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:

:type coeffs is a rr a y (3 down to 0) of integer;type channel_states is a rr a y (0 to 7) of state; state

sub type w ord is bit_vector(31 down to 0);type reg_file is a rr a y (0 to 15) of w ord;

:type color is (red, green, blue);type plane_status is a rr a y (color) of boolean; type matrix is a rr a y (1 to 3, 1 to 3) of real; 2D, floatingpoint type reg_file_set is a rr a y (0 to 3) of reg_file;


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0 1.

-.

.


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'Z',

.:

if request_enable = '1' the nrequest := ready;

el s erequest


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( ),,

, .

, std_match.


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s td_ma tch numeric_std

.

. "="

std_match . std_match

"don't care" ('') "don't care" .


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.

status


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.

:wi th addr(1 down to 0) s elect

request


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:

request


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.data_bus


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.

, , .

bit, std_ulogic std_logic.

, bit std_ulogic .


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process_statement w ait (clock-edge) .


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clock_edge .

:r ising_ e dg e ( clock_signal_ name )clock_signal_ name ' eve n t and clock_signal_ name = '1'clock_signal_ name = '1' and clock_signal_ name ' eve n tno t clock_signal_ name ' s tab le and clock_signal_ name = '1'clock_signal_ name = '1' and no t clock_signal_ name ' s tab le


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:

fa lling_ e dg e ( clock_signal_ name )clock_signal_ name ' eve n t and clock_signal_ name = 0'clock_signal_ name = 0' and clock_signal_ name ' eve n tno t clock_signal_ name ' s tab le and clock_signal_ name = 0'clock_signal_ name = 0' and no t clock_signal_ name ' s tab le


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:

simple_reg : pr o ce ss ( clk )b e gin

if clk'event and clk = '1' the nreg_out


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:

process_statement


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( )

; then

=> .

: w ait ,

.


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!

, .

=> ,

.


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w ait :

process_statement the n

;e nd if;

e nd pr o ce ss [ process _label ] ;

w ait , .


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w ait until...Tada je za clock-edge e :

clock_signal_ name = '1'clock_signal_ name = '0 w ait

. w ait

, w ait .

, w ait .


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reg : process isbegin

w ait until reset = '1' or rising_edge(clk);if reset = '1' then

q


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:

shift_reg: pr o ce ssva r iab le stored_value : bit_vector(7 down to 0);

b e ginwai t un til clk = '1';If load = '1' the n

stored_value := load_data_in;q


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, . ,

, . inferred storage.

:

latch : pr o ce ss ( enable, d )b e gin

if enable = '1' the nq


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VHDL- .

,

.

.


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.

.

.


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a rch itect u re rtl of state_machine istype state is (ready, ack, err);signa l current_state, next_state : state;

b e ginnext_state_and_output: pr o ce ss ( current_state, in1, in2 )

b e ginc as e current_state is

w he n ready =>

out1


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type mem_array is array (0 to 2**depth - 1) of std_ulogic_vector( w idth - 1 do w nto 0);

signal RAM : mem_array; :

asynch_RAM : process (addr, d_in, w e) isbegin

if w e = '1' thenRAM(to_integer(addr))


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,

synch_RAM : process (clk) isbegin

if rising_edge(clk) then

if w e = '1' thenRAM(to_integer(addr))


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VHDL:

.

.

.


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VHDL :

(inertial transport) after .

(clock-

edge) , .


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VHDL :

,

.


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VHDL:

. 'base,

'left, 'right, 'high, 'lo w , 'range,'reverse_range 'length.

.

, A'left(1) . 'event 'stable

clock-edge .


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VHDL:

, shift_left shift_right

numeric_bit numeric_std.

"/", mod rem ,

.

"**" ,

2.


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VHDL:

, .

. :

rtl_synthesis off

rtl_synthesis on

.

VHDL rtl_synthesis off

rtl_synthesis on .

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VHDL sinteza