VHDL Project II:VHDL Project II:Bubble SorterBubble Sorter

Matthew MurachMatthew Murach

Slides Available at: www.pages.drexel.edu/~

mjm46

Bubble Sort DescriptionBubble Sort Description

Takes a certain number of values and Takes a certain number of values and sorts them in ascending ordersorts them in ascending order

Project consists of a simple four bit Project consists of a simple four bit comparator which interchanges values comparator which interchanges values when required.when required.

Logic is needed to wire the comparators Logic is needed to wire the comparators together. (master->component design)together. (master->component design)

Bubble sort has a worst case complexity Bubble sort has a worst case complexity of O(N) where N is the number of of O(N) where N is the number of numbers to be sorted.numbers to be sorted.

Method One: Method One: Logic Flow (4 number Logic Flow (4 number

example)example)8 5 7 3 1st Stage: Sequence R-L-R-L

5 8 3 7 2nd Stage: Sequence L-R-L-R

5 3 8 7 3rd Stage: Sequence R-L-R-L

3 5 7 8 4th Stage: Sequence L-R-L-R (DONE)

= basic PE element (four required)= denotes swap operation

Processing ElementProcessing ElementLd : in std_logic_vector(3 downto 0) – initial value

R : in std_logic_vector (3 downto 0) – right register value

L : in std_logic_vector (3 downto 0) – right register value

Ck : in std_logic; -- clock inputEn : in std_logic; -- enableWr : in std_logic; -- load registerSw : in std_logic; -- R or L readRd : in std_logic; -- Read result

Output : out std_logic_vector(3 downto 0)

L_o : out std_logic_vector (3 downto 0) – pass result to the left register

R_o : out std_logic_vector (3 downto 0) – pass result to the left register

Disadvantages of Method Disadvantages of Method 11

Messy boundary conditionsMessy boundary conditions Need a special value at the ‘end’ nodesNeed a special value at the ‘end’ nodes Or need to use non-standard PEsOr need to use non-standard PEs

Wire intensiveWire intensive Uses lots of wires (11 total signals)Uses lots of wires (11 total signals) A pain to route all that internal wiring A pain to route all that internal wiring

in the master design (what if we want in the master design (what if we want more control on the swap which would more control on the swap which would require another 4 wires….)require another 4 wires….)

PE is complicatedPE is complicated

Method Two: Make it Method Two: Make it simplesimple Why not use registers to store values instead of Why not use registers to store values instead of

the processing units? (uses three simple PEs)the processing units? (uses three simple PEs)

A B

8 5 7 3

C

5 8 3 7

= Register

= PE

PE for Method TwoPE for Method Two

Ck : in std_logic; -- ClockEn : in std_logic; -- En

C : out std_logic_vector(3 downto 0);D : out std_logic_vector(3 downto 0);

A : in std_logic_vector(3 downto 0);B : in std_logic_vector(3 downto 0);

Method 2: ExaminedMethod 2: Examined

Only 6 wires need to be routed (8 if Only 6 wires need to be routed (8 if control is desired on the write ports)control is desired on the write ports)

Simple designSimple design No need for fancy internal logic (R, L states)No need for fancy internal logic (R, L states) Just compare the two values and swap if Just compare the two values and swap if

necessarynecessary Compare logic is fixed with respect to inputCompare logic is fixed with respect to input

Need extra logic for a register but that Need extra logic for a register but that is trivial.is trivial.

Component DeclarationsComponent Declarations Component declaration is nearly same as the Component declaration is nearly same as the

device’s entity declaration. device’s entity declaration. Simply Copy and Paste in the component Simply Copy and Paste in the component

descriptions and add the key word component.descriptions and add the key word component.

Component bubble_sort is port (

-- stuff here

); end component;

Entity bubble_sort is

port (

-- stuff here

); end bubble_sort;

Internal Signals and Port Internal Signals and Port MappingsMappings

Internal wiring is done with signals. Internal wiring is done with signals. Simply declare these signals like you Simply declare these signals like you have done in previous exercises.have done in previous exercises.

Port mapping is the where the actual Port mapping is the where the actual components are instantiated and components are instantiated and mapped to their respective signals.mapped to their respective signals.

Note that you can instantiate more Note that you can instantiate more then one instance of each then one instance of each component. component.

Example of Port Mapping Example of Port Mapping Let’s say you want to make a master VHDL Let’s say you want to make a master VHDL

design from the two components on the right.design from the two components on the right.

-- Signal Declarations

Signal N : std_logic;

Signal M : std_logic;

Begin

-- Port Map Declarations

My_A : Acomp generic map(N) port map(N,M,ck);

My_B : Bcomp generic map(N) port map(M,N,ck);

A Component

B Component

C Component

M N

Ck