--VHDL program for Booth’s Multiplier

------------------------------------------------------------------------------------ Company: -- Engineer: -- -- Create Date: 11:36:54 07/07/2011 -- Design Name: -- Module Name: booth - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity BoothMult4 is

GENERIC(k : POSITIVE := 4); port(multiplier, multiplicand: in std_logic_vector(k-1 downto 0);

clk: in std_logic; ready: out std_logic; product_result: out std_logic_vector((2*k-1) downto 0));

end BoothMult4; architecture boothMult4Arch of BoothMult4 is signal count: integer:=0;

begin process(clk)

variable num: std_logic_vector(2*k downto 0):="000000000"; variable Y, Z: std_logic_vector(k-1 downto 0);

variable i:integer; begin

if count=0 then num := "000000000";

Y := multiplicand; num(k downto 1) := multiplier; end if; if clk'event and clk='1' then

for i in 0 to (k-1) loop if(num(1) = '1' and num(0) = '0') then Z := num(2*k downto (k+1)); num(2*k downto (k+1)) := Z - Y; elsif(num(1) = '0' and num(0) = '1') then Z := num(2*k downto (k+1)); num(2*k downto (k+1)) := Z + Y; end if;

count<=count+1; if count=k then count<=0;

end if; num((2*k-1) downto 0) := num(2*k downto 1); end loop;

if count=k then ready<='1';

product_result <= num(2*k downto 1); else ready<='0'; end if;

end if;

end process;

end boothMult4Arch;

--TESTBENCH PROGRAM (4-bit multiplication (k=4))---------------------------------------------------------------------------------- Copyright (c) 1995-2007 Xilinx, Inc.-- All Right Reserved.---------------------------------------------------------------------------------- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 9.2i-- \ \ Application : ISE-- / / Filename : gggg.vhw-- /___/ /\ Timestamp : Thu Jul 07 12:45:01 2011-- \ \ / \ -- \___\/\___\ ----Command: --Design Name: gggg--Device: Xilinx--

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_TEXTIO.ALL;USE STD.TEXTIO.ALL;

ENTITY gggg ISEND gggg;

ARCHITECTURE testbench_arch OF gggg IS FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

COMPONENT BoothMult4 PORT ( multiplier : In std_logic_vector (3 DownTo 0); multiplicand : In std_logic_vector (3 DownTo 0); clk : In std_logic; ready : Out std_logic; product_result : Out std_logic_vector (7 DownTo 0) ); END COMPONENT;

SIGNAL multiplier : std_logic_vector (3 DownTo 0) := "0000"; SIGNAL multiplicand : std_logic_vector (3 DownTo 0) := "0000"; SIGNAL clk : std_logic := '0';

SIGNAL ready : std_logic := '0'; SIGNAL product_result : std_logic_vector (7 DownTo 0) := "00000000";

constant PERIOD : time := 200 ns; constant DUTY_CYCLE : real := 0.5; constant OFFSET : time := 100 ns;

BEGIN UUT : BoothMult4 PORT MAP ( multiplier => multiplier, multiplicand => multiplicand, clk => clk, ready => ready, product_result => product_result );

PROCESS -- clock process for clk BEGIN WAIT for OFFSET; CLOCK_LOOP : LOOP clk <= '0'; WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE)); clk <= '1'; WAIT FOR (PERIOD * DUTY_CYCLE); END LOOP CLOCK_LOOP; END PROCESS;

PROCESS BEGIN -- ------------- Current Time: 1185ns WAIT FOR 1185 ns; multiplier <= "0110"; multiplicand <= "0101"; -- ------------------------------------- -- ------------- Current Time: 2785ns WAIT FOR 1600 ns; multiplicand <= "1111"; -- ------------------------------------- WAIT FOR 415 ns;

END PROCESS;

END testbench_arch;

4-bit multiplication