VHDL Intermediate Level - PLDWorld.com · • 2 : Q, QB – The FUNCTION of the device ... WITH sel SELECT q

2002-12-23 P.1

www.fpga.com.cn

VHDL Intermediate Level

You can download more files from:www.FPGA.com.cn

2002-12-23 P.2

www.fpga.com.cn

Note :

All the following examples can be compiled by IEEE VHDL compliant compilerIf having any problem with your VHDL compiler, please refer to your VHDL compiler manual for reference

2002-12-23 P.3

www.fpga.com.cn

Standard VHDL syntax format

Entity– all designs are expressed in terms of entities

Architecture– the architecture describes the behaviour of the entity

Process (optional)– a process is the basic unit of execution in VHDL

Generic (optional)– use to parameter information to an entity

2002-12-23 P.4

www.fpga.com.cn

Example of Standard VHDL format

2002-12-23 P.5

www.fpga.com.cn

Design Revolution : Traditional Schematics

The Schematic contains 2 NAND gate symbol instancesFour port instancesNets connect the symbols and ports together to form the RS flip-flop

RSFF : Reset-Set flip-flop

2002-12-23 P.6

www.fpga.com.cn

Design Revolution : Macro Schematic What this Graphic describes– The number of INPUT pins for the devices

• 2 : Set, Reset– The number of OUTPUT pins for the devices

• 2 : Q, QB– The FUNCTION of the device

• in this example, the function of device is described by the name of the symbol : RSFF

Why I need to know this ?– the symbol specify the interface (I/O) and the

function to the designer– when we use any symbol, we need to knows

• all the Interface I/O• function

2002-12-23 P.7

www.fpga.com.cn

Design Revolution : VHDL Design (1)Entity RSFF isPort (set, reset : in bit;

q, qb : buffer bit);end RSFF;Architecture netlist of RSFF isbeginq <= not(set and qb);qb <= not(reset and q);end netlist;

2002-12-23 P.8

www.fpga.com.cn

Simulation Result

2002-12-23 P.9

www.fpga.com.cn

Design Revolution : VHDL Design (2)Entity RSFF isPort (set, reset : in bit;

q, qb : buffer bit);end RSFF;Architecture netlist of RSFF isbegin

process(set, reset)begin

if (set = ‘1’ and reset = ‘0’) thenq <= ‘0’;qb <= ‘1’;elsif (set = ‘0’ and reset = ‘1’) thenq <= ‘1’;qb <= ‘0’;elsif (set = ‘0’ and reset = ‘0’) thenq <= ‘1’;qb <= ‘1’;end if;

end process;end netlist;

2002-12-23 P.10

www.fpga.com.cn

Different Coding but same Function

The fact that VHDL has so many possible representations for similar functionality is what makes learning the entire language a big taskWhich is the best ?– it is fully programming style dependents and experience– some compiler can do a very good job in terms of speed and

area on a specific written style (explore it by yourself) – general speaking, both will give you almost the same result

2002-12-23 P.11

www.fpga.com.cn

Design a 4-1 MUXLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;

ENTITY mux4 ISPORT (i0, i1, i2, i3, a, b : IN STD_LOGIC;

q : OUT STD_LOGIC);END mux4;

ARCHITECTURE body_mux4 OF mux4 ISSIGNAL sel : INTEGER ;BEGIN

WITH sel SELECTq <= i0 WHEN 0,

i1 WHEN 1,i2 WHEN 2,i3 WHEN 3,'X' WHEN OTHERS;

sel <= 0 WHEN a='0' AND b='0' ELSE1 WHEN a='1' AND b='0' ELSE2 WHEN a='0' AND b='1' ELSE3 WHEN a='1' AND b='1' ELSE4;

END body_mux4;

2002-12-23 P.12

www.fpga.com.cn

Simulation of 4-1 MUX

2002-12-23 P.13

www.fpga.com.cn

LAB 1

MUX 4:1

2002-12-23 P.14

www.fpga.com.cn

Design Requirement

•Design 4:1 mux using AND, OR, NOT primitives•Use the VHDL Template to help your design

y

abcd

sel_lsb

sel_msb

01

23

2002-12-23 P.15

www.fpga.com.cn

Solution - And, Or, Not

Entity lab1 isPort (a,b,c,d, sel_lsb, sel_msb : in bit;

y : out bit);end lab1;Architecture netlist of lab1 isbeginy <= ( a and not (sel_lsb) and not(sel_msb)) or

(b and sel_lsb and not (sel_msb)) or(c and not (sel_lsb) and sel_msb) or(d and sel_lsb and sel_msb);

end netlist;

2002-12-23 P.16

www.fpga.com.cn

Process Statement

2002-12-23 P.17

www.fpga.com.cn

Process Statement

Statements that execute serially, one after the otherMost programming language support this type of behaviour– e.g. C, Pascal

2002-12-23 P.18

www.fpga.com.cn

Process Statement TemplateSensitivity List

2002-12-23 P.19

www.fpga.com.cn

Simple Process Statement Example

library ieee;use ieee.std_logic_1164.all;Entity nand2 isport (a, b : in std_logic;

c : out std_logic);end nand2;architecutre nand2_body of nand2 isbeginprocess(a,b)variable temp : std_logic;temp := not(a and b);c <= temp;end process;end nand2_body;

2002-12-23 P.20

www.fpga.com.cn

Something which you can

Something which you can use within Process only– IF - THEN - ELSIF - END IF– CASE - WHEN - OTHERS– LOOP - FOR

2002-12-23 P.21

www.fpga.com.cn

If-then-else syntax

IF __expression THEN__statement;__statement;

ELSIF __expression THEN__statement;__statement;

ELSE__statement;__statement;

END IF;

if (a =‘1’) thenc <= “111”;

elsif (b = ‘0’) thenc <= “101”

elsec <= “000”;

end if;

2002-12-23 P.22

www.fpga.com.cn

Case - When - Others

CASE __expression ISWHEN __constant_value =>

__statement;__statement;

WHEN __constant_value =>__statement;__statement;

WHEN OTHERS =>__statement;__statement;

END CASE;

CASE instruction ISwhen “00” => accum <= ‘0’;when “01” => accum <= ‘1’;when others => accum <= ‘Z’;

END CASE;

2002-12-23 P.23

www.fpga.com.cn

Loop - For

__loop_label:FOR __index_variable IN __range LOOP

__statement;__statement;

END LOOP __loop_label;

FOR i IN 1 to 10 LOOPi_squared(i) := i*i;

END LOOP;

2002-12-23 P.24

www.fpga.com.cn

Lab 2

MUX 4:1

2002-12-23 P.25

www.fpga.com.cn

Design Requirement

•Design 4:1 mux using IF statements•Use the VHDL Template to help your design

y

abcd

sel_lsb

sel_msb

01

23

2002-12-23 P.26

www.fpga.com.cn

Solution -- If-Then-ElseEntity lab2 isPort (a,b,c,d, sel_lsb, sel_msb : in bit;

y : out bit);end lab2;Architecture netlist of Mux41 isbegin

process(a,b,c,d,sel_lsb,sel_msb)begin

if (sel_lsb = ‘0’ and sel_msb = ‘0’) theny <= a;elsif (sel_lsb = ‘1’ and sel_msb = ‘0’) theny <= b;elsif (sel_lsb = ‘0’ and sel_msb = ‘1’) theny <= c;elsey <= d;end if;

end process;end netlist;

2002-12-23 P.27

www.fpga.com.cn

Signal vs

Variable

2002-12-23 P.28

www.fpga.com.cn

Signal vs Variable

Signal Assignment– receive the assign value after a period of time

Variable Assignment– happens immediately when the statement is executed, no

delay

2002-12-23 P.29

www.fpga.com.cn

Example

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;



ARCHITECTURE body_mux4 OF mux4 ISsignal muxval : integer;BEGINprocess(i0,i1,i2,i3,a,b)beginmuxval <= 0;if (a = '1') then

muxval <= muxval + 1;end if;if (b = '1') then

muxval <= muxval + 2;end if;

case muxval iswhen 0 => q <= i0;when 1 => q <= i1;when 2 => q <= i2;when 3 => q <= i3;when others => null;

end case;end process; END body_mux4;

Why ????

2002-12-23 P.30

www.fpga.com.cn




ARCHITECTURE body_mux4 OF mux4 ISBEGINprocess(i0,i1,i2,i3,a,b)variable muxval : integer;beginmuxval := 0;if (a = '1') then

muxval := muxval + 1;end if;if (b = '1') then

muxval := muxval + 2;end if;

case muxval iswhen 0 => q <= i0;when 1 => q <= i1;when 2 => q <= i2;when 3 => q <= i3;when others => null;

end case;end process; END body_mux4;

2002-12-23 P.31

www.fpga.com.cn

Key points to remember

Function– Variables represent local storage

• Variables is updated immediately– the updated value can be used later in the model for

further computations– Signals represent circuit interconnect

Place of Declare– Variables : allow within Process structure– Signal : allow within Architecture structure

2002-12-23 P.32

www.fpga.com.cn

Visible– Variable : only with the process– Signal : if define within Entity - visible within the whole Entity

if define within Architecture - visible within the wholeArchitecture

Make sure that you must you the correct Signal or Variable declaration

2002-12-23 P.33

www.fpga.com.cn

When communicate with Two ProcessQ : When communicate with two process, I should use Signal or Variable ? How ?

Entity test isport (a, b, x : in std_logic;

y : out std_logic);end test;Architecture test_body of test isbeginProcess (a,b)variable d : std_logic;begind := a and b;e ( ) d;end process;

Process (e,x)variable z : std_logic;beginz := e and x;y <= z;end process;end test_body;

Hints : Signal is a net to connect two module Variable is used to keep tempory storage

Now I want a net or a storage ?

2002-12-23 P.34

www.fpga.com.cn

Can you convert Variable to Signal ?Library Ieee;use ieee.std_logic_1164.all;

entity and5 isport (a,b,c,d,e : in std_logic;

q : out integer);end and5;architecture body_and5 of and5 isbeginprocess (a,b,c,d,e)variable state : std_logic;variable delay : integer range 0 to 7;beginstate := a and b and c and d and e;if state = '1' then

delay := 3;else

delay := 7;end if;q <= delay;end process;end body_and5;

2002-12-23 P.35

www.fpga.com.cn

Lab 3

Address Decoder

2002-12-23 P.36

www.fpga.com.cn

Design Requirement•Design an address decoder to select either the serial port at address 1010 or the parallel

port at address 1100. Use an IF-THEN-ELSE statement.

•Use the output of the address decoder to control the select line of the multiplexor

•Design an multiplexor to select either the serial_port_data or parallel_port_data. Use CASE statement

•Connect the address decoder and the multiplexor using a SIGNAL

selector = 0 when abcd = 1010selector = 1 when abcd = 1100

process_b

multiplexor

data_outsel01

serial_port_dataparallel_port_data

process_a

address decoder

selectorbcd

adata_out = serial_port_data when sel = 0data_out = parallel_port_data when sel = 1

If-then-else

Case

10101100

2002-12-23 P.37

www.fpga.com.cn

SolutionEntity lab3 isPort (a,b,c,d : bit;

serial_port_data : in bit;parallel_port_data : in bit;data_out : out bit);

end lab3;Architecture netlist of lab3 issignal sel : bit;beginprocess(a,b,c,d)beginif (a='1' and b='0' and c='1' and d='0') thensel <= '0';elsif (a='1' and b='1' and c='0' and d='0') thensel <= '1';end if;end process;

process(sel,serial_port_data,parallel_port_data)beginCASE sel IS

WHEN '0' =>data_out <= serial_port_data;

WHEN '1' =>data_out <= parallel_port_data;

WHEN OTHERS =>END CASE;end process;end netlist;

2002-12-23 P.38

www.fpga.com.cn

Data Type

VHDL is a strongly

DATA TYPE ORIENT LANGUAGE

2002-12-23 P.39

www.fpga.com.cn

Type Data

VHDL is a very rigid Type Data Oriented LanguageQ : What is it means?A : Different type can not do any assignmente.g. a : in belongs to TYPE A

b : out belongs to TYPE Bb <= a; ----- ERROR

because a and b is belonging to different typesQ : Why VHDL does not allow this ?A : This is a kind of protection, so engineer will not do

different TYPE assignment by mistake

2002-12-23 P.40

www.fpga.com.cn

Q : Is that any solution for this ?A : VHDL is a powerful language, so no doubt about it,

solution is available.Q : How ?A : It is easy ...........

Wake up, don’t sleep

2002-12-23 P.41

www.fpga.com.cn

VHDL Data Type

Data Type in VHDL– Built In Data Type

• designer can free to use it, it comes with VHDL– Customer Create Data Type

• designer need to create his own Data Type

2002-12-23 P.42

www.fpga.com.cn

Built In Data Type

There are some commonly used built in Data Type available– BIT– STD_LOGIC– INTEGER

What is the different ?How to use it ?

2002-12-23 P.43

www.fpga.com.cn

BIT

Example : a : in BIT;

BIT can only have two value– ‘0’ and ‘1’

Entity example isPort (a : in bit;

b, c, d, e, f : out bit);end example;Architecture example_body of example isbeginb <= a;c <= ‘1’;d <= ‘0’;e <= ‘Z’;f <= ‘X’;end example_body;

OK! a and b are the same type BIT

OK! b can take value ‘1’ or ‘0’

ERROR! ‘Z’ and ‘X’ is notallow in BIT type

2002-12-23 P.44

www.fpga.com.cn

STD_LOGIC

Example :a : in STD_LOGIC;

STD_LOGIC can have value– ‘0’, ‘1’, ‘X’, ‘Z’– ‘X’ - - used for unknown– ‘Z’ - - high impedence used for tri-state (capital Z, not z)

There is some trick to use STD_LOGIC

2002-12-23 P.45

www.fpga.com.cn


Entity example isport ( a : in STD_LOGIC;

b, c, d, e, f : out STD_LOGIC);end example;Architecture example_body of example isbeginb <= a;c <= ‘1’;d <= ‘0’;e <= ‘X’;f < = ‘Z’;end example_body;

Must have this statementuse before any ENTITY

Define a and b areSTD_LOGIC type

OK! a and b are the same typeOK! ‘0’, ‘1’, ‘X’ and ‘Z’are valid STD_LOGIC datatype

2002-12-23 P.46

www.fpga.com.cn

More for STD_LOGICLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;Entity example isport ( a : in STD_LOGIC;

b, c : out STD_LOGIC);end example;Architecture example_body of example issignal VCC : std_logic := ‘1’;signal GND : std_logic := ‘0’;beginprocess (a)

if (a = ‘1’) thenb <= VCC;c <= GND;elseB <= GND;c <= VCC;end if;end process;end example_body;

2002-12-23 P.47

www.fpga.com.cn

INTEGER

Example :a : in integer;b : in integer range 0 to 15;

INTEGER can take any integer value– Negative, Zero, Positive

• e.g. -7, 0, 100Entity test isport ( a : in integer;

b,c : out integer);end test;architecture test_body of test isbeginb <= a;c <= 8;end test_body;

OK! a and b are the same type

OK! c can accept Integer value

2002-12-23 P.48

www.fpga.com.cn

Something more on INTEGER data type

Q : How many bit will be use for a : in integer ?A : It depend on the VHDL compiler. Altera VHDL

compiler will take 32 bitsQ : Can I have more control on the INTEGER DATA

TYPE ?A : Yes. You can control the RANGE of the INTEGER

a : in integer range 0 to 15;b : in integer range -7 to 0;c : out integer range -10 to 10;

a can accept 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15

b can accept -7, -6, -5, -4, -3, -2, -1, 0 only

c can accept -10, -9, -8.....0.....1, 2, 3, ......10

2002-12-23 P.49

www.fpga.com.cn

How many bits use for 0 to 15 ? How many bits use for -7 to 0 ?How many bits use for -10 to 10 ?

4 bits - Why ? (have 16 value)

3 bits - Why ?(have 8 value) 5 bits - Why ?

(have 32 value)

2002-12-23 P.50

www.fpga.com.cn

Bus Implementation

VHDL offers vector types to implement busesCommon vector types are– BIT_VECTOR– STD_LOGIC_VECTOR

Example of Bus Implementation

a : in bit;b : out std_logic;

BIT OPERATION

a : in bit_vector(7 downto 0);b : out std_logic_vector (0 to 3);

BUS OPERATON

Define the size of the vector (how many bits)

2002-12-23 P.51

www.fpga.com.cn

INTEGER VECTOR

Integer

a : in integer;

Bus Integer

?a : in integer_vector

Note : there is no INTEGER_VECTORBut you can create your own INTEGER VECTOR– VHDL allow you to create your own DATA TYPE

How ?Later.........

2002-12-23 P.52

www.fpga.com.cn

Bus Assignment

a : out bit_vector(3 downto 0)– a <= “1011”;– a(2) <= ‘0’;– a(0 to 1) <= “10”– a(3 downto 1) <= “100”– a(3 downto 0) <= x”A”– a <= (others=> ‘1’)

a(0) <= ‘1’a(1) <= ‘1’a(2) <= ‘0’a(3) <= ‘1’a(2) <= ‘0’

a(0) <= ‘1’a(1) <= ‘0’

a(3) <= ‘1’a(2) <= ‘0’a(1) <= ‘0’

a(3) <= ‘1’a(2) <= ‘1’a(1) <= ‘1’a(0) <= ‘1’

a(3) <= ‘1’a(2) <= ‘0’a(1) <= ‘1’a(0) <= ‘0’

2002-12-23 P.53

www.fpga.com.cn

Different Data Type Assignmenta : in std_logic_vector(3 downto 0);b : in integer range 0 to 15;c : out std_logic_vector(3 downto 0);d : out integer range 0 to 15;

c <= a;d <= b;c <= b;d <= a;

OK because c and a are the same std_logic type

OK because d and b are the same integer type

ERRORERROR because c and b are different type

ERRORERROR because d and a are different type

2002-12-23 P.54

www.fpga.com.cn

Conversion Function

Use to convert data type from STD_LOGIC <-> INTEGERConversion Function available– conv_integer

• convert std_logic_vector to integer type– conv_std_logic_vector

• convert integer to std_logic_vector type

In order to use this Conversion Function, some trick!!!

2002-12-23 P.55

www.fpga.com.cn

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;

entity test1 isport (a : in std_logic_vector (3 downto 0);

b : in integer range 0 to 15;c : out std_logic_vector (3 downt 0);d : out integer range 0 to 15);

end test1;architecture test1_body of test1 isc <= a;d <= b;c <= conv_std_logic_vector(b,4);d <= conv_integer(a);end;

must have this statementuse before any entity

convert INTEGER to STD_LOGIC_VECTOR

convertUNSIGED STD_LOGIC_VECTOR to INTEGER

2002-12-23 P.56

www.fpga.com.cn

Conversion Function Available

Conversion Function provided by the package : STD_LOGIC_ARITH.ALL

2002-12-23 P.57

www.fpga.com.cn

Conversion Function : to INTEGER

Subtype SMALL_INT is INTEGER range 0 to 1;function CONV_INTEGER(ARG : INTEGER) return INTEGER;function CONV_INTEGER(ARG : UNSIGNED) return INTEGER;function CONV_INTEGER(ARG : SIGNED) return INTEGER;function CONV_INTEGER(ARG : STD_ULOGIC) return SMALL_INT;

2002-12-23 P.58

www.fpga.com.cn

Conversion Function : to UNSIGNED

function CONV_UNSIGNED(ARG : INTEGER; SIZE : INTEGER) return UNSIGNED;function CONV_UNSIGNED(ARG : UNSIGNED; SIZE : INTEGER) return UNSIGNED;function CONV_UNSIGNED(ARG : SIGNED; SIZE : INTEGER) return UNSIGNED;function CONV_UNSIGNED(ARG : STD_ULOGIC; SIZE : INTEGER) return UNSIGNED;

Note : Places “0” in the more significant (left) bitsTruncated at the most significant (left) bits

e.g. CONV_UNSIGNED(UNSIGNED’(“110”),8) => “00000110”CONV_UNSIGNED(UNSIGNED’(“1101010”),3) => “010”

2002-12-23 P.59

www.fpga.com.cn

Conversion Function : to SIGNED

function CONV_SIGNED(ARG : INTEGER; SIZE : INTEGER) return SIGNED;function CONV_SIGNED(ARG : UNSIGNED; SIZE : INTEGER) return SIGNED;function CONV_SIGNED(ARG : SIGNED; SIZE : INTEGER) return SIGNED;function CONV_SIGNED(ARG : STD_ULOGIC; SIZE : INTEGER) return SIGNED;

Note : Sign extension in the more significant (left) bitsTruncated at the most significant (left) bits

e.g. CONV_UNSIGNED(UNSIGNED’(“110”),8) => “11111110”CONV_UNSIGNED(UNSIGNED’(“1101010”),3) => “010”

2002-12-23 P.60

www.fpga.com.cn

Conversion Function : to STD_LOGIC_VECTOR

function CONV_STD_LOGIC_VECTOR(ARG : INTEGER; SIZE : INTEGER)return STD_LOGIC_VECTOR;

function CONV_STD_LOGIC_VECTOR(ARG : UNSIGNED; SIZE : INTEGER)return STD_LOGIC_VECTOR;

function CONV_STD_LOGIC_VECTOR(ARG : SIGNED; SIZE : INTEGER)return STD_LOGIC_VECTOR;

function CONV_STD_LOGIC_VECTOR(ARG : STD_ULOGIC; SIZE : INTEGER)return STD_LOGIC_VECTOR;

2002-12-23 P.61

www.fpga.com.cn

Create your own Type

VHDL allow you to create your own data type which VHDL does not come with

2002-12-23 P.62

www.fpga.com.cn

Your first Data Typelibrary ieee;use ieee.std_logic_1164.all;PACKAGE your_own_type ISTYPE sensor IS (red, green);END your_own_type;

library ieee;use ieee.std_logic_1164.all;use work.your_own_type.all;

Entity example1 isport (light : in sensor;

go : out std_logic);end example1;architecture body_example1 of example1 isbegin

go <= '1' when light = red else'0' when light = green;

end body_example1;

You create your own type named as “SENSOR”

2002-12-23 P.63

www.fpga.com.cn

Application of your own data type

With your own data type, you can design – State Machine very easily

Green

Yellow

Red Sensor = ‘0’

ylight = ‘1’

rlight = ‘1’glight = ‘1’

2002-12-23 P.64

www.fpga.com.cn

Simulation

Green

Yellow

Red Sensor = ‘0’

ylight = ‘1’

rlight = ‘1’glight = ‘1’

type t_state is (red, yellow, green);

R G Y R

2002-12-23 P.65

www.fpga.com.cn

You can create a SUB type from existing one

Package sub_type isSUBTYPE small_integer is integer range 0 to 255;end sub_type;

use work.sub_type.all;Entity test isport (a : in small_integer;

b : out small_integer);end test;

Now, a and b is both integer type but havingmore constraint apply on it. It only allow totake integer value from “0 to 255”

2002-12-23 P.66

www.fpga.com.cn

You can create ArrayPackage sub_type isSUBTYPE small_integer is integer range 0 to 255;type regtype is ARRAY(0 to 255) of small_integer;end sub_type;

use work.sub_type.all;Entity test isport (a_array : in regtype;

b : in small_integer;c : out small_integer);

end test;Architecture body_test of test isbeginc <= a_array(small_integer);end body_test;

a_array

0

255

Note : both C and A_ARRAY must be thesame type (small_integer) in orderto do the assigment

2002-12-23 P.67

www.fpga.com.cn

Examplelibrary ieee;use ieee.std_logic_1164.all;Package array_example istype data_bus is array(31 downto 0) of std_logic;type small_bus is array(7 downto 0) of std_logic;end array_example;

library ieee;use ieee.std_logic_1164.all;use work.array_example.all;

entity extract isport (data : in data_bus;

start : in integer;data_out : out small_bus);

end extract;

architecture test of extract isbeginprocess(data, start)begin

for i in 7 downto 0 loopdata_out(i) <= data(i + start);

end loop;end process;end test;

2002-12-23 P.68

www.fpga.com.cn

Simulation Result

2002-12-23 P.69

www.fpga.com.cn

You can create multi-dimension Arraylibrary ieee;use ieee.std_logic_1164.all;Package array_example istype D1_bus is array(31 downto 0) of std_logic;type D2_bus is array(7 downto 0) of D1_bus;type D3_bus is array(0 to 3) of D2_bus;end array_example;..variable o, i : D3_bus;..i(z)(y)(x) := ‘1’o(z)(y)(x) := i(z)(y)(x);

2002-12-23 P.70

www.fpga.com.cn

LAB 4

8 bit wide 4:1 MUX

2002-12-23 P.71

www.fpga.com.cn

Design Requirement•Design an 8-bit wide 4:1 bus mux with tri-state output enable control

•Implement the multiplexer in one process •Use STD_LOGIC_VECTOR type•Use CASE statement for Process_A•Use With-Select to implement the Tri-State function

data_out(7 downto 0)output_enable_control

sel (1 downto 0)

data(31 downto 24) data(23 downto 16)data(15 downto 8)data(7 downto 0)

process_a

Multiplexer data_mux(7 downto 0)

Tri-StateCase

With-Select

2002-12-23 P.72

www.fpga.com.cn

Solutionprocess(data)begincase sel is

when "00" => data_mux <= data(7 downto 0);

when "01" =>data_mux <= data(15 downto 8);



when others =>end case;end process;With output_enable_control Selectdata_out <= data_mux when '1',

"ZZZZZZZZ" when others;end netlist;

library ieee;use ieee.std_logic_1164.all;Entity lab4 isPort (data : in std_logic_vector(31 downto 0);

sel : in std_logic_vector(1 downto 0);output_enable_control : in std_logic;data_out : out std_logic_vector(7 downto 0));

end lab4;Architecture netlist of lab4 issignal data_mux : std_logic_vector(7 downto 0);begin

2002-12-23 P.73

www.fpga.com.cn

LAB 5

State Machine

2002-12-23 P.74

www.fpga.com.cn

Design Requirement•Design a state machine that will detect a Serial pattern of “011011”

from a serial_in stream •When this pattern is detected set match = ‘1’ output for one cycle•Test your design by Input the following pattern “011101”, “011011”

MatchSerial_in

clk

VHDL StateMachineReset

011011

2002-12-23 P.75

www.fpga.com.cn

Example State Machineprocess(present_state, sensor)begin

case present_state iswhen green => next_state <= yellow;

rlight <= '0';ylight <= '0';glight <= '1';

when red => rlight <= '1';glight <= '0';ylight <= '0';if (sensor = '1') then

next_state <= green;else

next_state <= red;end if;

when yellow => next_state <= red;rlight <= '0';ylight <= '1';glight <= '0';

end case;end process;

process(clk,next_state)begin

if (clk'event and clk = '1') thenpresent_state <= next_state;end if;

end process;end body_example1; use ieee.std_logic_1164.all;

use work.your_own_type.all;

Entity example1 isport (sensor, clk : in std_logic;

rlight, ylight, glight : out std_logic);end example1;architecture body_example1 of example1 issignal present_state, next_state : t_state;begin

library ieee;use ieee.std_logic_1164.all;package your_own_type istype t_state is (red, yellow, green);end your_own_type;

MatchSerial_in

clk

VHDL StateMachineReset

011011

2002-12-23 P.76

www.fpga.com.cn

Solutionif (clk'event and clk='1') thencase present_state is

when idle => if (serial_in = '0') thenpresent_state <= state0;elsepresent_state <= idle;end if;

when state0 => if (serial_in = '1') thenpresent_state <= state01;elsepresent_state <= idle;end if;




library ieee;use ieee.std_logic_1164.all;package your_own_type istype t_state is (idle,state0,state01,state011,

state0110,state01101,state011011);

end your_own_type;library ieee;use ieee.std_logic_1164.all;use work.your_own_type.all;Entity stmh isport (clk, serial_in, reset : in std_logic;

match : out std_logic);end stmh;architecture body_stmh of stmh issignal present_state : t_state;beginprocess(clk,serial_in, present_state)beginif (reset = '1') thenpresent_state <= idle;else



when others => present_state <= idle;end case;end if;end if;end process;process(present_state)beginif (present_state = state011011) thenmatch <= '1';elsematch <= '0';end if;end process;end body_stmh;

2002-12-23 P.77

www.fpga.com.cn

Simulation Result

2002-12-23 P.78

www.fpga.com.cn

Subprogram

2002-12-23 P.79

www.fpga.com.cn

What is Subprogram

In all kind of program language, e.g C, Pascal etc. can support subroutine (subprogram) VHDL also support this function with the same concept apply– a routine which use a lot within your design, so you can

simplify you coding by using SubProgram• Procedure

– can return more than one argument– parameters can be input/output/inout parameters

• Function– always returns just one argument– all parameters are input parameters

2002-12-23 P.80

www.fpga.com.cn

Example of Functionlibrary ieee;use ieee.std_logic_1164.all;Package num_types istype log8 is array(0 to 7) of std_logic;end num_types;

library ieee;use ieee.std_logic_1164.all;use work.num_types.all;

entity convert isport(i1, i2 : in log8;

o1, o2 : out integer);end convert;

architecture behave of convert isFUNCTION std_logic_array_to_integer(s : log8)RETURN integer isvariable result : integer;beginresult := 0;

for i in 0 to 7 loopresult := result * 2;

if s(i) = '1' thenresult := result + 1;end if;

end loop;return result;end std_logic_array_to_integer;

begino1 <= std_logic_array_to_integer(i1);o2 <= std_logic_array_to_integer(i2);end behave;

one codingcan serve twoplace (it helpsave you codingtime and easyto modify andtiny........)

2002-12-23 P.81

www.fpga.com.cn

Example of Procedurelibrary ieee;use ieee.std_logic_1164.all;package intpack issubtype small_integer is integer range 0 to 99;type bus_stat_vec is array(0 to 8) of small_integer;procedure bus_average(x : inout bus_stat_vec);end intpack;

package body intpack isprocedure bus_average(x : inout bus_stat_vec) isvariable sum, average : integer;beginsum := 0; for i in 0 to 7 loopsum := sum + x(i);end loop;average := sum;x(8) := average;end bus_average;end intpack;

library ieee;use ieee.std_logic_1164.all;use work.intpack.all;entity intave isport (clk : in std_logic;

a,b,c,d,e,f,g,h : small_integer;average : out integer);

end intave;architecture body_intave of intave isbegin

process(clk)variable input_value : bus_stat_vec;begininput_value(0) := a;input_value(1) := b;input_value(2) := c;input_value(3) := d;input_value(4) := e;input_value(5) := f;input_value(6) := g;input_value(7) := h;bus_average(input_value);if (clk'event and clk = '1') thenaverage <= input_value(8);end if;

end process;end body_intave;

2002-12-23 P.82

www.fpga.com.cn

Simulation

2002-12-23 P.83

www.fpga.com.cn

Counter with Asyn. “CLEAR”Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;Entity counter isport (clk, clear : in bit;

q : out std_logic_vector(7 downto 0));end counter;ARCHITECTURE example OF counter ISBEGIN

PROCESS (clk,clear)VARIABLE count : std_logic_vector (7 downto 0);BEGINIF (clear = ‘1’) THENcount := “00000000”;

elsif (clk’event and clk = '1’) THENcount := count + 1;END IF;

q <= count;END PROCESS;

END example;

2002-12-23 P.84

www.fpga.com.cn

Simulation Result

2002-12-23 P.85

www.fpga.com.cn

Tri-State Bufferand

Bi-Directional I/O pin

2002-12-23 P.86

www.fpga.com.cn

How to write a Tri-State Bufferlibrary ieee;use ieee.std_logic_1164.all;

entity tri_state isport (control : in std_logic;

q : out std_logic);end tri_state;architecture body_tri of tri_state isbeginprocess(control)beginif (control = '1') thenq <= '0';elseq <= 'Z';end if;end process;end body_tri;

2002-12-23 P.87

www.fpga.com.cn

Bi-Directional Pinlibrary ieee;use ieee.std_logic_1164.all;

entity tri_state isport (control, in1 : in std_logic;

q : inout std_logic;x : out std_logic);

end tri_state;architecture body_tri of tri_state isbeginprocess(control,q,in1)beginif (control = '0') thenx <= q;elseq <= in1;end if;end process;end body_tri;

Right or Wrong ??

2002-12-23 P.88

www.fpga.com.cn

How to handle Bi-Directional Pinlibrary ieee;use ieee.std_logic_1164.all;

entity tri_state isport (control, in1 : in std_logic;

q : inout std_logic;x : out std_logic);

end tri_state;architecture body_tri of tri_state isbeginprocess(control,q,in1)beginif (control = '0') thenx <= q;q <= 'Z';elseq <= in1;x <= q;end if;end process;end body_tri;

2002-12-23 P.89

www.fpga.com.cn

LAB 6

Design a v74699 in VHDL code

2002-12-23 P.90

www.fpga.com.cn

What is v74699 (74699)

SynchronousLoad

Hold the currentstate

Ignore thistwo function

2002-12-23 P.91

www.fpga.com.cn

Sample CodingLibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;Entity counter isport (cclk, cclrn, gn, ldn, u_dn : in bit;

d : in std_logic_vector(3 downto 0);q : out std_logic_vector(3 downto 0));

end counter;ARCHITECTURE example OF counter ISsignal count : std_logic_vector (3 downto 0);BEGIN

process(count,gn)beginif (gn = '0') thenq <= "ZZZZ";elseq <= count;end if;end process;END example;

PROCESS (cclk, cclrn, ldn, u_dn)BEGIN

if (cclk'event and cclk = '1') thenif cclrn = '0' thencount <= "0000";elsif (ldn = '0') thencount <= d;elsif (u_dn = '1') thencount <= count + 1;elsif (u_dn = '0') thencount <= count - 1;elsecount <= count;end if;

end if;END PROCESS;

2002-12-23 P.92

www.fpga.com.cn

Simulation Result

2002-12-23 P.93

www.fpga.com.cn

LAB 7

Design a 74245 (v74245) in VHDL

2002-12-23 P.94

www.fpga.com.cn

Sample CodeLibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;Entity v74245 isport (dir, oe : in bit;

a, b : inout std_logic_vector(7 downto 0));end v74245;ARCHITECTURE example OF v74245 ISBEGIN

process(a,b,dir,oe)beginif (oe = '1') thenif (dir = '1') thenb <= a;a <= (others => 'Z');elsea <= b;b <= (others => 'Z');end if;elsea <= (others => 'Z');b <= (others => 'Z');end if;end process;END example;

2002-12-23 P.95

www.fpga.com.cn

Simulation Result

2002-12-23 P.96

www.fpga.com.cn

Design a simple ALU

2002-12-23 P.97

www.fpga.com.cn

Example of ALUlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;

package instr istype instruction is (add, sub, lda, ldb, sta,

stb, rda, rdb, outa, xfr);subtype intrange is integer range 0 to 7;end instr;

library ieeee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use work.instr.all;entity i8031 isport (clk : in std_logic;

instr : in instruction;addr,datain : in intrange;dataout : out intrange);

end i8031;architecture i8031_body of i8031 isbegin

process(instr)beginif (clk’event and clk=‘1’) thencase instr is

when lda => a := datain;when ldb => b := datain;when add => a := a + b;when sub => a := a - b;when sta => reg(addr) := a;when stb => reg(addr) := b;when rda => a := reg(addr);when rdb => b := reg(addr);when outa => dataout <= a;when xfr => a := b;

end case;end if;end process;end i8031_body;

2002-12-23 P.98

www.fpga.com.cn

Anything Wronglibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;

package instr istype instruction is (add, sub, lda, ldb, sta,

stb, rda, rdb, outa, xfr);subtype intrange is integer range 0 to 7;end instr;

library ieeee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use work.instr.all;entity i8031 isport (clk : in std_logic;

instr : in instruction;addr,datain : in intrange;dataout :out intrange);

end i8031;architecture i8031_body of i8031 isbegin

process(instr)beginif (clk’event and clk=‘1’) thencase instr is

when lda => a := datain;when ldb => b := datain;when add => a := a + b;when sub => a := a - b;when sta => reg(addr) := a;when stb => reg(addr) := b;when rda => a := reg(addr);when rdb => b := reg(addr);when outa => dataout <= a;when xfr => a := b;

end case;end if;end process;end i8031_body;

2002-12-23 P.99

www.fpga.com.cn

Simulate with this patternCommand a b dataout

x xlda datain=4 4 xldb datain=3 4 3add 7 3ldb datain=2 7 2sub 5 2xfr 2 5sta addr=5stb addr=1lda datain=0 0 5ldb datain=0 0 0rda addr=5 2 0rdb addr=1 2 5

outa 2xfr 5 2

outa 5

2002-12-23 P.100

www.fpga.com.cn

LAB 8

Modify the ALU and simulate it

2002-12-23 P.101

www.fpga.com.cn

New ALUif (clk'event and clk='1') thencase instr is

when lda => storea <= datain;when ldb => storeb <= datain;when add => a := storea + storeb;

storea <= a;when sub => a := storea - storeb;

storea <= a;when sta => storereg(addr) <= storea;when stb => storereg(addr) <= storeb;when rda => storea <= storereg(addr);when rdb => storeb <= storereg(addr);when outa => dataout <= storea;when xfr => a := storea;

b := storeb;storeb <= a;storea <= b;

when others=> null; end case;end if;end process;end i8031_bo;

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use work.instr.all;

entity i8031 isport (clk : in std_logic;

instr : in instruction;addr : in intrange;datain : in intrange;dataout : out intrange);

end i8031;architecture i8031_bo of i8031 issignal storea, storeb : intrange;signal storereg : regtype;beginprocess(clk,instr,addr,datain)variable a, b : intrange;begin

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;

package instr istype instruction is (add, sub, lda, ldb,

sta, stb, rda, rdb, outa, xfr);

subtype intrange is integer range 0 to 7;type regtype is ARRAY(0 to 7) of intrange;end instr;

2002-12-23 P.102

www.fpga.com.cn

Simulation Result

2002-12-23 P.103

www.fpga.com.cn

Constant Assignment for the User Define Type

2002-12-23 P.104

www.fpga.com.cn

What is the state value

In the previous ALU example, there are couple state– add, sub, lda, ldb, sta, stb, rda, rdb, outa, and xfr

Max+Plus II will assign the state value as0 add1 sub2 lda3 ldb4 sta5 stb6 rda7 rdb8 outa9 xfr

2002-12-23 P.105

www.fpga.com.cn

But

But for some reason, I want to control the assignment as

The answer is YES !

5 add4 sub3 lda2 ldb1 sta0 stb9 rda8 rdb7 outa6 xfr

2002-12-23 P.106

www.fpga.com.cn

Sample Codelibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;package instr isconstant add :std_logic_vector(3 downto 0) :="0101";constant sub :std_logic_vector(3 downto 0) :="0100";constant lda :std_logic_vector(3 downto 0) :="0011";constant ldb :std_logic_vector(3 downto 0) :="0010";constant sta :std_logic_vector(3 downto 0) :="0001";constant stb :std_logic_vector(3 downto 0) :="0000";constant rda :std_logic_vector(3 downto 0) :="1001";constant rdb :std_logic_vector(3 downto 0) :="1000";constant outa :std_logic_vector(3 downto 0):="0111";constant xfr :std_logic_vector(3 downto 0) :="0110";subtype intrange is integer range 0 to 7;type regtype is ARRAY(0 to 7) of intrange;end instr;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use work.instr.all;

entity i8031 isport (clk : in std_logic;instr : in std_logic_vector(3 downto 0);addr : in intrange;datain : in intrange;dataout : out intrange);end i8031;architecture i8031_bo of i8031 issignal storea, storeb : intrange;signal storereg : regtype;beginprocess(clk,instr,addr,datain)variable a, b : intrange;beginif (clk'event and clk='1') thencase instr is

when lda => storea <= datain;when ldb => storeb <= datain;when add => a := storea + storeb;

storea <= a;when sub => a := storea - storeb;

storea <= a;when sta => storereg(addr) <= storea;when stb => storereg(addr) <= storeb;when rda => storea <= storereg(addr);

when rdb => storeb <= storereg(addr);when outa => dataout <= storea;when xfr => a := storea;

b := storeb;storeb <= a;storea <= b;

when others=> null; end case;end if;end process;end i8031_bo;

2002-12-23 P.107

www.fpga.com.cn

Simulate the following patternCommand a b dataout

x xlda(3) datain=4 4 xldb(2) datain=3 4 3add(5) 7 3ldb(2) datain=2 7 2sub(4) 5 2xfr(6) 2 5sta(1) addr=5stb(0) addr=1lda(3) datain=0 0 5ldb(2) datain=0 0 0rda(9) addr=5 2 0rdb(8) addr=1 2 5outa(7) 2xfr(6) 5 2

outa(7) 5

2002-12-23 P.108

www.fpga.com.cn

Simulation Result

2002-12-23 P.109

www.fpga.com.cn

Hierarchy Design

2002-12-23 P.110

www.fpga.com.cn

Multiple Design Files

• VHDL allows hierarchical design through component component instantiationinstantiation

top.vhdentity-architecture “top”component “mid_a”component “mid_b”

mid_a.vhdentity-architecture “mid_a”component “bottom_a”

mid_b.vhdentity-architecture “mid_b”component “bottom_a”component “bottom_b”

bottom_a.vhdentity-architecture “bottom_a”

bottom_b.vhdentity-architecture “bottom_b”

2002-12-23 P.111

www.fpga.com.cn

Hierarchy Design Example

TOP

SEGMENT7

SEG7

2002-12-23 P.112

www.fpga.com.cn

Exampleentity top isport (i : in bit_vector(3 downto 0);

clk : in bit;out_seg : out bit_vector(6 downto 0));

end top;architecture top_body of top iscomponent segment7port (ii : in bit_vector(3 downto 0);

segg: out bit_vector(6 downto 0));end component;signal ri : bit_vector(3 downto 0);signal rout_seg : bit_vector(6 downto 0);beginprocess(clk,i)beginif (clk'event and clk='1') thenri(3 downto 0) <= i(3 downto 0);out_seg(6 downto 0) <= rout_seg(6 downto 0);end if;end process;u1:segment7port map (ii=>ri, segg=>rout_seg);end top_body;

entity segment7 isport (ii : in bit_vector(3 downto 0);

segg : out bit_vector(6 downto 0));end segment7;architecture segment7_body of segment7 iscomponent seg7port (iii : in bit_vector(3 downto 0);

seg : out bit_vector(6 downto 0));end component;beginu1:seg7port map (iii=>ii, seg=>segg);end segment7_body;

2002-12-23 P.113

www.fpga.com.cn

cont...entity seg7 isport (iii : in bit_vector(3 downto 0);

seg : out bit_vector(6 downto 0));end seg7;architecture body_seg7 of seg7 isbeginprocess(iii)beginif (iii = "000") thenseg <= "1111110";elsif (iii = "001") thenseg <= "0110000";elsif (iii = "010") thenseg <= "1101101";elsif (iii = "011") thenseg <= "1111001";elseseg <= "0000000";end if;end process;end body_seg7;

2002-12-23 P.114

www.fpga.com.cn

ReviewEntity Mother isport (mother_in1, mother_in2 : in bit;

mother_out1 : out bit);end Mother;Architecture mother_body of mother iscomponent Sonport (son_in1, son_in2 : in bit;

son_out1 : out bit);end component;beginu1:Sonport map(son_in1 mother_in1, son_in2 mother_in2,

son_out1 mother_out1);..........end mother_body;

Entity Son isport (son_in1, son_in2 : in bit;

son_out1 : out bit);end son;Architecture son_body of son isbeginson_out1 <= son_in1 and son_in2;end son_body;

2002-12-23 P.115

www.fpga.com.cn

LAB 9

Up/Load Counter

2002-12-23 P.116

www.fpga.com.cn

Design Requirement

Top_levl.vhd

count8

qloadenableup/downclear

Create a simple 8-bit counter with- sync load (“10100101”)- sync clear- sync up/down- enable

Create a top-level design and instantiate your counter

2002-12-23 P.117

www.fpga.com.cn

SolutionLibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;Entity counter isport (clk, clear, load, enable, up_down : in bit;

q : out std_logic_vector(7 downto 0));end counter;ARCHITECTURE counter_body OF counter ISBEGINprocess (clk,clear,load,enable,up_down)VARIABLE count : std_logic_vector (7 downto 0);BEGINif (clk’event and clk=‘1’) then

if (clear = ‘1’) thencount := “00000000”elsif (load = ‘1’) thencount := “10100101”;elsif (enable = ‘1’ and up_down = ‘1’) thencount := count + 1;elsif (enable = ‘1’ and up_down = ‘0’) thencount := count - 1;end if

end if;q <= count;end process;end counter_body;

Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;Entity top isport (clk, clear, load, enable, up_down : in bit;

q : out std_logic_vector(7 downto 0));end counter;ARCHITECTURE top_body OF top ISBEGINu1:counterport map (clk=>clk, clear=>clear, load=>load,

enable=>enable, up_down=>up_down,q=>q);

end top_body;

2002-12-23 P.118

www.fpga.com.cn

VHDL Also Support Parameterize

2002-12-23 P.119

www.fpga.com.cn

Bit to Integer Conversionlibrary ieee;use ieee.std_logic_1164.all;entity vmux isgeneric (number_bit : integer);port (indata : in bit_vector(number_bit-1 downto 0);

q : out integer);end vmux;architecture vmux_body of vmux isbeginprocess(indata)variable temp : integer;begintemp := 0;for i in number_bit-1 downto 0 loop

if (indata(i) = '0') thentemp := temp*2 + 0;elsetemp := temp*2 + 1;end if;

end loop;q <= temp;end process;end vmux_body;

library ieee;use ieee.std_logic_1164.all;

entity top isport (indata : in bit_vector(3 downto 0);

q : out integer);end top;architecture top_body of top iscomponent vmuxgeneric(number_bit : integer);port (indata : in bit_vector(number_bit-1 downto 0);

q : out integer);end component;beginu1:vmuxgeneric map (number_bit=> 4)port map(indata=>indata, q=>q);end top_body;

2002-12-23 P.120

www.fpga.com.cn

Simulation Result

2002-12-23 P.121

www.fpga.com.cn

LAB 10

Design a Variable Shift Register which support

Different Number Of Bits&

Different Level of Shift

2002-12-23 P.122

www.fpga.com.cn

Graphic

2002-12-23 P.123

www.fpga.com.cn

Sample Codinglibrary ieee;use ieee.std_logic_1164.all;entity vdff isgeneric (number_bit : integer;

level : integer);port (clk : in bit;

d : in bit_vector(number_bit-1 downto 0);q : out bit_vector(number_bit-1 downto 0));

end vdff;architecture vdff_body of vdff istype reg_array is array (level-1 downto 0) of bit_vector(number_bit-1 downto 0);begin.......end vdff_body;

2002-12-23 P.124

www.fpga.com.cn

Sample Codinglibrary ieee;use ieee.std_logic_1164.all;entity vdff isgeneric (number_bit : integer;

level : integer);port (clk : in bit;


end vdff;architecture vdff_body of vdff istype reg_array is array (level-1 downto 0) of bit_vector(number_bit-1 downto 0);signal temp : reg_array;beginprocess(d,clk)beginif (clk'event and clk='1') thentemp(0) <= d;

for i in 1 to level-1 looptemp(i) <= temp(i-1); end loop;

q <= temp(level-1);end if;end process;end vdff_body;

2002-12-23 P.125

www.fpga.com.cn

library ieee;use ieee.std_logic_1164.all;

entity top isport (clk : in bit;

d : in bit_vector(3 downto 0);q : out bit_vector(3 downto 0));

end top;architecture top_body of top iscomponent vdffgeneric(number_bit, level : integer);port (clk : in bit;


end component;beginu1:vdffgeneric map (number_bit=> 4, level=>5)port map(clk=>clk, d=>d, q=>q);end top_body;

2002-12-23 P.126

www.fpga.com.cn

Simulation Result

2002-12-23 P.127

www.fpga.com.cn

Any Problem ?

2002-12-23 P.128

www.fpga.com.cn

Simple VHDLLIBRARY IEEE;USE IEEE.std_logic_1164.all;ENTITY clock ISPORT(clk: OUT std_logic);END;ARCHITECTURE behaviour OF clock ISBEGINstart: PROCESSBEGINclk<= '1';wait for 67.7 ns;clk<= '0';wait for 33.8 ns;END PROCESS;END behaviour;

2002-12-23 P.129

www.fpga.com.cn

Simulate by VHDL simulator

It generate a 66.7 ns HIGH and 33.8 ns LOW

2002-12-23 P.130

www.fpga.com.cn

Compile by Max+Plus II

Convert the design to PLD

2002-12-23 P.131

www.fpga.com.cn

Compile by Synplicity

2002-12-23 P.132

www.fpga.com.cn

Compile by Synopsys FPGA Express

2002-12-23 P.133

www.fpga.com.cn

Compile by Exemplar Galileo

2002-12-23 P.134

www.fpga.com.cn

What happen

VHDL is a very powerful language, but– something can be simulate but doesn’t means it can convert

to Hardware

start: PROCESSBEGINclk<= '1';wait for 66.7 ns;clk<= '0';wait for 33.8 ns;END PROCESS;

How to convert it to Hardware ?

??????

2002-12-23 P.135

www.fpga.com.cn

Conclusion

VHDL is a very powerful languageYou have learn– Concurrent Statement

• Signal Assigment• Conditional Signal Assigment• Selected Signal Assigment

– Process Statement• If-Then-Else• Case-when• For-Loop

2002-12-23 P.136

www.fpga.com.cn

Cont...

Data Type– Create your own Data Type

• memory array• state machine

Signal vs Variable differentFunction and ProcedureHierarchical DesignParameterized VHDL Code

2002-12-23 P.137

www.fpga.com.cn

Do you need more training?

All Is Here :

www.fpga.com.cnThe Top Chinese FPGA Website

Documents

VHDL Intermediate Level - PLDWorld.com · • 2 : Q, QB – The FUNCTION of the device ... WITH sel SELECT q