VHDL Data Types

VHDL Data Types

Suresh Balpande

www.sbalpande.webs.com


VHDL Data Types


VHDL Data TypesScalar

IntegerEnumeratedReal (floating point)*Physical*

CompositeArrayRecord

Access (pointers)*

* Not supported by synthesis tools


Predefined Data Types

bit (0 or 1)

bit_vector (array of bits)

integer integer

real

time (physical data type)


Data

Enumeration:Red, blue

Boolean:TRUE, FALSE

Bit:Float:

standard logic:

Resolved, Unresolved

Different data types

Data types

Bit:0,1

Charactera,b

String:text

Integer:13234,23

Float:0.124


Examples of some common types

Type BOOLEAN is (FALSE, TRUE)

type bit is (0 ,1);

type character is (-- ascii string)type character is (-- ascii string)

type INTEGER is range of integer numbers

type REAL is range of real numbers


VHDL Data Objects

Constant

Variable

SignalSignal

File*



Identifiers

May contain A-Z, a-z, 0-9, _

Must start with letter

May not end with _May not end with _

May not include two consecutive _

VHDL is case insensitiveSel sel and SEL refer to same object


Identifier Examples

A2G

valid

8bit_counter

invalid -- starts with numberinvalid -- starts with number

_NewValue

invalid -- starts with _

first#

invalid -- illegal character


Characters and Strings

CharactersA, 0, 1, $, x, *

StringsStringsstring of characters

00101101

0X110ZZ1



Bit StringsB011111010110

O3726

X7D6


Integer Data Type

Integer

Minimum range for any implementation as defined by standard: - 2,147,483,647 to 2,147,483,647

Example assignments to a variable of type integer :ARCHITECTURE test_int OF test ISBEGIN

PROCESS (X)VARIABLE a: INTEGER;

BEGINa := 1; -- OKa := -1; -- OKa := 1.0; -- illegal

END PROCESS;END test_int;

ARCHITECTURE test_int OF test ISBEGIN

PROCESS (X)VARIABLE a: INTEGER;

BEGINa := 1; -- OKa := -1; -- OKa := 1.0; -- illegal

END PROCESS;END test_int;


Integer Data Type

Minimum range for any implementation: -2,147,483,647 to 2,147,483,647Define range of integer

minimizes synthesized logicminimizes synthesized logic

type CountValue is range 0 to 15;type Twenties is range 20 to 29;type Thirties is range 39 downto 30;


Example of Integer Data Type

process(addr)variable j: integer range 0 to 35;variable addru: unsigned(7 downto 0);beginfor i in 7 downto 0 loopfor i in 7 downto 0 loop

addru(i) := addr(i);end loop;j := conv_integer(addru);M

Enumeration types:

An enumeration type is defined by listing (enumerating) all possible values

Examples:

type COLOR is (BLUE, GREEN, YELLOW, RED);

type MY_LOGIC is (0, 1, U, Z);

-- then MY_LOGIC can be one of the 4 values


TYPE binary IS ( ON, OFF );... some statements ...TYPE binary IS ( ON, OFF );... some statements ...

VHDL Data Types

Scalar Types (Cont.)Enumerated

User specifies list of possible values

Example declaration and usage of enumerated data type :

... some statements ...ARCHITECTURE test_enum OF test ISBEGIN

PROCESS (X)VARIABLE a: binary;

BEGINa := ON; -- OK... more statements ...a := OFF; -- OK... more statements ...

END PROCESS;END test_enum;

... some statements ...ARCHITECTURE test_enum OF test ISBEGIN

PROCESS (X)VARIABLE a: binary;

BEGINa := ON; -- OK... more statements ...a := OFF; -- OK... more statements ...

END PROCESS;END test_enum;


Exercises

Example of the enumeration type of the menu of a restaurant:type food is (hotdog, tea, sandwich, cake, chick_wing);

(a) Declare the enumeration type of the traffic light.Answer: _______________________________________

(b) Declare the enumeration type of the outcomes of rolling a dice. dice.

Answer: _______________________________________(c) Declare the enumeration type of the 7 notes of music.

Answer: _______________________________________


Physical Physical

Can be user defined range

Physical type example

Time units are the only predefined physical type in VHDL.


Physical Physical

Can be user defined range

Physical type example

Current in Amp, mA.,


Predefined physical data type


ARCHITECTURE test_real OF test ISARCHITECTURE test_real OF test IS

VHDL Data TypesScalar Types (Cont.)

Real

Minimum range for any implementation as defined by standard: -1.0E38 to 1.0E38

Example assignments to a variable of type real :

ARCHITECTURE test_real OF test ISBEGIN

PROCESS (X)VARIABLE a: REAL;

BEGINa := 1.3; -- OKa := -7.5; -- OKa := 1; -- illegala := 1.7E13; -- OKa := 5.3 ns; -- illegal

END PROCESS;END test_real;

ARCHITECTURE test_real OF test ISBEGIN

PROCESS (X)VARIABLE a: REAL;

BEGINa := 1.3; -- OKa := -7.5; -- OKa := 1; -- illegala := 1.7E13; -- OKa := 5.3 ns; -- illegal

END PROCESS;END test_real;


PhysicalRequire associated unitsRange must be specifiedExample of physical type declaration :

VHDL Data TypesScalar Types (Cont.)

Time is the only physical type predefined in VHDL standard

TYPE resistance IS RANGE 0 TO 10000000

UNITSohm; -- ohmKohm = 1000 ohm; -- i.e. 1 KWMohm = 1000 kohm; -- i.e. 1 MWEND UNITS;

TYPE resistance IS RANGE 0 TO 10000000

UNITSohm; -- ohmKohm = 1000 ohm; -- i.e. 1 KWMohm = 1000 kohm; -- i.e. 1 MWEND UNITS;


Booleanstype boolean is (false, true);variable A,B,C: boolean;C := not AC := A and BC := A and BC := A or BC := A nand BC := A nor BC := A xor BC := A xnor B


Bits

type bit is (0, 1);signal x,y,z: bit;x

Standard Logic

type std_ulogic is ( U, -- UninitializedX -- Forcing unknown0 -- Forcing zero

library IEEE;use IEEE.std_logic_1164.all;

0 -- Forcing zero1 -- Forcing oneZ -- High impedanceW -- Weak unknownL -- Weak zeroH -- Weak one-); -- Dont care


Standard Logic

type std_ulogic is unresolved.

Resolved signals provide a mechanismfor handling the problem of multiplefor handling the problem of multipleoutput signals connected to one signal.

subtype std_logic is resolved std_ulogic;


Resolved logic concept(Multi-value Signal logic)

Can the outputs be connected together?

C1C1

C2

??


Resolved signal concept

Signal c1,c2, b1: bit;

b1

Type Std_logic and std_ulogic

Std_logic is a type of resolved logic, that means a signal can be driven by 2 inputscan be driven by 2 inputs

std_ulogic: (the u: means unresolved) Std_ulogic type is unresolved logic, that means a signal cannot be driven by 2 inputs


VHDL Data TypesComposite TypesArray

Used to group elements of the same type into a single VHDL object

Range may be unconstrained in declaration

Range would then be constrained when array is used

Example declaration for one-dimensional array (vector) :

TYPE data_bus IS ARRAY(0 TO 31) OF BIT;TYPE data_bus IS ARRAY(0 TO 31) OF BIT;

VARIABLE X : data_bus;VARIABLE Y : BIT;

Y := X(12); -- Y gets value of element at index 12

VARIABLE X : data_bus;VARIABLE Y : BIT;


0 31

0 1

...element indices...

...array values...


Example one-dimensional array using DOWNTO :

TYPE reg_type IS ARRAY(15 DOWNTO 0) OF BIT;TYPE reg_type IS ARRAY(15 DOWNTO 0) OF BIT;

15 0...element indices...

VHDL Data TypesComposite Types (Cont.)

DOWNTO keyword must be used if leftmost index is greater than rightmost index

Big-endian bit ordering, for example

VARIABLE X : reg_type;VARIABLE Y : BIT;


VARIABLE X : reg_type;VARIABLE Y : BIT;


15 0

0 1

...element indices...

...array values...


VHDL Data TypesComposite Types (Cont.)

Records

Used to group elements of possibly different types into a single VHDL object

Elements are indexed via field names

Examples of record declaration and usage :

TYPE binary IS ( ON, OFF );TYPE switch_info IS

RECORDstatus : BINARY;IDnumber : INTEGER;

END RECORD;

VARIABLE switch : switch_info;switch.status := ON; -- status of the switchswitch.IDnumber := 30; -- e.g. number of the switch

TYPE binary IS ( ON, OFF );TYPE switch_info IS

RECORDstatus : BINARY;IDnumber : INTEGER;

END RECORD;

VARIABLE switch : switch_info;switch.status := ON; -- status of the switchswitch.IDnumber := 30; -- e.g. number of the switch

Examples of record declaration and usage :


VHDL Data Types

Suresh Balpande




VHDL Data Types



VHDL Data Types
Scalar
Integer

Enumerated

Real (floating point)*

Physical*
Composite
Array

Record
Access (pointers)*



Predefined Data Types
bit (0 or 1)bit_vector (array of bits)integerrealtime (physical data type)


Different data types



Examples of some common types
Type BOOLEAN is (FALSE, TRUE)type bit is (0 ,1);type character is (-- ascii string)type INTEGER is range of integer numberstype REAL is range of real numbers


VHDL Data Objects
ConstantVariableSignalFile*



Identifiers
May contain A-Z, a-z, 0-9, _Must start with letterMay not end with _May not include two consecutive _VHDL is case insensitive
Sel sel and SEL refer to same object



Identifier Examples
A2Gvalid8bit_counterinvalid -- starts with number_NewValueinvalid -- starts with _first#invalid -- illegal character


Characters
A, 0, 1, $, x, *
Strings
string of characters

00101101

0X110ZZ1



Bit Strings
B011111010110

O3726

X7D6



Integer Data Type
Integer
Minimum range for any implementation as defined by standard: - 2,147,483,647 to 2,147,483,647

Example assignments to a variable of type integer :

ARCHITECTURE test_int OF test IS

BEGIN

PROCESS (X)

VARIABLE a: INTEGER;

BEGIN

a := 1; -- OK

a := -1; -- OK

a := 1.0; -- illegal

END PROCESS;

END test_int;



Integer Data Type
Minimum range for any implementation: - 2,147,483,647 to 2,147,483,647Define range of integer
minimizes synthesized logic
type CountValue is range 0 to 15;type Twenties is range 20 to 29;type Thirties is range 39 downto 30;


Example of Integer Data Type

process(addr)

variable j: integer range 0 to 35;

variable addru: unsigned(7 downto 0);

begin

for i in 7 downto 0 loop

addru(i) := addr(i);

end loop;

j := conv_integer(addru);

M

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VHDL Data Types