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Dr. Ahmed H. Madian-VLSI 1
Very Large Scale Integration (VLSI)
Dr. Ahmed H. [email protected]
Lecture 2
Dr. Ahmed H. Madian-VLSI 2
Contents
Wiring tracks Circuit characterization & performance
Resistance estimation Capacitance estimation Inductance estimation
Delay estimation Simple RC model Penfield-Rubenstein Model
Delay minimization techniques Transistor sizing Distributed drivers Large driver
Wiring techniques
3
Types of Design Rules
Scalable Design Rules (e.g. SCMOS)
Based on scalable “coarse grid” - l (lambda)
Idea: reduce l value for each new process, but keep rules the same
Key advantage: portable layout
Key disadvantage: not everything scales the same
Not used in “real life”
Absolute Design Rules
Based on absolute distances (e.g. 0.75µm)
Tuned to a specific process (details usually proprietary)
Complex, especially for deep submicron
Layouts not portable
Dr. Ahmed H. Madian-VLSI
4
SCMOS Design Rules
Intended to be Scalable
Original rules: SCMOS
Submicron: SCMOS-SUBM
Deep Submicron: SCMOS-DEEP
Authoritative Reference: www.mosis.org
Dr. Ahmed H. Madian-VLSI
Dr. Ahmed H. Madian-VLSI 5
Contents
Wiring tracks Circuit characterization & performance
Resistance estimation Capacitance estimation Inductance estimation
Dr. Ahmed H. Madian-VLSI 6
Wiring Tracks
A wiring track space required for a wire
4l width, 4l spacing from the neighbor=8 l
Transistor consumes one wiring track
4l
4l
4l
4l
Dr. Ahmed H. Madian-VLSI 7
Area Estimation
Estimate Area by Counting wiring tracks
Multiply by 8 (4Width + 4Spacing) to express in l
40l
32l
Dr. Ahmed H. Madian-VLSI 8
Latch up
Latch up is a condition that can occur in a circuit fabricated in a bulk CMOS technology.
N+ N+ P+ P+
VDDGND
N-well
P
N
P
N
VDD
Dr. Ahmed H. Madian-VLSI 9
P-substrate
Latch up Prevention
This could be corrected by: Include an N-well contact every time a pFET is connected to VDD
Include an p-substrate contact every time a NFET is connected to GND
N+ N+ P+ P+
VDDGND
N-well
VDDGND
Dr. Ahmed H. Madian-VLSI 10
Circuit characterization & performance
Resistance estimation
Capacitance estimation
Inductance estimation
11
Parastic Elements
So far, we’ve concentrated on getting circuit elements that we want for digital design
Transistors
Wires
Parasitics - occur whether we want them or not
Capacitors
Resistors
Transistors (bipolar and FET)
Dr. Ahmed H. Madian-VLSI 12
Resistance estimation
Resistance of uniform slab can be given as,
Where = resistivity
t= thickness
l= conductor length
w=conductor width
or,
Rs is the sheet resistance /
ohmsw
l
tR .
ohmsw
lRR s .
I
l
t
w
Dr. Ahmed H. Madian-VLSI 13
Resistance estimation (cont.)
Resistance of certain layers
Rs (/)Material
0.03metal
15100Poly
80Diffusion p
35Diffusion n
24Silicide
1K 5KN-well
Dr. Ahmed H. Madian-VLSI 14
Resistance estimation
For MOSFET channel resistance
Rchannel = RSheet (L/W)
where Rsheet = 1/µCOX(Vgs-Vt)
For P and n channels
Rsheet = 1000 ->30,000 /
N+ N +L
channel
L
W
Dr. Ahmed H. Madian-VLSI 15
Resistance estimation (cont.) Resistance of non rectangular regions
W1
W2
W2
W1
W2
W1
L
Ratio = 2L/(L+2W1)
L
W
Ratio =L/W Ratio =L/W
W2
W1
L
Ratio =W1/W2
W2 W2
W1
W1
Ratio =W2/W1
16
Resistance Depends on resistivity of material (Rho)
Sheet resistance Rs = /t
Resistance R = Rs * L / W
Corner approximation - count a corner as half a square
Corner (1/2 Square)
Corner (1/2 Square) 1/2 Square
Corner (1/2 Square)
1/2 Square
Example:
R = Rs(poly) * 13 + 2*(1/2) + 3*(1/2) squares
R = 4Ω/sq * 15.5 squares = 62Ω
Resistance Layout
20Kohm(10 μm long) 2Mohm (1000μm long)
Dr. Ahmed H. Madian-VLSI 17
Dr. Ahmed H. Madian-VLSI 18
Inverter resistance estimation
CMOS inverter (no static current)
Switching current
VDD
Vin
VGS
VOUT = VDSIL
IDS
MP
MN
Vin Vout
VDD
Rs,p (L/W)
Rs,n (L/W)
351025
1
,,max
,,
max
DDDD
nsps
DD
nsps
DD
total
DD
VV
RR
VI
WLfor
W
LR
W
LR
V
R
VI
35.
2
maxDD
VVIlosspowerswitching DD
Dr. Ahmed H. Madian-VLSI 19
Circuit characterization & performance
Resistance estimation
Capacitance estimation
Transistor capacitance
Routing capacitance
Inductance estimation
Delay estimation
Dr. Ahmed H. Madian-VLSI 20
Capacitance estimation
The dynamic response of MOS systems strongly depends on the parasitic capacitances associated with the MOS device. The total load capacitance on the output of a CMOS gate is the sum of: gate capacitance (of other inputs connected to out)
diffusion capacitance (of drain/source regions)
routing capacitances (output to other inputs)
gate
drain
source
substrate
CGD
CGS CSB
CDB
CGB
21
Capacitance (1/2)
Transistors
Depends on area of transistor gate
Depends on physical materials, thickness of insulator
Given for a specific process as Cg
Diffusion to substrate
Side-wall capacitance - capacitance from periphery
bottom-wall capacitance - capacitance to substrate
Given for a specific process as Cdiff,bot, Cdiff,side
Dr. Ahmed H. Madian-VLSI
22
Capacitance (2/2)
Metal to substrate
Parallel plate capacitance is dominant
Need to account for fringing, too
Poly to substrate
Parallel plate plus fringing, like metal
don’t confuse poly over substrate with gate capacitance
Also important: capacitance between conductors
Metal1-Metal1
Metal1-Metal2
Dr. Ahmed H. Madian-VLSI
Dr. Ahmed H. Madian-VLSI 23
Capacitance estimation (cont.)
Gate capacitance
Diffusion capacitance
Routing capacitance
Cdiff >Cpoly>Cm1>Cm2
n+substrate
gate
insulatorCgate
Cdiff.
gate
n+substrate
Metal layer
Crouting
Dr. Ahmed H. Madian-VLSI 24
Capacitance estimation
In general, capacitance could be calculated using
d
A
d
AC ro ...
oxro
areaunit Cd
C .
/ d
Dr. Ahmed H. Madian-VLSI 25
Gate Capacitance
Cg = Cgs + Cgd + Cgb
Dr. Ahmed H. Madian-VLSI 26
Capacitance estimation (cont.)
Diffusion capacitance (source/drain)Source
Diffusion
Area
Drain
Diffusion
Area
b
a
Gate
insulatorCJP
Side wall capacitance
CJa
area capacitance
PCACC sidewallsdAreaddiffs .. ,,,
Where A = area and p = perimeters
Dr. Ahmed H. Madian-VLSI 27
Routing capacitance
single conductor capacitance
multiple conductor capacitance
Dr. Ahmed H. Madian-VLSI 28
Capacitance estimation (cont.)
Metal 1
substrate
Fringing capacitance
2222
1ln
22
t
h
t
h
t
hh
tw
Ctotal
Routing capacitance: a) single conductor capacitance
w h
t
Half cylinders
Dr. Ahmed H. Madian-VLSI 29
Capacitance estimation (cont.)
Metal 2
Metal 1
substrate
C12
C2
C1
C1C2
C12
Metal 2Metal 1Vin
Vout
122
12.CC
CVV inout
Routing capacitance: b) multiple conductor capacitance
Dr. Ahmed H. Madian-VLSI 30
Multilayer capacitance calculations
Example: given the layout shown in the figure calculate the
total capacitance at source and gate given that:
Cmetal/Area = 0.025µF/µm2
Cpoly/Area = 0.045µF/µm2
CGate/A = 0.7 fF/µm2
Cd,a/A = 0.33fF/µm2
Cd,side/L = 2.6fF/µm
l = 5.1µm
100l
3l CM
4l
4l
2l
3l
2l
4l4l 2l
CMP
CP1
Cgate
CP1
Dr. Ahmed H. Madian-VLSI 31
Solution
100l
3l CM
4l
4l
2l
3l
2l
4l4l 2l
CMP
CP1
Cgate
CP1
Source capacitance
CS,diff = Cd,A . A + Cd,side walls . P
A = 4l * 3l = 12 l2
P = 2*(4l + 3l)=14 l
So, CS, diff = 0.33* 12 l2+2.6* 14 l=63.51fF
Cs
S D
G
CG
CD
Dr. Ahmed H. Madian-VLSI 32
Solution (cont.)100l
3l CM
4l
4l
2l
3l
2l
4l4l 2l
CMP
CP1
Cgate
CP1
Gate capacitance
CG,total = CM + CMP+CP1+CG+CP2
CM = 0.025 * 100l*3 l=7.5l2
CMP = 0.045 * 4l* 4 l = 0.72l2
CP1 = 0.045 * 2l* 2l = 0.18l2
CP2 = 0.045 * 2l* 2l = 0.18l2
CG = 0.7 * 2l* 3l = 4.2l2 CM CMP CP1 Cgate CP1
33
Example Problems -Parasitic Calculation (1/10)
poly
metal1
ndiff
Rmetal1=?
Cmetal1=?
Rpoly=?
Cpoly=?
Rndiff=?
Cndiff=?
1l=0.25µm
30l
Dr. Ahmed H. Madian-VLSI
34
Example Problems -Parasitic Calculation (2/10)
poly
metal1
ndiff
1l=0.25µm
30l
Rmetal1 = (30l / 3l) * 0.08Ω/o = 0.8Ω
Cmetal1 = (30l * 0.25µm/l) * (3l * 0.25µm/l) * 0.04fF/µm2 +
(30l + 3l 30l + 3l) * 0.25µm/l * 0.09fF/µm
= 0.225fF + 1.485fF
= 1.71fF
Dr. Ahmed H. Madian-VLSI
35
Example Problems -Parasitic Calculation (3/10)
poly
metal1
ndiff
1l=0.25µm
30l
Rndiff = (11l / 3l) * 2Ω/o = 7.33Ω
Cndiff = (11l * 0.25µm/l) * (3l * 0.25µm/l) * 0.6fF/µm2 +
(11l + 3l 11l + 3l) * 0.25µm/l * 0.2fF/µm
= 1.24fF + 1.4fF
= 2.64fF
Dr. Ahmed H. Madian-VLSI
36
Example Problems -Parasitic Calculation (4/10)
poly
metal1
ndiff
1l=0.25µm
30l
Rpoly = ((3l / 2l) + 1/2o + (8l / 2l)) * 4Ω/o = 24Ω
Cpoly = ( ((3l * 0.25µm/l) * (2l * 0.25µm/l))
((10l * 0.25µm/l) * (2l * 0.25µm/l))) * 0.09fF/µm2 +
(5l + 10l 2l + 8l + 3l + 2l) * 0.25µm/l * 0.04fF/µm
= 0.15fF + 0.3fF
= 0.45fF
Corner approx.
1/2o
Dr. Ahmed H. Madian-VLSI
37
Example Problems -Parasitic Calculation (5/10)
poly
metal1
ndiff
1l=0.25µm
30l
Rmetal1=0.8Ω
Cmetal1= 1.71fF
Rndiff=7.33Ω
Cndiff= 2.64fF
Rpoly=24Ω
Cpoly= 0.45fF
Dr. Ahmed H. Madian-VLSI
38
Example Problems -Parasitic Calculation (6/10)
A
1l=0.25µm
What are the parasitic capacitances visible from point “A”?
Dr. Ahmed H. Madian-VLSI
39
Example Problems -Parasitic Calculation (7/10)
A
1l=0.25µm
What are the parasitic capacitances visible from point “A”?
Cpoly = (6l * 0.25µm/l) * (2l * 0.25µm/l) * 0.09fF/µm2 +
(6l + 2l 6l + 2l) * 0.25µm/l * 0.04fF/µm
= 0.675fF + 0.16fF
= 0.84fF
Dr. Ahmed H. Madian-VLSI
40
Example Problems -Parasitic Calculation (8/10)
A
1l=0.25µm
What are the parasitic capacitances visible from point “A”?
Cgate = (3l * 0.25µm/l) * (2l * 0.25µm/l) * 0.9fF/µm2
= 0.34fF
Remember: use Cg, not Cpoly for transistor gates!
Dr. Ahmed H. Madian-VLSI
41
Example Problems -Parasitic Calculation (9/10)
A
1l=0.25µm
What are the parasitic capacitances visible from point “A”?
Coverhang = (2l * 0.25µm/l) * (2l * 0.25µm/l) * 0.09fF/µm2 +
(2l + 2l 2l + 2l) * 0.25µm/l * 0.04fF/µm
= 0.0225fF + 0.08fF
= 0.1fF
Dr. Ahmed H. Madian-VLSI
42
A
1l=0.25µm
What are the parasitic capacitances visible from point “A”?
Example Problems -Parasitic Calculation (10/10)
Dr. Ahmed H. Madian-VLSI
Dr. Ahmed H. Madian-VLSI 43
Contents
Wiring tracks Latch-up Circuit characterization & performance Resistance estimation Capacitance estimation Inductance estimation Delay estimation
Simple RC model Penfield-Rubenstein Model
Delay minimization techniques Transistor sizing Distributed drivers Large driver
Wiring techniques
Dr. Ahmed H. Madian-VLSI 44
Inductance estimation Inductance is normally small but as the process shrink on-chip inductance must be
taken into account.
Bond-wire inductance can cause deleterious effects in large, high speed I/O buffers.
The inductance of bonding wires and the pins on packages could be calculated by,
d
h
w
hL
48ln
2
substrate
h
W
Design techniques to overcome this problem:
separate power pins for I/O pads and chip core
multiple power and ground pins
careful selection of the position of the power and
ground pins on the package
adding decoupling capacitances on the board
increase the rise and fall times
use advanced package technologies (SMD, etc)