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Versatile Link+ for HGCAL upgrade project.
¨Electronics Engineer or Applied Physicist for Next Generation Optical Links for CMS Calorimeter Upgrade¨
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18/05/2020
Motivation for upgrading CMS endcap calorimeters for HL-LHC
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The High-Luminosity Large Hadron Collider (HL-LHC) project crank up the performance of the LHC increasing luminosity by a factor of 10 beyond the LHC’s design value.
Versatile Link +
18/05/2020
The existing CMS endcap calorimeters cannot cope with the expected radiation or pileup at HL-LHC. CMS will replace it with a new High Granularity calorimeter (HGCAL).
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CMS at HL-LHC:~1𝑥1016 1MeV 𝑛𝑒𝑞 𝑐𝑚
−2 at
3𝑎𝑏−1 and up to 2MGy absorbed dose in endcap calorimeters.
Motivation for upgrading CMS endcap calorimeters for HL-LHC
Versatile Link +
18/05/2020
Versatile Link+ for HL-LHC
VTRx+
Passives
TRX
Backend
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For the HGCAL, the Versatile Link+ project will provide the High-bandwidth data transceiver for the front-end and all the optical path till the backend electronics, dealing with the amount of radiation this parts will suffer, and the narrow space this detector has for integrating everything.
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18/05/2020
Versatile Link+ for HL-LHC Experiments
• Asymmetric Data-rates
5 or 10 Gb/s upstream (out of detector)
2.5 Gb/s downstream
• Environment
1 MGy, 3x1015 n/cm2
-35 to +60 °C
On-Detector Off-Detector
Custom ASICs & packaging
Radiation tolerant
Commercial
Custom protocol
Up to 4Tx plus 1Rx On-board 12Tx, 12Rx module
Backend
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VTRx+
cpVLAD: Charge Pump VcseL Array Driver
The on-chip charge pump internally provides more than 2.5V to the Output Buffer. This voltage follows the VCSEL’sforward voltage increase as the total dose accumulates, automatically controlled by the Feedback circuit.
Supply voltages:1.2V and 2.5V only
The cpVLAD: a collaboration between SMU and CERN, is a laser driver with a Charge Pump that leaves head room to driver the VCSELs even with the power demand grows.One charge pump for every Tx channel, where we have the problem of the power consumption in the LDQ10.
Designed in: Dept. of Physics, SMU (Southern Methodist University, Dallas TX.)
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cpVLAD: End of the tests
All of this results, errors and problems detection are reported to the cpVLAD designers.
• After a fast study of the chip with laser in the parts signals as probably problematic, the designers noticed that the software they use to eliminating gate redundancy, deleted part of the design that should be present.
• When the optoteam irradiated VTRx+ modules in Louvain with neutrons, they did not observe any significant advantage from the cpVLAD. In particular, the way the bias and modulation is defined already before irradiation is not as useful/flexible as the LDQ10.
Next step:
cpVLAD_v3
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• With all of these things added together, the group in charge of the project supervision from CERN, decided that the amount of time and money that solving this problems need and the complete rework of the chip to get something beneficial, versus the advantages of this chip as substitute of the LDQ10 laser driver currently using the VTRx+ prototypes, is not worth it.
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18/05/2020
Other solution for the VTRx+
Return to the previous laser driver.
The LDQ10 is the laser driver that the cpVLAD wanted to replace in the VTRx+ project.
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VTRx+ module
Meanwhile the cpVLAD was developed and tested, the development and test of the LDQ10 continued by the optoteam.
The main problem of the LDQ10 (and the same one that the cpVLAD was trying to solve) was the level of radiation that it is able to support before dropping the current driven to the VCSELs.
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18/05/2020
Other solution for the VTRx+
Without the option of the redesign a new laser driver to fix the LDQ10 problem, the only way to install the current version of the VTRx+ is including an area restriction for installing it, in the design of the proper detector parts.
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PCB design of a section of HGCAL 1st cassette
Area where the
radiation is higher
than the amount
that the LDQ10
resists
Going back to the previous laser driver, is the reason why, after the cpVLAD_v3 was cancelled, I entered in the “front-end electronics task force” group for the CMS endcap calorimeters (HGCAL).
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18/05/2020
Other solution for the VTRx+
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My main role in the electronics task force is the design of the optical fiber mapping from the VTRx+, (inside the cassettes) to the backend in the service cavern, assuring that the attenuation in the fibers path is the minimum we can achieve.
Side view of HGCAL
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18/05/2020
Basic fiber constraints:
Connection configuration
Fiber fragility
4+1Front-end
12+12Back-end
Complex mapping:Rearranging fibers to get the minimum amount of dark fibers and waste of service´s space
Broken fiber core by a sudden tug Lateral crack due to bend the fiber
• Resistant in direction along the core.• Fragile in the direction perpendicular to the
core.
Impossible to put any naked fiber outside the cassette
Problems for the fiber mapping in the HGCAL:
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3 OPTIONS:1) Custom N to M connector fanout harness for inside cassette
Unique connection map for each cassette and each ϕ of the cassette Super fragile Complex design connections Complex installation Minimum amount of dark fibers along the services cavern
Need a lot of spare pieces EXPENSIVE
Currently working in the design of a fibers map mixing the options 1 and 2. With just one of two custom fanouts useful for all the cassette layers and minimizing the number and size of the shuffle boxes.
Mapping:
Problems for the fiber mapping in the HGCAL:
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2) Shuffle between PPO & PP1 Custom made shuffle “boxes” Competing for space with services.
3) Shuffle in the backend All shuffle elements co-located. E.g. in one of the Back-end Racks. Biggest amount of dark fibers all along the path.
There are big space constraints along entire path to the backend.
Waste of space and money in fibers.
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VTRx+ transceiver Sizes
• small-footprint (20 mm ×10 mm). • 2mm stacking height 40-pin connector.• Total height of 2.5mm• MT clamp for the pigtail: 7mm x 3.8mm Taller than the 3mm height inside the cassette!
Power consumption• To minimize it, unused channels can be disabled.• The end-of-life power consumption is 6 mW + 50 mW/ch Tx + 100 mW/ch.
VTRx+ module plugged onto its host board.
Main constrains inside the cassettes:
Problems for the fiber mapping in the HGCAL:
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Versatile Link + optical power budget allows 5 break points maximum.
VTRx+Trunk
MT-clamp MTP24 connector
Shuffle
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1st proposal: Splice fibers inside cassette
Shuffle patch cordShuffle patch cord
*irremovable
Problems for the fiber mapping in the HGCAL:
1st proposal) Splice fibers inside the cassette
Cut the fibers and fuse with other in some point of the mapping:• This option demands a trained technician to fuse the fibers during the cassette assembly, and create
the naked fibers ¨spider net¨ for each cassette, one by one.
Jacketed fiber
Naked fiber
fused fiber points
MPO24 jacketed at the edge (PP0)
We can eliminate almost all the dark fibers, and separate Trigger and DAQ inside the cassette doing a complex ¨spider net¨.
Naked fiber
Jacketed fiber
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This is the layer 5: the worst layer in terms of dark fiber, custom made nets during assembly will reduce to a much lower %
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VTRx+Trunk
MT-clamp MTP24 connector
Shuffle
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2nd proposal) Splice to a shuffle box at the backend.
Splice &Shuffle box
Shuffle patch cord
*irremovable
Problems for the fiber mapping in the HGCAL:
2nd proposal) Splice fibers at the backend
12 connectors of 24 fibers / trunk
If we have 4 connector of 24fibers in each cassette (multiply the worst casette to all system) -> 28.800 fibers/endcap57.600 fibers in the system / 288 (fibers/trunk) = 200 trunks The alive fibers are 43.560, this means that we are using until this point 14.040 dark fibers - > 24% DARK FIBER43.560 fibers to splice and reorganize by hand in the Service Cavern floor…This is feasible, but check each one of the fusions and check if the system is working and where is the error at the final stage will be difficult.
Splice points
To backend
Shuffle box custom ordereddirectly with the lengths and connectors to the BE boards
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3rd proposal) Shuffle patch cord: between PP0 & PP1 (along splice inside the cassettes)
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Just with this two shuffle models, the dark fiber is reduced from 35% to <5% before the Trunk, saving a 30% of the most expensive piece of the map.
Overview mapping
Example of cabling plan for 1 cassette: 2 Trigger links/engine
Assuming it is possible to reach PP0 filling the connector and ordering all the fibers inside the cassette
Shuffle only inside the cavern.As close to PP0, the better.
How the backend order their transceivers is just a supposition.
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MeanwhileOther Tasks:
Versatile Link Plus Transceiver Version 10 Prototype Batch 2 - Room-temperature functional tests:In October 2019, 326 prototypes modules were delivered to CERN after being assembled by AEMtec GmbH.
TestsFirst, some static tests have been carried out to verify the optical coupling. To test dynamic performance, optical eye diagrams have been captured at different VCSEL bias and modulation currents and some eye diagram parameters have been extracted. Finally, the receiver sensitivity of the prototypes was measured by performing bit error rate tests in the opposite direction using a reference transmitter.
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Meanwhile
Other Tasks:
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In Feb. 2020 I started to build a real size mock up of one of the cassettes of the most complicated layer of HGCAL to study the “worst case scenario” of the whole cabling.
The original idea was to build the different proposal of the fiber mapping and try to compare the main restrictions of this ideas: size, cost, power budget losses, necessary time to mount and difficulty to build the harnesses.
Due the actual situation:As most of the people, I’m not able to work in the lab to continue this tests. I was assigned to other task related to the HGCAL cassettes:
PCB design of a section of HGCAL 1st cassette
LD HD
This is just the schema of how the cassette would look like, the pieces forming it are still in the design stage.
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Hardware DesignHigh Density:
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An overview of the HD connections is shown. This diagram shows the worst case2 of 3 Full HD-HexModules and 1 Partial HD-HexModule.
The PCB stack-up.
Right now I’m in charge of design the HDEngine and the HDWagon board.
But because, the modules that I need for this boards are still in developing stage, I’m making also the test boards for most of this modules and figuring out how to program some FPGAs to behavior like some of this modules to test the others…
