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1. Start Xilinx Project Navigator

2. Create a new project

Click on File, then chooseNew Projecton the drop down menu Enter your project name, in this case the project is called MUX2to1 Choose your project location, this project is stored at C:\Projects\ MUX2to1 ChooseHDL as the source type from the Top-Level Source Type menu. ClickNextbutton

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3. You will be asked to select the hardware and design flow for this project.

For Family, choose Spartan3 For Simulator, chooseISE Simulator (VHDL/Verilog) ClickNextbutton

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4. A project summary will appear. Click on the Finish button.

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5. Now we want to add a new file to our project.

Click on Project, chooseNew Source

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6. Choose Verilog Module as the file type

In the File name: box enter the desired file name, in this case the file is namedmux2to1.v

Click on theNextbutton

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7. You will be asked for the modules port names/types. You can skip this step

and click on theNextbutton.

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8. A project summary will appear. Click on the Finish button.

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9. The mux2to1.v file has been added to your project.

The mux2to1.v file has

been added to the

project.

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10. Write the verilog code for the required functionality in the workspace.

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11. After coding is done, select Simulation by clicking the radio button.

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12. Click on the mux2to1.v file

In the Processes tab below, ISim

Simulator option appears. Expand it

and double click on the Behavioral

check Syntax

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13. Any syntax errors would be displayed here. If Check Syntax is done

completely, then double click on the Simulate Behavioural model

Any Errors after Behavioural Check

Syntax would be shown here.

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14. After double clicking on the Simulate Behavioural model, a new simulation

window opens up. (ISim M.63c)

In the ISim window, the Input and

Output signals along with their

values appear.

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15. Assign the values to the inputs by right clicking on the value and selecting

Force Constant.

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16. After selecting Force Constant, a dialog box appears and the value to be

forced is given in the Force to Value field. Leave the other fields as it is. After

entering the Force to value, click on Apply and the OK buttons. Repeat thesame process only for the inputs.

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17. After selecting the Force to value for all the inputs, click on the run button.

RUN button

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Synthesis:

18. For Synthesis, go back to the Project Navigator window and select the

Implementation radio button.

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19. If there are multiple verilog files in the same project click on the module

you want to synthesise and right click on it and select Set as Top Module. After

that a dialog box appears, click YES. If there is only one file to synthesize youcan skip this step.

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20. In the Processes tab below, expand Synthesize - XST and then double click

Check Syntax.

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21. After the Syntax is checked successfully, double click the View RTL

Scehmatic. Then Set RTL/Techviewer starupmode window appers. Choose the

first radio button and click OK.

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22. Then the Create RTL Schematic Window Appears. In this window, select

the project mux2to1 and then click ADD. The project gets added to the Selected

Elements list and then click the Create Schematic button at the right bottom.

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23. After clicking the Create Schematic button, the synthesised multiplexer

appears

24. Double click on the mux2to1 box that is being shown. The gate level

realisation of the multiplexer is shown