Vahe Caliskan, Sc.D. - ece.uic.eduvahe/spring2012/ece396/linreg.pdf · Topology Advantages Disadvantages NPN smallest die size large dropout voltage ... BodePlot(magnitude&phase)

Linear Regulators: Fundamentals and Compensation

Vahe Caliskan, Sc.D.Senior Technical Expert

Motorola AutomotiveGovernment & Enterprise Mobility Solutions

February 15, 2012

Vahe Caliskan, Sc.D. (g17823) Linear Regulators February 15, 2012 1 / 32

1 Introduction

2 Review of Linear Regulator Topologies

3 Transfer Functions

4 Poles & Zeros

5 Bode Magnitude & Phase Plots


Outline

1 Introduction



4 Poles & Zeros



Introduction to Seminar Series

Goals of the Seminar Series

Provide an overview of power conversion techniquesPower supplies are common subsystems in most of our products

Present follow-up seminars in related areas→ switching regulator topologies/compensation, simulation

Offer refresher seminars in fundamental areas→ mathematical modeling, circuit analysis, control design


Previous Seminars

Overview of Linear and Switching Power Supplies

Two seminars were held on September 15 and October 17, 2005a total of 83 people attended these seminars

Follow-up seminars in linear and switching regulators were requested

http://compass.mot.com/go/powerconversion


Outline

1 Introduction



4 Poles & Zeros



Linear Regulator Basics

Three-terminal devices – input, output, common (ground)

Linear regulators may be classified by their series (pass) transistor

− Series element may consist of bipolar of field-effect transistors

Bipolar outputs → Darlington NPN, PNP, NPN-PNP

Majority of regulators use bipolars (FET-based regulators $)

Series transistor structure determines Vdropout , Ibias , Iq, Pdiss

Frequency compensation and protection circuity also important

Vdropout minimum input-output voltage difference to stay in regulation

Ibias bias current for the pass transistor

Iq regulator quiescent current of which Ibias is one component

Pdiss regulator power dissipation


Linear Regulator – Typical Usage

Vin Vout

GND

IN OUT

BYPASSEN

TPS76433

ESR1µF

0.01µF

4.7µF

TPS76433 – 3.3V, 150mA, PMOS LDO linear regulator

Low output voltage noise (50µV), Low power (Iq = 140µA)

0.01µF bypass capacitor filters reference voltage

Capacitor ESR important for stability (not too high, not too low)

Current limit (1A), thermal protection (165C shutdown)


NPN Regulator

NPN Regulator

−

+

+−

Vin

R1

R2

Vref

VoutIload

Error Amp

IbiasGND

Characteristics

NPN Darlington pass

PNP driver

Used in 78xx series

Ibias ≈ Iload/β3

Smallest chip area

Small comp. capacitor

Least expensive

Vdo = 2VBE+Vsat ≈ 2.0V

No reverse batteryprotection


PNP Low Dropout (LDO) Regulator

PNP (LDO) Regulator

−

+

+−

Vin

R1

R2

Vref

VoutIload

Error Amp

IbiasGND

Characteristics

PNP pass

NPN or EA direct drive

Vdo = Vsat ≈ 600mV

Inherent reverse batteryprotection

Ibias ≈ Iload/βpnp

Large chip area

Large comp. capacitor

More expensive


Composite (Quasi-LDO) Regulator

Composite Regulator

−

+

+−

Vin

R1

R2

Vref

VoutIload

Error Amp

IbiasGND

Characteristics

NPN pass

PNP driver

Vdo = VBE + Vsat ≈ 1.3V

Ibias ≈ Iload/β2

Compromise betweenNPN and PNP

Larger chip area thanNPN

Large comp. capacitor

No reverse batteryprotection


PMOS LDO Regulator

PMOS Regulator−

+

+−

Vin

R1

R2

Vref

VoutIload

Error Amp

IbiasGND

Characteristics

PMOS pass

NPN driver

Very low Vdo (≈ 50mV)

Vdo controlled by Rds,on

Very low Ibias

Can’t enhance FET forVin < 3V


NMOS LDO Regulator

NMOS Regulator

−

+

+−

Vin

R1

R2

Iload

Vref

Vout

Vbias

Error Amp

GND

Characteristics

NMOS pass

Direct drive

Very low Vdo

Lower Rds,on than PMOS

Lower output impedance

Smaller external caps

Needs Vbias > Vout toenhance FET


Summary of Linear Regulator Advantages/Disadvantages

Topology Advantages Disadvantages

NPN smallest die size large dropout voltagefastest transient response no rev. batt. protectionsmallest comp. capacitor

PNP LDO low dropout voltage high quiescent currentrev. battery protection large comp. capacitor

large die size

NPN/PNP moderate dropout voltage large comp. capacitorlower Iq than PNP no rev. battery protection

PMOS LDO very low Vdo and Ibias need Vin > 3VVdo ∝ Rds,on

NMOS LDO very low Vdo , low Rout need Vbias > Vout

lower Rds,on than PMOSsmaller external capacitors


Outline

1 Introduction



4 Poles & Zeros



Transfer Function Fundamentals

Transfer function is a ratio of response to excitation ( responseexcitation)

Use of (outputinput ) for TFs is vague (E and R can be at same port)

Expressed in frequency domain using Laplace or Fourier Transforms

vin

R

C vout++

−−

Voltage Gain (V/V), ωc = 1RC = corner frequency

A(s) =vout(s)

vin(s)=

1sC

R + 1sC

=1

1 + sRC=

1

1 + sωc

iin

R

Cvin

+

−

Input Impedance (Ω)

Zin(s) =vin(s)

iin(s)= R+

1

sC= R

1 + sRC

sRC= R

1 + sωc

sωc


Poles & Zeros

Transfer function is a ratio of two polynomials A(s) = num(s)den(s)

Poles are values of s that make den(s) = 0

Also called roots or natural frequenciesResponse to initial conditions, independent of applied excitationDetermine stability

Zeros are values of s that make num(s) = 0

Also called transmission zerosNo impact on stabilityDetermine undershoot, transient response (with poles)

Evaluate TF by letting s = jω and take complex magnitude and phase

A(jω) =1

1 + j ωωc

=1

√

1 +(

ωωc

)2

︸︷︷︸

magnitude

∠− tan−1

(ω

ωc

)

︸︷︷︸

phase


Bode Plots & Stability

Loop gain T (s) is the product of forward and feedback gains

Closed-loop system can be unstable even if T (s), G (s) have no RHP poles

Undesired ringing and overshoot can occur even in stable systems

Crossover frequency ωc is where ‖T (jωc)‖ = 1 ⇒ 0dB

Phase margin φm = 180 + ∠T (jωc)

If φm > 0 ⇒ feedback system stable (no RHP poles)

Small φm ⇒ high-Q resonant poles near ωc ⇒ overshoot & ringing

We normally need φm ≥ 45 in practical feedback systems

If φm < 0 ⇒ feedback system unstable (at least one RHP pole)


Outline

1 Introduction



4 Poles & Zeros



1st Order Poles and Zeros

1st Order Pole 11+s/ωc

ω

ω

0dB

−20dB

−40dB

3dB

−45

−90

0

5.7

5.7

ωc 10ωc0.1ωc

−20dB/dec

−45/dec

1st Order Zero 1 + s/ωc

ω

ω0dB

20dB

40dB

3dB

45

90

0

5.7

5.7

ωc

ωc

10ωc

10ωc

0.1ωc

0.1ωc

+20dB/dec

+45/dec


Outline

1 Introduction



4 Poles & Zeros



Bode Plot (magnitude & phase)100

80

60

40

20

-60

-40

-20

180

135

90

45

-225

-180

-135

-90

-45

10101010101010

0

0

0

-1 1 2 3 4 5

Magnitude(dB)

Phase

(deg

)

Frequency (rad/sec)

-20dB/dec


LDO System (3.3V/100mA)

−

+

+−

+−Vin

Vout

Vref

1.192V

2Ω

10µF

0.5µF

R1

R2

RL

RC

0.64R

0.36R

Co

Cb

Iload

TPS76433

Error Amp

Vout = (1 + R1R2)Vref = (1 + 0.64R

0.36R ) 1.192V = 3.31V

RL = Vout/Iload = 3.3V/100mA = 33Ω


LDO System Model

−

+

+−

+−

D

G

S

vgs Cgsgmvgs

rds

Roa

Vin

Vout

Vref

1.192V

2Ω

33Ω

10µF

0.5µF

R1

R2

RL

RC

0.64R

0.36R

Co

Cb

Error Amp


LDO System Model Simple

D

G

S

S

vgs Cgs

rds

Roa

2Ω

33Ω

10µF

0.5µF

R1

R2

RL

Rc

0.64R

0.36R

Co

Cb

Gpmosvgs =(gmrds)vgs

vs

voutZo(s) ≈ (Rc +

1sCo

)‖ 1sCb

‖RL

+

+

−

− Geavs

︷︸︸︷

Gea(vs − Vref︸︷︷︸

→ 0

)


LDO System Loop Gain

−gmrds

vgs

vs

vout

R2R1+R2

Zo(s)rds+Zo(s)

Gea

11+sRoaCgs

Feedback DividerError Amp Gain

Load & FilterPMOS Voltage GainEA – PMOS

Frequency Response

Gfb

G (s)−GpmosGoa(s)

Vref = 0

−

+


LDO System Loop Gain (redrawn)

gmrds

vgs

vs

vout

R2R1+R2

Zo(s)rds+Zo(s)

Gea1

1+sRoaCgs

Feedback Divider

Error Amp Gain Load & FilterPMOS Voltage GainEA – PMOS

Frequency Response

Gfb

G (s)GpmosGoa(s)

Vref = 0−

+

T (s)


Loop Gain Calculation

G (s) ≈ G01 + s/ωz

(1 + s/ωo)(1 + s/ωb)with G0 =

RL

rds + RL

T (s) ≈ GpmosG0GfbGea1 + s/ωz

(1 + s/ωo)(1 + s/ωb)(1 + s/ωoa)

T0 = GpmosG0GfbGea ⇒ Low-frequency loop gain

ωo ≈ 1/[Co(Rc + rds‖RL)] ⇒ Load pole

ωoa = 1/[RoaCgs ] ⇒ Pole due to opamp-PMOS interaction

ωb ≈ 1/[CbRc(rds‖RL)/(Rc + (rds‖RL))] ⇒ Pole due to bypass cap

ωz = 1/[RcCo ] ⇒ Zero due to ESR


Parameters, Gains, Pole/Zero Locations

Vout 3.3V Iload 100mARL 33Ω Roa 300kΩRc 2Ω Co 10µFgm 123mA/V Cb 0.5µFrds 65Ω Cgs 200pFR1 64kΩ R2 36kΩ

Gpmos gmrds 8 ⇒ 18.1dBGfb R1/(R1 + R2) 0.36 ⇒ −8.9dBGo RL/(rds + RL) 0.337 ⇒ −9.45dBGea N/A 56.2 ⇒ 35dBT0 GpmosG0GfbGea 54.5 ⇒ 34.7dB

ωo 1/[Co(Rc + rds‖RL)] 4.2krad/s ⇒ 667Hzωoa 1/[RoaCgs ] 16.7krad/s ⇒ 2.65kHzωb 1/[CbRc‖(rds‖RL)] 1.1Mrad/s ⇒ 172kHzωz 1/[RcCo ] 50krad/s ⇒ 8kHz


Conclusion

item 1

item 2

item 3

item 4

item 5


References

Everett Rogers, “Stability Analysis of low-dropout linear regulators with a PMOS pass element”

Texas Instruments Analog Applications Journal, Dallas, TX, August 1999.

Bang S. Lee, “Understanding the stable range of equivalent series resistance of an LDO regulator”

Texas Instruments Analog Applications Journal, Dallas, TX, November 1999.

Chester Simpson, “Linear Regulators: Theory of Operation and Compensation”

National Semiconductor Application Note AN–1188, Santa Clara, CA, May 2000.

Kieran O’Malley, “Compensation for Linear Regulators”

ON Semiconductor Application Note SR0003AN/D, Phoenix, AZ, April 2001.

Kieran O’Malley, “Linear Regulator Output Structures”

ON Semiconductor Application Note SR0004AN/D, Phoenix, AZ, April 2001.

Todd Schiff, “Stability in High Speed Linear LDO Regulators”

ON Semiconductor Application Note AND8037/D, Phoenix, AZ, October 2000.


Sources of information on the web

http://www.analog.com —– Analog Devices

http://www.infineon.com – Infineon Technologies

http://www.linear.com —– Linear Technology

http://www.maxim-ic.com – Maxim

http://www.national.com – National Semiconductor

http://www.onsemi.com —– ON Semiconductor

http://www.ti.com ———– Texas Instruments


Documents

Vahe Caliskan, Sc.D. - ece.uic.eduvahe/spring2012/ece396/linreg.pdf · Topology Advantages Disadvantages NPN smallest die size large dropout voltage ... BodePlot(magnitude&phase)