41 IEEE T R A N S A C T I O N S O N S E M I C O N D U C T O R MANI’F.\CTI!RING. V O L . 5 . N O I . FEBRl IAKY 1992

Using Yield Models to Accelerate Learning Curve Progress

Daren Dance and Richard Jarvis

Abstract-World-wide competitive pressure is dribing SUC- cessful semiconductor companies toward ever improving per- formance-price ratios. In addition, this pressure is accelerating the rate of performance-price improvement. Using yield models can accelerate the rate at which processing experience reduces manufacturing costs. This paper reviews learning curves, out- lines an improvement strategy using yield models, presents en- hancements, and illustrates an application of yield models to accelerate learning. Detailed, validated models can simulate the yield effects of process and equipment improvement plans. Yield models, used with short-loop defect monitors, allow rapid feed- back of experimental results to yield improvement efforts by compressing normal processing cycle times.

I . INTRODUCTION ROM the early days of industrial America, managers F have recognized that manufacturing proficiency im-

proves with continued production. As proficiency ini- proves, costs are reduced. Learning curves describe the relationship between unit cost and cumulative volume. Today, world-wide competitive pressure drives semicon- ductor manufacturers to improve performance-price ra- tios. In addition, these pressures accelerate the rate of performance-price improvement, steepening the semicon- ductor learning curve. Using yield models to accelerate learning curve progress reduces learning cycle time to de- liver required manufacturing technology within the time frame set by the competition.

11. LEARNING CURVES T. P. Wright first applied the learning curve (or expe-

rience curve) in 1936, “the man-hours required to assern- ble an airplane declined by 20% each time the uni t pro- duction doubled” [ 11. Plotting the data on a log-log scale shows a straight line with negative slope. indicating a constant rate of reduction. Such a plot describes an 80% learning curve.

Cunningham’s 1980 article on learning curves presents 15 examples from U.S. industries, with learning curve slopes ranging from 60 to 9 0 % . Aggressive learning curve slopes in the semiconductor industry result from such fac-

Manuscript received August 16, 1990: revised March 26. 1991 D. Dance is with SEMATECH. Austin, TX 78741 R . Jarvis is with AT&T Microelectronics. Orlando. FL 32819 IEEE Log Number 9104508.

tors as reducing unit price and increasing circuit density. Quoting Cunningham: “Both have tumbled down learn- ing curves of 75 to 80%. Combining these parameters yields the very impressive 60% price versus electronic function slope * * . .” He observes that we can, “expect that continual improvements in efficiency and productiv- ity are normal and expected, and that when such improve- ments stop or slow down, something is wrong” [ 11.

Learning curves clearly show manufacturing improve- ment. But learning curves contain a fallacy: Increased production does not automatically cause unit price reduc- tion as the learning curve implies. Blindly producing more and more of the same product in the same way does not increase productivity. Unit price reduction results from continuous improvement by applying knowledge gained from increased production.

111. THE IMPROVEMENT CYCLE Applying the Demming (or Shewhai-t) improvement

cycle to all phases of the product life cycle results in con- tinuous improvement. The Demming cycle has four steps

I . Plan. What could be the most important accom- plishments? What changes might be desirable? Plan a change or test.

2. Do. Carry out the change or test decided upon. 3. Verify. Observe the effects of the change or test. 4. Learn. What did we learn from the results? What

can we predict?

121:

The improvement cycle repeats, learning from previous cycles.

The ability of learning curves to measure improvement is due to correlation between the number of improvement cycles and manufacturing production volume. Increased production provides increased opportunities to apply the Demming improvement cycle. We have three ways of im- proving learning curve progress:

1 . Increase the production rate to increase improve- ment cycle opportunities.

2. shorten cycle times to provide more frequent learn- ing opportunities. or

3 . increase the learning rate from each improvement cycle.

0894-6.507/92$03 00 C 1992 IEEE

42 IEEE T R A N S A C T I O N S OS S E M I C O N D U C l O R M A N U F A C T U R I N G . V O L 5 . N O I , F E B R U A R Y I Y V ?

While the first option is difficult, the Japanese increased DRAM production during the early 1980’s and increased their market share while reaping significant learning ben- efits. The second option, shortening cycle time. can be combined with smaller lot sizes to provide more learning cycles without increasing production. The third option uses tests with short cycle times, calibrated to the process, to increase the learning rate. Options may be combined for greater learning curve progress.

IV. YIELD MODELS A N D THE IMPROVEMENT CYCLE

Yield models are widely discussed in the literature. Stapper references an excellent bibliography [ 31. Yield models relate integrated circuit yield to circuit (area and design) and process parameters (defect density). Certain defects may cause electrical faults. While the sensitivity of a circuit to a defect may vary, all defects have some probability of causing failure [4]. Seeds’ equation is a ex- ample of a yield model [3]

where - Y = Defect-Limited Yield

A = Device Area

Pf = Fault Probability

Do = Defect Density.

Fault probh,ility is the ratio between the area in which a defect must occur to cause a failure and integrated circuit die area. Yield models use estimates of fault probability and process defect density from sources such as visual inspections and short-loop defect monitor chips to esti- mate defect-limited die yield.

A process improvement cycle using yield models has been described by several authors [ 5 ] , [6], [lo]. This cycle, shown in Fig. 1, accelerates the learning curve progress by implementing the yield model in a process improvement cycle. The specific yield model equation used is not critical to the improvement cycle. Different models are appropriate for different processes. Thus, model selection is left to the user.

Semiconductor manufacturing can be divided into pro- cessing zones, each containing a photolithographic se- quence. The yield model can be applied to the processing zone as well

f

Defect data from the i th zone visual defect inspection es- timates defect-limited yield for the i th processing zone.

Process

Inspection Check Mode?

Continue Process)

Failure Analysis1

Ship Yes -- Model OK

Fig I Improvement cycle u j i n g yield modelj

Defect-limited yield estimates for a lot may be com- pared to zone statistics using statistical process control methods, driving the process improvement cycle. As shown in Fig. 1 , information can be fed back to prior pro- cessing to improve process, methods, and equipment. In- formation can also be fed forward to later zones for qual- ity control and scheduling. Inspection, analysis, and feedback are repeated for each process zone.

After processing is finished, electrical yield is com- pared with model yield forecasts. Analyzing these differ- ences drives another improvement cycle. If failure anal- ysis shows the presence of nonrandom defect related problems then information is fed back to the process. Oth- erwise yield model parameters are updated for continuous improvement.

Implementing yield models in the improvement cycle has: “made it possible for process engineers to quantify their own process sector’s influence on [electrical] test yield. They no longer have to wait months to get actual final test results to ensure that the changes they made worked” IS] . Thus an improvement cycle using yield models accelerates learning curve progress.

V. ACCELERATING THE IMPROVEMENT CYCLE

Accelerated learning is one key to competitive manu- facturing. The improvement cycle previously described can be improved to accelerate learning. Some improve- ments include using:

1 . Fine-grained, detailed yield analysis and models, 2. short-loop defect monitors correlated to electrical

yield for shorter processing time, 3. equipment particulate characteristics to predict de-

fect-limited yield, and 4. statistical confidence intervals about yield model

predictions.

We will further discuss each improvement which accel- erates learning curve progress.

DANCE A N D JARVIS USING Y I L L D MODELS 10 ACCELtKATE LEAKNIhG C U R V E PROGRESS 41

A . Fine-Grain Yield Analysis and Models Lea and Bolouri [4] separate yield improvement meth-

ods into coarse-grain and fine-grain yield analysis de- pending on the resolution of observations made about the fabrication process and circuit layout. Coarse-grain anal- ysis approximates yield by considering major influences. One coarse-grain approach uses a single defect density estimate to represent all defect mechanisms. Fine-grain analysis characterizes the contribution of each process zone or defect type to defect-limited yield. This is difficult and expensive, requiring estimates of defect distribution and fault probability by defect type. However, only fine- grain analysis traces yield losses to fundamental causes. Equation (1 ) is an example of a coarse-grain yield model and the process zone model (2) shown in Fig. 2 is an example of a fine-grain model. Knowledge of cause and density by defect type allows focusing on significant problems first.

B. Short-Loop Defect Monitors Using short-loop defect monitors can isolate process

zones and shorten the learning cycle. Short-loop monitors are devices with shorter than full processing cycle times, calibrated to the process. Examples include parallel plate capacitors to detect dielectric defects, contact chains to detect open contacts, interdigitated combs to detect bridg- ing defects, and serpentine meanders to detect open cir- cuits [ 1 11. Short-loop monitors use a portion of the pro- cess and are not biased by defects in other process zones. For example, yield improvement efforts by one of the au- thors were fruitless until the discovery that polysilicon ar- tifacts from a previous zone not metalization problems were causing metal defects. Information obtained from short-loop monitors is well matched to data requirements of fine-grain yield models. These monitors give rapid re- sults and shorten the learning cycle by requiring only a few process steps.

C. Equipment Particulate Characteristics Predicting defect-limited yield from equipment partic-

ulate characteristics extends yield improvement efforts to manufacturing design. Rather than installing a new fab- rication line and process only to spend countless yield im- provement hours eliminating problems, one can use yield considerations to select equipment, develop processes, and design products for subsequent phases. Equipment particle counts are obtained by cycling bare wafers through the equipment, comparing before and after par- ticle measurements made with a laser wafer surface par- ticle counter to estimate particles added per wafer pass (PWP). A table of equipment PWP targets for large DRAMS is found in [7].

As illustrated in Fig. 3, the fine-grain yield model can be extended to the equipment level. This model assumes that defects within a zone are similar and can be added to generate a total PWP for each zone. The zone PWP defect

' i

NTUB THIN GATE LDD N+ P+

WIN 1 MET 1 WIN 2 ' MET 2,

LEVELS OF YIELD MODEL DETAIL

density is factored by the fault probability to estimate fault density. Knowing area and fault density allows calculat- ing defect-limited yield for the zone

k

( 3 ) - 1 Y = rI

I = I 1 + A P , c PWP,,", .

Estimates of equipment PWP allow selecting equipment to maximize yield and focusing improvement efforts on equipment types with the largest impact. This reduces early manufacturing problems to accelerate yield learn- ing.

D. Yield Confidence Intervals

Yield models use assumptions about distributions of defect size, type, and location and estimates of defect density. Thus a yield model provides a point estimate of true yield. It is desirable to have a confidence interval about the yield model's point estimate. A confidence in- terval is a bounded range within which the true parameter may be assumed to lie. Assuming that a random parame- ter follows a normal distribution permits using the follow- ing interval estimate for a confidence interval [ 121:

~

I

44 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING. VOL. 5 . NO. I . FEBRUARY 1992

where

x = Sample Mean

p = Population Mean

s = Sample Standard Deviation

n = Sample Size

t,/2,n - I = Student’s t Statistic

CY = Probability that p lies outside the interval.

Without confidence intervals about yield predictions, the yield analyst may waste time chasing discrepancies be- tween estimated and actual yield that are within the range of normal process variation.

Several authors [8]-[ lo], [ 131 discuss confidence inter- vals for yield estimates. Winter and Cook [8] assume that the underlying distribution of defect densities follow a mixed Gamma-Poisson distribution and use a chi-square approximation to determine confidence interval estimates for expected yield values. Foard Flack [9] also assumes a mixed Gamma-Poisson distribution of defect densities and builds from Stapper’s negative binomial model. How- ever, rather than developing interval estimates, she esti- mates the variation in the Gamma distribution parameters and assumes that large sample sizes will minimize that variation. Dimitrijev et al. [ 101 use the binomial approx- imation, where the variance s2 of the distribution is a function of the mean, to estimate yield variance. Knowing variance allows calculation of control limits as in (4). Kaempf [13] uses a Poisson distribution to develop nomograms of yield confidence limit curves for various sample sizes. Confidence interval estimates accelerate learning curve progress by allowing yield management to focus on problems rather than chasing normal process variation.

V I . IMPLEMENTATION EXAMPLE

The improvement cycle using yield modeling can be illustrated with an example. Yield improvement efforts at SEMATECH use yield models to estimate defect-limited yield using information from three sources. The first defect-limited yield estimate used actual equipment PWP. An equipment level yield model similar to (3) was imple- mented, using the initial processing sequence and actual equipment PWP measurements from a Tencor Model 5500.

The second defect-limited yield estimate used in-pro- cess inspection results to estimate defect-limited yield. A fine-grained yield model similar to (2) used inspection re- sults to estimate defect-limited yield. The third estimate

1 - Failure Analysis

+ Eguipmsnt PWP

+ Process PLY I 8 Short Loop

1

f P \ @

Normalized Yield

Fig. 4. Defect-limited yield distributions from yield models

of defect-limited yield used results from short-loop defect monitors to estimate zone defect density. Since short-loop monitors are designed with the same geometries as pro- duction devices, they can also validate fault probability estimates. The same yield model is used, but care must be taken in obtaining zone defect density estimates as short-loop monitors may include multiple zones. For ex- ample, a parallel plate capacitor will require three pro- cessing zones to deposit and pattern the lower plate, the dielectric, and the upper plate, while an interdigitated comb can be defined in one processing zone. Common geometries a!low correlating zone defect density esti- mates from short-loop monitors to production devices.

Defect-limited yield estimates from equipment PWP, in-process inspections, and short-loop monitor results may be compared with failure analysis characterization results from completed devices for validation. In failure analysis, wafers with electrically identified failure locations are se- lectively delayered to determine failure cause, separating actual yield into defect-limited and nondefect-limited yields. Fig. 4 compares normalized yield distribution curves. The curves are normalized by using the mean and standard deviation of the actual observations and forecasts to generate normal distribution curves. Differences be- tween the yield model curves and the actual defect-limited yield curve indicate the presence of systematic or nonran- dom problems. For example, the difference between ac- tual and the in-process inspection model curve may indi- cate the presence of particle detection problems with the inspection tools. The difference between actual and the short loop model curve results from not including all of the process zones in the short loop model. Finally the equipment PWP model is different from actual because equipment PWP measurements do not always include pro- cess chemicals and gases.

The effect of the improvement cycle on accelerated learning is illustrated in Fig. 5. These curves plot learning cycle length, the median time between lot stan and the availability of feedback test results. As expected, short loop monitor lots have shorter learning cycles than full flow product lots. The cumulative effect of accelerated

in

DANCE AND JARVIS: USING YIELD MODELS TO ACCELERATE LEARNING CURVE PROGRESS

1

Median Length

Y * + Short Loop Monitor

1

#

+ +

Month

Fig. 5. Learning cycle length.

learning is also shown as the length of the learning cycle is generally decreasing with time.

This example shows how the improvement cycle uses yield models to address process and equipment problems. Fine-grain, detailed models use information from many sources to estimate defect-limited yield. Comparing de- fect-limited yield estimates to electrical test and failure analysis results indicates the presence of nonrandom de- fects. Short-loop monitors accelerate the learning cycle by allowing parallel improvement efforts in different pro- cessing zones. Estimating yield confidence intervals fo- cuses improvement efforts on significant problems rather than chasing normal process variation. Further feedback comparing actual product yields to estimates from in-pro- cess inspection, equipment PWP, and short-loop monitors will fine-tune the yield model and process measurement methods.

VII. CONCLUSION Learning curves describe the relationship between unit

cost and cumulative volume. But increased production does not automatically cause unit price reduction as the learning curve implies. Unit prices are reduced by apply- ing knowledge gained through increased production for continuous improvement; the result of the improvement cycle.

Yield models estimate defect-limited yields by relating integrated circuit yield to circuit and process parameters. The relationship between observed defect density and ex- pected yield allows incorporating yield models in the im- provement cycle. The process improvement cycle can be accelerated by using fine-grained analysis and models, us- ing short-loop defect monitors for rapid feedback and si- multaneous development of process modules and equip- ment, predicting defect-limited yield from equipment characteristics, and estimating statistical confidence inter- vals about yield model predictions. Defect density infor- mation from process zones, entered into a fine-grained yield model, estimates yield. Confidence intervals about

111

the yield model estimates can indicate the presence or ab- sence of nonrandom, systematic process defects. Thus, using yield models in an improvement cycle accelerates learning curve progress.

ACKNOWLEDGMENT The authors are grateful for the support of SEMA-

TECH Manufacturing Methods technicians and engi- neers. Special thanks to T . Parikh and G . Dempsey for the PWP study, W. Connor for statistical support, and P. Calhoun, A. Machiewicz, and S. Pearce for management encouragement.

REFERENCES

[I] J . A. Cunningham, “Using the learning curve as a management tool,” IEEE Spectrum, pp. 45-48, June 1980.

121 W. E . Demming, Out of the Crisis. Cambridge, MA: Massachusetts Institute of Technology, Center of Advanced Engineering Study, 1986, p. 88.

[3] C. H. Stapper, “Fact and fiction in yield modeling,” Microelectron. J., vol. 20, no. 1-2, pp. 129-151, 1989.

[4] R. M. Lea and H. S. Bolouri, “Fault tolerance: Step towards WSI,” IEE Proc., vol. 135, Pt. E, no. 6 , pp. 289-297, Nov. 1988.

[5] C. H. Stapper et a l . , “Evolution and accomplishments of VLSI yield management at IBM,” IBM J. Research and Develop., vol. 26, no. 5, pp. 532-545, Sept. 1982.

161 R. A. Maeder, F. W. Oster, ahd R. J . Soderman, “Semiconductor and integrated circuit device modeling,” U.S. Patent 3,751,647, 1973.

[7] V. Ramakrishna and J. Hanigan, “Defect learning requirements,” Solid State Technol., pp. 103-105, Jan. 1989.

[8] C. L. Winter and W. L. Cook, “Interval estimates for yield model- ing.” lEEE J. Solid-state Circuits, vol. SC-21, no. 4 , pp. 590-591,

~~

A i g . 1986.

J. Solid-State Circuits, vol. SC-21, no. 2, pp. 362-365. Apr. 1986. [9] V . Foard Flack, “Estimating variation in IC yield estimates,” IEEE

..

[ lo] S. Dimitrijev, N. Stojadinovic, and Z. Stemenkovic, “Yield model for in-line integrated circuit production control,” Solid-State Elm- tron., vol. 31, no. 5, pp. 975-979, 1988.

[ I l l D. M. H. Walker, Yield Simulation for Integrated Circuits. Hingham, MA: Kluwer, 1987, pp. 149-156.

1121 W. S. Messina, Statistical Quality Control for Manufacturing Man- agers.

[ 131 U. Kaempf, “Statistical significance of defect density estimates,” IEEE Proc. Microelectronic Test Structures, vol. 1, no. I , pp. 107- 113, Feb. 1988.

New York: Wiley, 1987, pp. 58-64.

Daren L. Dance received the B.S. degree in en- gineering in 1974 from Idaho State University, Pocatello.

He is a member of the Modeling and Analysis technical staff at SEMATECH, Austin, TX. where he is responsible for defect-limited yield model- ing. He is a mentor to the SEMATECH Centers of Excellence at Texas A&M University and Flor- ida Institute of Technology. Prior to joining SEMATECH, he was a staff engineer with Gould AMI Semiconductor, Pocatello, ID, (formerly

American Microsystems, Inc.) where he developed yield improvement and manufacturing methods. While at Gould AMI he also participated in de- veloping and implementing manufacturing cost models.

46 IEEE T R A N S A C T I O N S O N S E M I C O N D U C T O R M A N U F A C T U R I N G . VOL S. N O I . F E B R U A R Y l Y Y 2

Richard W. Jarvis received the B.S . degree in chemical engineering from the University of Flor- ida, Gainesville, in 1978.

He is the Yield Improvement and Modeling senior engineer at AT&T Microelectronics, Or- lando Plant. He wah at SEMATECH for a 2 year assignment during 1989 and 1990. His current re- sponsibilities include identifying current and fu- ture yield improvement opportunities in manufac- turing and development using yield modeling and to support defect density planning. While at

SEMATECH, hia was Yield Management Department Manager. He con- tinues as an industry mentor to the SEMATECH Center of Excellence at the Florida Institute of Technology and their work in modeling. In 1978, after graduating college, he worked at Intel Corp. for six years. In 1984 he moved to AT&T, contributing to his second manufacturing facility startup as a senior process technologist. then later as a member of the product engineering team. Now back at AT&T. he is focusing on advanced defect detection and using current manufacturing data to find yield improvement opportunities through modeling.